It may be one of the best equipped system-development labs on Earth, but it’s largely used to create designs that aren’t used on this planet.

By Ann Steffora Mutschler

As individual blocks of IP in an IC design grow to more than 1 million gates, making sure each block functions reliably and interfaces with the system properly is a make-or-break scenario for many companies.

For one thing, getting it right is absolutely critical as the semiconductor industry reaches its maturity point with margins harder to reach. Coupled with an industry-wide downturn, even the largest IDMs are looking outside their internal teams for non-differentiated IP, which is standardized physical IP that is not a differentiator in a design.

“One of the factors that this economy will generate is more outsourcing of IP, which has been a very significant trend over the last several years, with the largest IDMs outsourcing a significant amount of IP,” says John Koeter, VP of marketing for IP solutions at Synopsys Inc., who notes that 17 of the top 20 semiconductor companies in the world buy IP from Synopsys. “So it’s pretty significant. And this includes digital and mixed signal IP that historically has been something large companies have viewed as a core competency,”

He believes the strong movement toward outsourcing, especially interface IP such as USB, DDR, PCI and SATA, is occurring because those types of IP are hard to design and are getting more complex. However, he points out, they don’t fundamentally differentiate a design.

In addition to outsourcing, consolidation in the overall semiconductor industry has been a major driver in IP industry consolidation, says Brani Buric, executive VP of marketing at Virage Logic.

Buric defines physical IP as IP that resides close to the silicon, including all kinds of digital IP, analog IP, memories, logic and high-speed interfaces. “With every new process node, complexity of reliable development and quality assurance for physical IP is becoming more and more expensive, and more and more timing critical. With physical IP, the key criteria of consolidation is that the barrier to entry of new players in the commercial market is very high because the cost of development and silicon validation,” Buric explains.

A second type of IP can be labeled system-level or RTL-level IP, which includes microprocessors. “Here,” he says, “the situation is different because there are a couple of fundamental blocks like microprocessors where there is market separation around a few companies that are leading in certain applications.” Also in this category are blocks that have a definite market window and thus a short lifetime, such as WIMAX and Bluetooth.

That said, with cost as king, semiconductor and systems companies are squeezing expenses and redeploying their engineers from non-differentiating tasks to more core-differentiating tasks.

Who’s buying whom?

To support the outsourcing, IP providers have made a number of consolidating moves over the past several years aimed at streamlining the IP delivery process and improving reliability for customers.

Most notably, IP industry leader ARM bought Artisan, while rival MIPS acquired Chip Idea.

Synopsys has made a number of acquisitions over the last four or five years, including InSilicon, which added PCI and USB to the company’s IP portfolio. Next, the company acquired Accelerant Networks for high speed, mixed signal CERTES capabilities, followed by Mosaid, Cascade and others.

Meanwhile, Virage purchased Ingot Design Systems for its DDR capabilities and Impinj for multiple time programmable memory.

Other players, like Mentor Graphics Corp. have scaled their investments in the IP space back, although still engaging with existing customers, according to Bill Martin, general manager of Mentor’s IP Division.

It is widely agreed that this consolidation will continue and will be of benefit to customers.

Tom Lantzsch, VP of Arm’s PIPD Division, says the semiconductor industry is hitting its maturity point, and like other industries that hit their maturity point there are fewer opportunities.

“From that perspective, this entire consolidation process is going through a natural evolution that most industries go through,” Lantzsch says. “Combined with the fact that the complexity of the products that we are asked to service our customers with are increasing rapidly, there is a corollary that they cost much more for us to develop. Based upon the IP business model that most companies use that has an upfront licensing fee and royalties, to get that investment back unfortunately takes much longer than most of us want to think about.”

What does this mean to customers? “In many cases, an improvement,” he says. “Our customers are becoming more global. The demands of supporting them are increasing. Incrementally, they have design centers working on products in multiple regions of the world. And even if they procure IP in one place, they may be using it in several. The ability to support them on a global basis is a key driving point. I don’t believe they’ve lost anything from a technical capability [due to consolidation] and they’ve probably gained in their ability to get support and investment on these products on a global basis.”

Further, the number of products that ARM brings out on a 32nm design platform versus at 180nm is approximately five times larger. Those products also are supported under a common EDA framework of all the major tool vendors, and they have been tested so the interoperability issues that historically drove customers to choose multiple vendors have been minimized.

Synopsys is seeing a similar trend for both technical and business reasons. “We’re seeing a huge push from our customer base in this direction,” Koeter says. “Buying IP is complex. There is a long technical process to evaluate a particular piece of IP, negotiating the business terms especially around things like warranty indemnification tends to be very difficult. And if you buy multiple pieces of IP and they don’t work together, you start to get finger pointing.”

For those reasons, as well as purchasing power, customers are trying to consolidate their IP vendors because IP is a volume-based business, wherein the more you buy the better discount you get. “They just have to put one legal contract in place, then can evaluate IP methodologies and apply them to future purchases so they don’t have to go through a detailed benchmark every time. They can buy in bulk and they get favorable payment terms. Typically a lot of our contracts are three year contracts and they are structured as IP VPAs, so customers commit a certain amount of dollars to us and in return get very favorable business terms and get to spread their payments over the duration of that contract,” he says.

Virage’s Buric believes reliability definitely rises with consolidation and is driving more careful choices on IP purchases. “It is becoming epidemic to see people being very conservative about quality because the cost of failure is too high. The cost of redesign has two components. One is tangible, which can be a couple of million or tens of millions of dollars. Or the intangible, like missing a market window, which is basically irrecoverable damage.”

For those reasons, end users are looking very carefully to avoid any damage from usage of unreliable IP components.

Foundries in the IP game

As semiconductor foundries have an interest in manufacturing chips with reliable IP, they have begun providing a limited set of pre-verified physical building blocks to coincide with advanced process development.

ARM’s Lantzsch recognizes that in some cases, a foundry would be viewed as a competitor, but stresses that very few foundries actually provide IP, and understanding why they do it is key.

He notes that historically the business model for Artisan (now part of ARM) was to service smaller companies largely on older technology nodes or more mature technology nodes, and market penetration for ARM/Artisan in those spaces is strong. “With that being the case, we weren’t really involved in early technology development at all,” he admits, but ARM now believes it is critically important as it moves on to the next class of customers, which are tier-one companies. Those larger companies are beginning to face some of the same challenges that fabless ASIC vendors have had in the past, where they don’t want to develop things that don’t add differentiation.

“It’s made us have to accelerate our technology road map significantly. What that means is bringing up the libraries in parallel with the process development. When we weren’t doing that, the foundries needed to do that,” Lantzsch says.

Still, ARM maintains strong relationships with a number of foundries including TSMC and the Common Platform. In fact, ARM and the Common Platform announced last September that ARM will develop and license a comprehensive physical IP design platform meant to help customers achieve optimal power, performance, and area for current and future ARM Cortex processors.

“We’d been working with them well in advance of that announcement on how to get the most out of the litho and creating the most density in the cells, what the tradeoffs are between design rules and standard cells and how does that then impact, in our case, ARM system performance on the CPUs. And that iterative process early on as part of process development, we believe is critically important,” he said of the close collaboration between the companies. The IDMs were used to doing that for years – they did that themselves internally. So for us to be able to address that market, we had to replicate, in many cases, what they were doing. Of the foundries that predominantly offer libraries, a significant reason to do so is largely this issue. They need to do that as part of their process development, and driving things even into the EDA space like routing technologies. It’s that iterative process on the advanced technologies that there’s a need to do that and if it’s not satisfied by a third party partner, then they were forced to do it themselves.

With IP consolidation to continue, closer partnerships and better reliability will be the result, with users ultimately benefitting from the activity.

By Pallab Chatterjee

The tightening worldwide economy finally has forced the consumer products arena to adopt an aggressive single-SKU mentality for their products. This means companies are now making a single standard product that can be sold into multiple applications.

This marks a radical shift in the way products are being designed, a direction that makes the design and development process far more efficient. Already, this approach has begun making its way into flat panel TVs, mobile appliances and radios, with common designs that are targeted for the United States, Europe, Australia, and Asia. All of these products are platform designs that are firmware-programmable.

Two of the companies with major products on display this year at the Consumer Electronic Show that highlighted this approach were Xcieve and Imagination Technologies. Xcieve is a semiconductor company shipping standard product ICs to OEMS with a firmware development toolset. Imagination Technology is an IP core licensing company that also completes the design chain by providing reference designs and full application development software.

Xcieve makes a monolithic 0.18um SiGe single chip tuner for flat panel TV and PVR applications. What makes this interesting from a system-level design standpoint is that most of the other products on the market are traditional hybrid technology can tuners that are fixed-format, based on the wider variation component values. The other solid-state tuners typically utilize 0.25um SiGe technology and do not maintain enough performance margin to be adjustable for the different signal formats.

The new tuner (the XC5000) is DSP based, supports all major analog and digital broadcast standards worldwide, while minimizing the power requirements and component area. The small size makes the product advantageous for the new slim line LCD & Plasma displays as well as low profile PVR set top boxes. At this time the XC5000 has adopted by LG, Miele, Sony and others in their TV, combo TV/Monitor and PVR products.

All personalization for region of destination is done with a downloadable firmware routine rather than making component changes in the custom circuits. The chip has the ability to real-time monitor the incoming RF signal and dynamically adapt the output to produce a correct signal.

Imagination Technologies has both video and audio IP cores. The audio cores are proven in many designs by PURE, Bose, B&O, Philips, TEAC and Sony and support most of the DVB radio standards, as well the internet radio format model. These cores have an advanced firmware/software framework (called META AAF, or Advanced Audio Framework), which provides a comprehensive suite of audio codecs implementing all major audio formats including MP2, MP3, AAC, eAAC+, WMA, Dolby Digital, Real, plus audio post-processing tools. This is an application of the Imagination Technology META HTPP-Audio solution, which is made of IP blocks that include multi-threaded DSP cores, a customized Linux kernel, and a middleware application library in addition to the AAF product.

The company also released some multi-format HD display targeted multi-threaded PowerVR SGX543 core. This core brings high-performance shading and 3D graphics presentation to a large-format display, based on the same low-power, high-performance multithreaded cores that have been used on their mobile display cores. These cores are joined by a new frame grabber core, which provides for inter-frame generation for 240hz refresh rate applications on flat panel televisions. The use of multi-threaded DSP style cores, in these applications allows for in-application optimization through firmware such as optimizing the Flash 10 performance in browsers on MIDs (Mobile Internet Devices).

These cores and ICs are the new architectural direction of globally targeted semiconductors that are optimized for power and area. The targeting of “standards” such as dictated by the broadcast TV, radio and cell phone industries allows for companies to capitalize on their semiconductor design and manufacturing expertise rather than pushing the performance envelope beyond a usable limit. This trend is broadening in the industry as the communication standards solidify and more multi-function products (media servers, netbooks, graphics capture devices, etc.) enter the marketplace.

By Ed Sperling

It used to be considered axiomatic that chip companies would be rewarded for spectacular technology, reflected in the market value of their components and in their stock price. But with stock prices routinely getting hammered even before the downturn, many companies have begun to re-think their mission.

National Semiconductor, for one, is looking at creating modules rather than just chips in the future. Brian Halla, National’s chairman and CEO, said the perceived value is in the systems business, not semiconductors.

“When it comes to energy, 95 percent of the solution is from semiconductors,” Halla said. “It doesn’t make that much sense to sell chips. More and more it’s about module technology.”

This is a big shift for a company that made its reputation in having incredible numbers of components. And while the trend is not new, it is significant.

Stephan Ohr, an analyst at Gartner, said Texas Instruments got into this business years ago in power management when it bought a module maker in Chicago. “A lot of times, entrance into the business is through modules,” he said. “Then the question is how all the pieces get integrated.”

Ohr said the modular approach has become particularly attractive in such areas as voltage regulators. The best regulators are integrated modules that also can be more efficient, but the approach is also more expensive. That’s good for the companies selling the products, however, considering that average selling prices of some components in the future likely will not be high enough not enough to support the design and development of those components in places like North America, Europe and Japan.

That integration is becoming critical in all aspects of system-level design. A slimming down of design teams and companies, in general, coupled with tight market windows and growing complexity, mean that companies want far more integration than in the past—of everything from hardware to firmware, operating systems and applications. The latest semiconductor industry road map survey identifies this trend very clearly.

Successful IP vendors have been building off of this premise for years, because of the difficulty of getting individual blocks of intellectual property created by different companies to work well together. The problem is defining those blocks consistently enough so they can work in a plug-and-play fashion. Buying pre-integrated pieces is much more of a sure thing, which is reflected in the continued growth of the larger IP companies such as ARM, Virage Logic, Synopsys’ standard IP business and Denali’s verification IP, and the inability of smaller IP companies to make significant inroads.

While standards such as IP-XACT are supposed to ease the integration, the standard remains a leap of faith for companies that are extremely cautious about making wrong moves that could cost valuable time and potentially market windows for their products.

By Ed Sperling & John Blyler

For all the concern about 45nm chip development—and there have been a number of design investigations at that process node since the beginning of the year—the vast majority of activity is still at 130nm.

This is an indication of just how costly it has become to stay on the Moore’s Law road map—and how many companies have stopped trying to keep up. It’s also an indication of just how much life is left in the older process nodes. Since the beginning of the year, there have been more than 13,000 design investigations—trying out new tools, architectures and processes. Roughly 12 percent of those were at 45nm, with 60 percent at either 90nm or 130nm.

This has multiple implications for the industry, and particularly the fabless development model. While companies such as Broadcom, Qualcomm, Nvidia and AMD continue to live on the bleeding edge of the fabless world, the vast majority of chip developers have adopted strategies that either hang back one or two nodes or skip nodes entirely. Because of the expense of developing new chips, the number of chips that need to be sold to generate a profit has been steadily rising.

Within the foundry business, however, there have been two very distinct models. While companies such as TSMC, UMC and the Common Platform triumvirate of IBM, Samsung and Chartered Semiconductor continue to lead the pack to the next process node, that leadership comes at a very high price. Others, such as China’s SMIC, Israel’s Tower and Malaysia’s Silterra continue to erode their profits several nodes back where volume is significantly higher.

Joanne Itow, managing director for manufacturing at Semico Research, said the number of wafers processed at the leading edge continues to grow. That’s a function of how much volume is necessary to break even at advanced nodes. But Itow said that also translates into more foundry business at the leading edge than there was five years ago. Within that scenario, there also is more competition.

At the same time, she said 130nm remains popular for a variety of reasons: “It can be run with or without copper, on 200mm or 300mm wafers, and there is still a lot of capacity at 130nm. So the price is very competitive and it is not surprising that companies will continue to utilize that technology for a long time. As the price to manufacture declines, we (consumers) benefit from the new electronic applications that emerge. New designs at 130nm are taking advantage of the technology at very good price points.” Apple’s iPhone is only one example of new consumer designs that use 130nm technology.

For capital equipment makers, this isn’t particularly good news. Fewer foundries at the leading edge mean fewer sales. The abandonment of the 200mm fab equipment by memory makers has left a lot of used equipment for sale, said Itow. Big foundries have depreciated their equipment and remain competitive on pricing against second-tier foundries, but the overall effect on capital equipment sales is significant.

This also has implications for the EDA industry, although low-power design starts and a focus on business objectives versus raw performance could pry open a replacement market as well as drive new markets. As expected, the vast majority of design investigations occurred at 100MHz and 50MHz. Low power has become not only a mandate but an opportunity for chip developers, and many companies have begun developing multicore chips that run at lower clock speeds—or are using multiple chips at lower clock speeds.

Systems on chip, in particular, seem to be gaining momentum. Of all design activity, nearly 40 percent of those questioned used at least one block of non-memory IP, and some used more than 30 blocks. That figure is a strong indication of time-to-market pressures and the maturity of the IP industry, as well as an indication of how companies are crafting their chips.

Interestingly, the bulk of the lower clock speeds are being developed at older process nodes, not at the bleeding edge. Speed is still important, but as a selling point power is at least as important, if not more important. In fact, since January there have been only 23 investigations into chips running at clock speeds greater than 3GHz.

By region, most of the design activity occurred in North America. Asia, including Japan, saw only about one-fourth as much activity as North America in 2008. Despite all the startups in China and the preponderance of manufacturing there, the bulk of the design activity remains in North America. Asia was tied with Europe.

This online graduate course covers the essentials of systems engineering management and its critical interconnection to program/project management. Systems engineering is the integration of several engineering fields into an efficient and effective process for the overall technical management of programs and development of systems and products. Students will gain detailed knowledge in management techniques applicable to activities within Systems Engineering, including evaluating new technology, integrating legacy systems, trade-off studies, technical performance measurement, cost-effective process tailoring, technical reviews and audits, and others. Several case studies projects will be studied throughout the course to illustrate key concepts and management techniques

Professor: John Blyler

Class Begins: September 28, 2009

Class Ends:  December 6, 2009