By Clive “Max” Maxfield

System Level Design (SLD) is one of those terms that means different things to different people. For some, SLD is understood to refer to the process of capturing (and verifying) a complex ASIC/ASSP/SoC design at a high level of abstraction. Another term that we often hear in this regard is Electronic System Level (ESL) design.

Trust me, you don’t want to get me talking about ESL. A couple of years ago I wrote an opinion piece for a DAC newsletter entitled “What the hell is ESL?” You would be amazed at the number of folks who e-mailed me after reading that piece saying, “Thank goodness, I thought it was only me who was confused.” But we digress…

I absolutely agree that SoCs are going to get bigger and better (and scarier), and that companies like Cadence, Mentor, Magma, and Synopsys – along with all of the smaller EDA companies whose mission it is to create SoC design and verification tools – are going to continue to astound us with their latest and greatest offerings.

But I also have some problems with this. For example, very few products these days can justify the tens of millions of dollars it can cost to design and deploy a custom silicon chip. Another consideration is that when you create an SoC, your algorithms are effectively “frozen in silicon,” which can be extremely awkward when standards and protocols are continually evolving all around us.

One alternative is to use a Field Programmable Gate Array (FPGA) as the implementation platform for the design. Of course we all know that early FPGAs were logic limited, power-hungry, and generally not very interesting. But times have changed. Some FPGA families boast incredibly high capacity and high performance; others offer extremely low power; still others provide mixed-signal capabilities; and all offer configurable fabric that can be adapted to whatever tasks are required.

This doesn’t mean that FPGAs are suitable for every application, but they are currently appearing in all sorts of systems, from handheld, battery-powered units to supercomputers whose performance make your eyes water.

Another consideration is that future generations of electronic products will not be used as standalone devices. Instead, they will be intelligent elements in an interconnected ecosystem. As one rather obvious example, look at Apple’s iPod. When considered in isolation, this is only a vaguely interesting media-playing device. What has made the iPod so widely successful—especially when compared to its competition—is its associated media purchase and download ecosystems in the form of iTunes.

This type of “big picture” view increasingly will apply to products of all shapes and sizes. Consider a company that creates residential air conditioning units for example. Customers are certainly going to be interested to hear about new units that are more efficient, quieter and more powerful, but only to a point. What will really interest them is when their air conditioning system is augmented with connectivity features that allow them to monitor and interact with the system from anywhere in the world. Imagine, for example, returning from vacation, realizing that you have arrived in the middle of an unexpected heat wave, and calling your air conditioner from your car and instructing it to start cooling your home in preparation for your arrival.

Similarly, imagine a smart air conditioner that can communicate with its manufacturer and/or your service provider. If your air conditioner notices an unexpected vibration or a loss in performance, it could automatically log a request for a service before system failure occurs. (This would have been really useful at my house a couple of summers ago.)

What all this means is that “System Level Design” cannot simply focus on the development of a silicon chip in isolation. Instead, we have to work from the top down at a very high level of abstraction, starting by considering the user “experience,” the user interface, and the way in which this product is going to interact with the outside world. And only then should we actually start to think about the underlying implementation. Put another way, it’s important to decide just what it is we actually want to do, and then we can decide how to go about doing it.

The majority of today’s EDA environments are ferociously complicated, not the least that they require their users to learn special languages such as VHDL and Verilog. But a lot of folks who have really good ideas don’t know these languages and they don’t think like hardware design engineers. Wouldn’t it be better to make the tools more intelligent so that they can understand the languages favored by different users, such as C/C++, Java, Python, and so forth. I know there are some interesting C/C++ synthesis tools around, but a lot more could be done in this area.

As a somewhat related topic, it’s no longer sufficient to design the various parts of a product in isolation. That includes the FPGA, the circuit board on which it rides, the enclosure in which everything resides, and the firmware and software that run on the device. Instead, what is required is a unified environment in which everything can be developed and verified in the context of everything else.

Yes, the “big boys” in EDA have environments like this … but have you actually tried to use one? It’s hard enough to gain expertise in even a small portion of one of these environments. Running the entire thing with only a couple of people is well-nigh impossible. And then there’s the cost of all these tools.

The reason all of this is so important is that we are increasingly relegating product designs to fewer and fewer people that require incredible levels of training and expertise. This may work for the most complex SoC devices, but it is not a good way to go for the majority of products. What we need are solutions that will unleash the creative and innovative potential of a wide range of users. Instead of leaving things to technological experts, we need to empower new waves of users who can conceive world-changing ideas and products.

By Ann Steffora Mutschler

With the cost of failure at an astronomical high, the last thing chip designers want to worry about is the physical IP they will use to build their SoC.

In addition to less willingness on the customer’s behalf to take risks, complexity and economics have driven the need for more off-the-shelf IP and a corresponding rise in interest in verification IP. Compounding matters, IP investments are being stretched out for longer periods of time than in the past. That has made verification IP even more popular. Confidence in IP is critical, and this comes through a comprehensive IP validation discipline on the part of the IP provider.

However, the maturation of any method or tools means new focus on them, and so far the design industry has not even settled on what the optimal methodology should be for IP verification.

As a starting point, it helps to define types of verification. First, there is an intense level of unit-level verification where compliance to the relevant protocols is focused on and where the functionality of the block itself is detailed, said Mark Gogolewski, CTO at Denali Software. In addition, there is a separate step during which the subsystem or the system is constructed, with verification at this point being very different.

“For a time, there was a lot of IP verification when you had a bigger subsystem, but these days, the IP gets completely wrung out at the unit level and then when you construct the system, you are focused much more on connectivity and dataflow and how the system interacts,” he explained.

“If you are testing an IP block, there are two major dimensions of verification challenge. One is the protocols that are relevant to the IP block, and the other is the functionality, which is making sure the microarchitecture that was used to design the IP was correctly implemented,” Gogolewski said. “Correct” can have many meanings in terms of correct function and leading off performance objectives of that particular block of IP, he noted.

“Verification is all about observability and control. You need to make sure you are observing every aspect of the protocol, but then you have to give the customer control. One dimension for memories is giving easy control of the data space, and another is error injection and that’s another level of investment has to be made,” he added.

Carl Ruggiero president and CEO of Trilinear Technologies, agrees that common definitions of IP verification need to be established. “Depending on [a customer’s] point of view, everyone has a different idea of what verification ought to be, and that’s really making our job very challenging. Everybody says they want verification, but right now there is really no defined vocabulary for it. You cannot call it gates and flops like you can on the design side. People want to talk about coverage and percent of coverage, but at the same time coverage is very subjective. You can get 100% coverage with five coverage points. Therefore, it is hard to say what good coverage is because if you have 300 coverage points, you might be missing that 301^st, which is the critical one. How do we go about putting metrics on it? How do we define the vocabulary so we can all speak the same language? We struggle with this on a daily basis.”

In an effort to start out clearly with customers, Ruggiero says Trilinear talks about its verification in terms of functional coverage. “We talk about the actual things that we set out to do. We talk about garnering 100% functional coverage. While we don’t say that we’ve tested every ad nauseum combination of things, that for the things that our software drivers and reference drivers, the functions that are listed in the data sheet and in the specification, those are the ones we’ve tested to.”

IP Verification Challenges

Ken Brock, director of physical IP marketing at Virage Logic, said that when it comes to IP validation specifically for on-chip physical IP, challenges and solutions can include taking a standard cell library of more than 1,600 unique circuits and running them through one of several EDA vendors synthesis tools, running them again through the same or different EDA vendors’ physical synthesis/place and route tools and have them all work perfectly; taking a memory compiler with a dozen different knobs and switches and producing a fully functional memory IP over the number of words and bits with multiple aspect ratios, test options and power optimization configurations; mixing them together with other IP on an SoC; and doing all of these things over the full speed, voltage, temperature and process variability extremes of a specific leading edge silicon process.

He noted that the IP validation process requires a rigorous discipline, which includes unit validation, integration testing, platform validation and silicon validation.

Indeed, IP giant ARM is pursuing just that. Tom Lantzsch, VP of ARM’s Physical IP Division noted, “We spend a lot more time with the EDA partners integrating our IP under their flows much earlier and having them leverage it and test it themselves. It is a constant activity because when we do our verification, unlike an internal supplier, which probably has a limited EDA flow, and maybe even a limited customer set within their company, we have to be much more systematic and have to create a verification environment that supports us for multiple years.”

The Cost of Providing Verified IP

Whether making an investment into a new technology for entrepreneurial reasons or encouraged by major customers, the latter of which Denali did with its entry into the PCI Express arena, making it pay off is no small task both to the customer and for the IP provider.

As Gogolewski explained, with the company’s entry into PCI Express, “the world got a lot more complicated because it is extremely configurable, programmable and complicated. What we mean by configurable is that before you even put a design in silicon there are many choices. We have a couple hundred choices in our configuration spec just to correctly specify what that particular device even looks like at a specification level. It is programmable because it has all sorts of register settings that have to be set correctly and which can change the behavior of the device. And then it’s just complicated—our engineers had to become experts on two to three thousand pages of documentation. We had to make sure all the functionality was in there with the flexibility and programmability; we had to make sure all of those thousands of pages of spec became error checks and assertions. And then the way that [PCI Express] protocol works, your IP has to both handle correct functionality and incorrect functionality and respond properly. So there was a multitude of error injection that we had to make available to our customers as well as our own design team to make sure that they could inject all these levels of errors and validate whether or not their design caught it correctly.”

To deliver this level of backup data to customers for PCI Express, Denali estimates the extra engineering effort required is equal to approximately 70 to 75 man-years of effort over 7 years, with about 550,000 lines of new code created, not including the company’s Purespec library code.

The IP Verification Horizon

In the next phase of IP verification, one thing is for sure—there will be more of it provided by third parties.

“We’re at a tipping point from ‘make unless you have to buy’ to ‘buy unless you have to make,’ and the current economic climate is going to accelerate that. Basically the fundamental premise of third party IP is that if it is a ubiquitous problem and it is solved well, then the market is overall more efficient and better off when a third party solves it, rather than each customer solving it on its own,” Gogolewski said.

He also sees more IP verification moving toward third party IP vendors, even though there will always be customers that will create their own IP to maintain their place on the very bleeding edge of design. And he believes coverage-centric verification will be embraced. “It used to be something that leading-edge design teams would use, but now it is becoming ubiquitous,” he said.

David Patterson, Professor of Computer Science at UC Berkeley, presented his views to the Naval Postgraduate School about the prospects for multicore programming success. This video was excerpted from his presentation.

By Pallab Chatterjee

Some products literally sing out for attention—especially to system-level engineers.

At the recent Consumer Electronics Show in Las Vegas, several in particular were worth noting: the Gibson Dark Fire guitar, the Jones Audio PA-M300 amplifier and display products from Westinghouse.

Gibson in late 2007 introduced its first-generation auto-tuning guitar, aka the “robot guitar.” This was a standard Les Paul guitar that had an analog closed loop system to auto-tune the strings in a short period of time—less than 30 seconds—to either pre-programmed or custom configurations. This year the company introduced a significantly improved, high-speed analog closed loop tuning system—less than 2 seconds, this time—for a similar Les Paul guitar that supports a digital recording interface to Macs and Windows.

The new system improves the feedback loop performance by using low-power higher-bandwidth amplifiers, faster-settling PZTs and servos for the tuning knobs and different pickups. The new system offers overall improved performance at approximately the same price point, while supporting a better power cycle and electronics recording interface. This new technology is dramatically improved in playback and performance capability over “digital” sampling and modeling guitars.

The Dark Fire plays with the same robustness and tone as a standard Les Paul guitar without the auto-tune feature. This solution has been implemented as an advanced “continuous time analog” application, bucking the trend to go with sampled data and a DSP application.

The Jones Audio amplifier, meanwhile, is part of the niche world of high-performance audio. Unlike the majority of products in this space, however, this is not a vacuum tube amplifier. Instead it uses solid-state power devices to drive the 300W+ on the outputs. What made the product standout was the system-level design and analysis that yields an over -120db noise floor. This is the result of both electrical and magnetic isolation of the power supply path from the signal drive circuitry. The design was validated initially with design software to achieve the standard performance. The increased performance was found using traditional engineering bench and application testing to improve performance as the modeling information available for the board and semiconductor design was not sufficiently details to support this level of performance.

The audio performance difference between typical 90db SNR and the 120db+ SNR is easily discernable and truly audible when listening to most music styles. As anyone who works with power supply and amplifier design is aware, the 100db+ SNR world is a rare and unique space, especially in high-power applications.

Westinghouse, meanwhile, has been a well-known brand in the U.S. electronics market for many decades. The company just recently introduced some 19-inch to 32-inch LCD flat panel TVs for the standard 720 and 1080 consumer markets. Interestingly, Westinghouse targeted them at the commercial and industrial markets. In an effort to support the high-resolution/high-definition marketplace, the company demonstrated a 4K flat-panel display. This product was primarily targeted to the 4K and 2K editing marketplace for content creation and for very high performance commercial video applications. It was one of only two 4K displays that were operating and shown at CES, the other being from Sony.

Westinghouses offering was an interesting system application because a large number of the components were shared with the standard lower ASP consumer model displays and utilized a similar user interface.

Westinghouse also showed off some new software for digital signage. As a hardware provider, this product was historically bundled with the displays to support advertising insertion, display scaling and other effects on a windows platform driving the display along with the video feed. As the market has progressed, product was modified to be display manufacturer-independent and hardware-independent, so these advanced video-imaging features can be used on standard PCs with any 720 or 1080 displays. This was one of the few instances where a hardware company became aware of market drivers for their GUI and application base and chose to provide a solution (be it software or software and hardware) to the client base rather than stick with their traditional hardware-only model.

By Cheryl Ajluni

In spite of all of its hype, WiMAX is not the only standard causing a stir these days or being called a “killer app.” Another technology that has achieved this illustrious title is Long Term Evolution (LTE), the Third Generation Partnership Project’s (3GPP’s) air interface for wireless access.

Granted, WiMAX does have the advantage of a head start in development, testing and deployment, but LTE is gaining momentum. According to a new ABI Research report, more than 18 operators globally have announced LTE deployment plans, and the tough economy seems to have done little to dampen their enthusiasm. Verizon accelerated its LTE deployment timetable, moving its launch forward from 2010 to 2009. NTT also is likely to deploy LTE in Japan in 2009. By 2013, operators are expected to spend over $8.6 billion on LTE base station infrastructure alone.

The difficulty with these projections is that LTE is an evolving technology (e.g., its MAC and upper layers are still be finalized) and therefore subject to change and interpretation. Specifications for the LTE radio interface are stabilizing, but this uncertainty leaves room for error and further complicates an already challenging design and test process. Nevertheless, chipsets, infrastructure and devices currently are being developed for commercial launch. Much of the pressure for successful development falls to the system-level engineer, who must accurately and cost-effectively design and test for the moving target that is LTE. How can this goal be achieved? Let’s take a closer look.

Understanding the Options

While LTE is expected to offer both consumers and operators a number of key benefits (e.g., lower costs, better services and an increase in data rate with lower latency), the complexity resulting from its use of technologies like SC-FDMA in the uplink, multiple antenna configurations and OFDMA, presents a host of engineering challenges to the engineer. LTE’s variable channel bandwidths further add to this complexity. Challenges also stem from the dependence of LTE system performance on its baseband and RF subsystems, both of which are subject to impairments like nonlinearities, multi-path and fading.

Dealing with this complexity and the resulting challenges is no easy task. As Frank Ditore, product marketing manager at Agilent Technologies points out, “For the system-level engineer working with LTE, or any emerging technology for that matter, there is simply nothing to validate their designs against. There is no LTE base station against which a designer can test their handset design. So, right from the very beginning the engineer faces uncertainty.”

Anritsu offers a solution to this dilemma. Its new MD8430A Signalling Tester is intended for developers who want to verify the operation of a new LTE terminal, but are unable to connect to an actual base station. As a base station simulator, this solution offers the functions needed to test the performance of 3.9G mobile terminals supporting the LTE standard.

What are some of the designer’s other options? The first alternative is to guess. In this case, the engineer builds a device with LTE functionality and hopes the design is correct. If the device was not designed properly, the engineer would unfortunately not realize this until after the design was fabricated. The design would then need to be fixed and fabricated again—a costly and time consuming process and one that’s not likely to receive much support given the current economic situation.

The other alternative is to use early design solutions with algorithms created by a company that’s closely involved with the LTE specification. Granted these solutions and the algorithms on which they are based will not be perfect as LTE is not yet finalized, but they do increase the engineer’s confidence that his/her design is correct. Over time these algorithms will become more mature and the design solutions that employ them will likewise mature, further raising the engineer’s confidence. And, since algorithms used in early design solutions ultimately find their way into measurement solutions, test equipment like signal analyzers, signal generators and network emulators that employ these algorithms also will be mature. Using design tools and measurement solutions from the same company is one way to ensure access to the most mature algorithms.

Agilent Technologies is one company offering solutions that span the entire LTE development lifecycle. In addition to its Advanced Design System (ADS) and the ADS Wireless LTE Library for design simulation and verification, the company also offers a range of pattern generators, logic analyzers, signal generators, signal analyzers, and network emulation and protocol development tools—all of which support early R&D in components, base station equipment and user equipment.

Successful Design And Test

Regardless of which company’s design and test solutions that are used, there are a few key tips for the engineer to keep in mind:

1. Design simulation can be a valuable ally in addressing LTE development challenges and in verifying the engineer’s interpretation of the LTE standard. Its uses are multi-purpose: enabling the engineer to perform system-level trade-offs early in the design cycle to determine design requirements and specifications, and enabling evaluation of the system’s RF/mixed-signal performance by simulating RF and baseband designs together in one simulation environment. Additionally, combining design simulation with test equipment provides added flexibility in addressing testing needs for LTE.

   One solution capable of enabling such functionality is Agilent’s SystemVue 2008 (see Figure 2). This new electronic design automation platform provides an easy-to-use environment with simulator and modeling technologies, along with links to hardware implementation and test. It allows algorithm creation and prototyping for challenging communications system architectures at the physical layer. It also bridges the design flow gap between algorithm developers and the mainstream design community and lowers the cost of ownership by unifying a disjointed flow at an affordable price.

2. For design and test accuracy, select tools from a company with known good algorithms and models.

3. Consider purchasing design automation tools and measurement solutions from the same company, as its algorithms will become much more mature as they trickle down from design automation tool to measurement solution.

4. Foster a close working relationship with the company from whom you purchase design tools and/or measurement solutions. You want to know what your vendor is doing to address changes in the LTE specification and that they are fully committed to making updates to their solutions, as necessary, in a quick and efficient manner.

5. According to Andrew Kodarin, business development manager, Anritsu, another key tip is to “verify that the solutions you purchase are future proof and will preserve your investment.” In other words, ensure that the tools can be expanded to support future developments in the standard and that you won’t have to buy a new solution every time the specification changes.

Summary

There is no denying the current buzz surrounding LTE. Despite this, its true test will come on the first day of its commercial launch, when user’s expectations will be at the highest. How well LTE can meet those expectations will ultimately determine its long-term success. Much of this burden will fall to the system-level engineer tasked with designing and testing LTE devices. While some uncertainty in this process is inevitable given the changing nature of the standard, some tips (e.g., using design simulation with known, good algorithms and models) can prove especially useful in helping the engineer achieve a successful design.

By Pallab Chatterjee

The tightening worldwide economy finally has forced the consumer products arena to adopt an aggressive single-SKU mentality for their products. This means companies are now making a single standard product that can be sold into multiple applications.

This marks a radical shift in the way products are being designed, a direction that makes the design and development process far more efficient. Already, this approach has begun making its way into flat panel TVs, mobile appliances and radios, with common designs that are targeted for the United States, Europe, Australia, and Asia. All of these products are platform designs that are firmware-programmable.

Two of the companies with major products on display this year at the Consumer Electronic Show that highlighted this approach were Xcieve and Imagination Technologies. Xcieve is a semiconductor company shipping standard product ICs to OEMS with a firmware development toolset. Imagination Technology is an IP core licensing company that also completes the design chain by providing reference designs and full application development software.

Xcieve makes a monolithic 0.18um SiGe single chip tuner for flat panel TV and PVR applications. What makes this interesting from a system-level design standpoint is that most of the other products on the market are traditional hybrid technology can tuners that are fixed-format, based on the wider variation component values. The other solid-state tuners typically utilize 0.25um SiGe technology and do not maintain enough performance margin to be adjustable for the different signal formats.

The new tuner (the XC5000) is DSP based, supports all major analog and digital broadcast standards worldwide, while minimizing the power requirements and component area. The small size makes the product advantageous for the new slim line LCD & Plasma displays as well as low profile PVR set top boxes. At this time the XC5000 has adopted by LG, Miele, Sony and others in their TV, combo TV/Monitor and PVR products.

All personalization for region of destination is done with a downloadable firmware routine rather than making component changes in the custom circuits. The chip has the ability to real-time monitor the incoming RF signal and dynamically adapt the output to produce a correct signal.

Imagination Technologies has both video and audio IP cores. The audio cores are proven in many designs by PURE, Bose, B&O, Philips, TEAC and Sony and support most of the DVB radio standards, as well the internet radio format model. These cores have an advanced firmware/software framework (called META AAF, or Advanced Audio Framework), which provides a comprehensive suite of audio codecs implementing all major audio formats including MP2, MP3, AAC, eAAC+, WMA, Dolby Digital, Real, plus audio post-processing tools. This is an application of the Imagination Technology META HTPP-Audio solution, which is made of IP blocks that include multi-threaded DSP cores, a customized Linux kernel, and a middleware application library in addition to the AAF product.

The company also released some multi-format HD display targeted multi-threaded PowerVR SGX543 core. This core brings high-performance shading and 3D graphics presentation to a large-format display, based on the same low-power, high-performance multithreaded cores that have been used on their mobile display cores. These cores are joined by a new frame grabber core, which provides for inter-frame generation for 240hz refresh rate applications on flat panel televisions. The use of multi-threaded DSP style cores, in these applications allows for in-application optimization through firmware such as optimizing the Flash 10 performance in browsers on MIDs (Mobile Internet Devices).

These cores and ICs are the new architectural direction of globally targeted semiconductors that are optimized for power and area. The targeting of “standards” such as dictated by the broadcast TV, radio and cell phone industries allows for companies to capitalize on their semiconductor design and manufacturing expertise rather than pushing the performance envelope beyond a usable limit. This trend is broadening in the industry as the communication standards solidify and more multi-function products (media servers, netbooks, graphics capture devices, etc.) enter the marketplace.

By Ed Sperling

One of the strange things about downturns is they force companies to re-examine what they do and question what kind of value they bring to the market. This is particularly true in the semiconductor world, where the average selling prices for chips has been sliding for the better part of two decades.

In the case of the chip industry, which is heavily cyclical, that leaves lots of time for reflection. And the latest trend seems to be somewhat different than the last downturn, which produced, ‘Do more with less.’ The current direction seems to be, ‘Do much more,’ although not necessary with less.

“Companies have to deliver whatever they were delivering before plus more value,” said Ian Mackintosh, president of OCP-IP. “For IP vendors, they need more software content—drivers, broader connectivity and more validation of the process they use. For EDA providers, they need more offerings. There will be a lot of fallout as a result of this downturn, and people will make acquisitions they couldn’t make a year ago. Products will get into a stronger sales channel. This is the classic integrate or die. Consolidation will do that for them.”

But there are two inherent business problems that have to be solved before system-level design can extract more value for its efforts. The first is a broader definition of exactly what’s involved in designing and developing a system rather than just a chip.

“EDA has to become the general contractor for design,” said Jim Hogan, a private investor in the technology world. “If you’re building an SoC, you’re most likely creating platforms for a vertical market using third-party IP and your own secret sauce. The problem is verification. You can’t run it with the application.”

That helps to explain some of the recent acquisitions and changes under way within the semiconductor tools world. Synopsys, for one, bought Synplicity for its FPGA tools and part of ProDesign to move into ASIC prototyping and verification. As Synopsys CEO Aart de Geus said, “All trends that existed before the downturn have not changed.”

De Geus noted that in the future, makers of semiconductors will have to deliver embedded software and even applications, which is the reason behind acquisition of prototyping companies like Virtio. “Everyone would like to have the chip before the software and they want to have the software before they have the hardware. These two statements may sound like contradictions, but increasingly they’re not.”

The other piece of the equation that needs to be ironed out is complexity. That helps explain Mentor Graphics’ intense focus on TLM 2.0, which is basically black-box technology to speed design across multiple areas. IP-XACT, which is aimed at making IP more plug-and-play, fits squarely into the TLM 2.0 world, as well.

Standards become stronger in dowturns because there are fewer dollars available for developing new technology. Most R&D budgets are flat to down. Even de facto industry standards, which typically precede the adoption of technology by standards bodies, grow stronger in a downturn because there is less money to challenge them.

“If you look at the systems space, ARM is the de facto standard in the wireless world,” said Hogan. “In the interconnect space, Sonics and Arteris are making a play, and the interconnect strategy will become important. It also will be important to have IP that works together. Chip Estimator is like the yellow pages of IP and IPExtreme is repacking silicon process IP blocks, but so far no one has a total solution.”

The same challenge persists in the software world. There is no uniform test bench strategy, so far, and application software is not part of that entire process. “Right now we have articulation points in software signoff, but with the application all we have is intent verification,” Hogan said.

In system-level design, the real mantra might literally be to think outside the box. Chris Rowen, founder and CTO at Tensilica, said the value in devices isn’t what’s in the box, but how it works on the network.

“It’s all about what it enables,” Rowen said. “When they put it on their customers table it has to now all the protocols and standards used by the end consumer, no matter what market it’s in. Chips need to know what the home services look like.”

And for the companies that design chips, or which create the tools to design and develop them, the end of the downturn could be a rather rude awakening to the new rules of the game.

AI used to be the stuff of science fiction, but cheap processing power and storage has made it a reality. To find out what’s being developed, System-Level Design (www.chipdesignmag.com/sld) tracked down Rachel Goshorn, assistant professor of System Engineering at the Graduate School of Engineering and Applied Science in the Naval Postgraduate School in Monterey, Calif. Check out what she has to say.

By Ed Sperling

It used to be considered axiomatic that chip companies would be rewarded for spectacular technology, reflected in the market value of their components and in their stock price. But with stock prices routinely getting hammered even before the downturn, many companies have begun to re-think their mission.

National Semiconductor, for one, is looking at creating modules rather than just chips in the future. Brian Halla, National’s chairman and CEO, said the perceived value is in the systems business, not semiconductors.

“When it comes to energy, 95 percent of the solution is from semiconductors,” Halla said. “It doesn’t make that much sense to sell chips. More and more it’s about module technology.”

This is a big shift for a company that made its reputation in having incredible numbers of components. And while the trend is not new, it is significant.

Stephan Ohr, an analyst at Gartner, said Texas Instruments got into this business years ago in power management when it bought a module maker in Chicago. “A lot of times, entrance into the business is through modules,” he said. “Then the question is how all the pieces get integrated.”

Ohr said the modular approach has become particularly attractive in such areas as voltage regulators. The best regulators are integrated modules that also can be more efficient, but the approach is also more expensive. That’s good for the companies selling the products, however, considering that average selling prices of some components in the future likely will not be high enough not enough to support the design and development of those components in places like North America, Europe and Japan.

That integration is becoming critical in all aspects of system-level design. A slimming down of design teams and companies, in general, coupled with tight market windows and growing complexity, mean that companies want far more integration than in the past—of everything from hardware to firmware, operating systems and applications. The latest semiconductor industry road map survey identifies this trend very clearly.

Successful IP vendors have been building off of this premise for years, because of the difficulty of getting individual blocks of intellectual property created by different companies to work well together. The problem is defining those blocks consistently enough so they can work in a plug-and-play fashion. Buying pre-integrated pieces is much more of a sure thing, which is reflected in the continued growth of the larger IP companies such as ARM, Virage Logic, Synopsys’ standard IP business and Denali’s verification IP, and the inability of smaller IP companies to make significant inroads.

While standards such as IP-XACT are supposed to ease the integration, the standard remains a leap of faith for companies that are extremely cautious about making wrong moves that could cost valuable time and potentially market windows for their products.

By Ed Sperling

Most of our weather predictions are developed from about 150 stationary government radar systems, which interlock and occasionally overlap to create a cohesive picture. The picture isn’t perfect—in fact, it’s probably the equivalent of looking at a large, grainy satellite photo—which creates plenty of wrong forecasts. But the system can track large storms across state borders and, in many cases, well into the ocean.

Getting insights into the inner workings of storms and how they are affected by a number of variables is generally left to amateurs, who have devised their own technology—sometimes crude, often innovative—to look into the center of hurricanes and tornadoes. But getting an up-close, crystal-clear look into the center of the beast, and being able to repeat that experience with consistency, has been impossible.

At least it was impossible until a piece of government radar fell into the hands of the Naval Postgraduate School in Monterey, Calif. The radar originally belonged to the U.S. Army and was being used for mobile air defense. While it was considered outdated for military purposes, it proved to be incredibly advanced for scientific research. Weather researchers don’t typically acquire a $2 million piece of military radar for chasing storms.

“What we’ve been doing is casting versus forecasting,” said Jeffrey Knorr, professor and chairman of the Naval Postgraduate School’s department of electrical and computer engineering. “We thought we could use this for atmospheric science. This is a phased array, and it’s the only mobile phased array in existence.”

It became mobile when Knorr and his team mounted it on the back of a flatbed truck, added a diesel generator and developed some software programs to take advantage of the radar in real time.

“The National Weather System radar is a high-power S-band system, which is a parabolic antenna that basically can scan 360 degrees. There’s a clear-air mode and a precipitation mode, but it takes time to develop an image in 360 degrees. It’s about 5 to 6 minutes for a precipitation scan and about 10 minutes for a clear-air scan. With mobile radar, you can get the same data but you don’t have to scan 360 degrees. It’s all programmable from a laptop, so you can take a phased area and make it frequency agile,” he said.

The shape of things to come?

Weather radar can measure how hard it is raining through reflectivity, which includes the number of raindrops and the average velocity. It also can measure spectral spread of the precipitation, which includes turbulence and wind sheer, which is useful in measuring rainfall rates and predicting flash floods. But the speed of updates is a problem for making fast and accurate predictions.

Knorr’s system allows updates every 5 to 10 seconds through the addition of a high-speed digital signal processor. But it does more than that. Most radar is horizontally or vertically polarized. His team added a third axis, so instead of just seeing how hard it is raining and how many raindrops there are, it can measure the size of the raindrops. The larger they are, the flatter they are, which makes it impossible to pick up using ordinary polarization.

“What we’re able to measure now is the storm velocity, reflectivity, motion toward or away from the radar, and the gray area, which is zero radio velocity,” he said. “We also get a higher-resolution picture. Radar spreads as it goes out, so a 1 degree beam width has a certain cross-range resolution at 1 mile. Shorter-range radar has higher resolution.”

This is particularly important in tracking the path of tornadoes, which have a signature characteristic on weather radar. When weather experts look at a radar image, they can identify this signature and predict that tornadoes will form. What they can’t do is refresh the image frequently enough and look inside with a better image. That requires radar to be much more mobile, quicker and much more accurate.