The best way to figure out where the problems are with products is to check with customer service. They hear everything. So System-Level Design sat down with Tom Flodeen, VP of customer service at Mentor Graphics to see where customers are asking questions. Yeah, we know there’s a little marketing in this, but it’s worth wading through to listen to what’s going on behind the scenes.

By Ed Sperling & John Blyler

For all the concern about 45nm chip development—and there have been a number of design investigations at that process node since the beginning of the year—the vast majority of activity is still at 130nm.

This is an indication of just how costly it has become to stay on the Moore’s Law road map—and how many companies have stopped trying to keep up. It’s also an indication of just how much life is left in the older process nodes. Since the beginning of the year, there have been more than 13,000 design investigations—trying out new tools, architectures and processes. Roughly 12 percent of those were at 45nm, with 60 percent at either 90nm or 130nm.

This has multiple implications for the industry, and particularly the fabless development model. While companies such as Broadcom, Qualcomm, Nvidia and AMD continue to live on the bleeding edge of the fabless world, the vast majority of chip developers have adopted strategies that either hang back one or two nodes or skip nodes entirely. Because of the expense of developing new chips, the number of chips that need to be sold to generate a profit has been steadily rising.

Within the foundry business, however, there have been two very distinct models. While companies such as TSMC, UMC and the Common Platform triumvirate of IBM, Samsung and Chartered Semiconductor continue to lead the pack to the next process node, that leadership comes at a very high price. Others, such as China’s SMIC, Israel’s Tower and Malaysia’s Silterra continue to erode their profits several nodes back where volume is significantly higher.

Joanne Itow, managing director for manufacturing at Semico Research, said the number of wafers processed at the leading edge continues to grow. That’s a function of how much volume is necessary to break even at advanced nodes. But Itow said that also translates into more foundry business at the leading edge than there was five years ago. Within that scenario, there also is more competition.

At the same time, she said 130nm remains popular for a variety of reasons: “It can be run with or without copper, on 200mm or 300mm wafers, and there is still a lot of capacity at 130nm. So the price is very competitive and it is not surprising that companies will continue to utilize that technology for a long time. As the price to manufacture declines, we (consumers) benefit from the new electronic applications that emerge. New designs at 130nm are taking advantage of the technology at very good price points.” Apple’s iPhone is only one example of new consumer designs that use 130nm technology.

For capital equipment makers, this isn’t particularly good news. Fewer foundries at the leading edge mean fewer sales. The abandonment of the 200mm fab equipment by memory makers has left a lot of used equipment for sale, said Itow. Big foundries have depreciated their equipment and remain competitive on pricing against second-tier foundries, but the overall effect on capital equipment sales is significant.

This also has implications for the EDA industry, although low-power design starts and a focus on business objectives versus raw performance could pry open a replacement market as well as drive new markets. As expected, the vast majority of design investigations occurred at 100MHz and 50MHz. Low power has become not only a mandate but an opportunity for chip developers, and many companies have begun developing multicore chips that run at lower clock speeds—or are using multiple chips at lower clock speeds.

Systems on chip, in particular, seem to be gaining momentum. Of all design activity, nearly 40 percent of those questioned used at least one block of non-memory IP, and some used more than 30 blocks. That figure is a strong indication of time-to-market pressures and the maturity of the IP industry, as well as an indication of how companies are crafting their chips.

Interestingly, the bulk of the lower clock speeds are being developed at older process nodes, not at the bleeding edge. Speed is still important, but as a selling point power is at least as important, if not more important. In fact, since January there have been only 23 investigations into chips running at clock speeds greater than 3GHz.

By region, most of the design activity occurred in North America. Asia, including Japan, saw only about one-fourth as much activity as North America in 2008. Despite all the startups in China and the preponderance of manufacturing there, the bulk of the design activity remains in North America. Asia was tied with Europe.

By Ed Sperling

The crossover for system on insulator (SOI) versus bulk CMOS was supposed to happen at the 22nm, but that was before software developers ran into problems programming multicore chips.

For years, SOI was considered the high-performance cousin of CMOS—more expensive, more difficult to manufacture and unnecessary for most applications. It is the heart of the Cell processor, for example, which drives Sony’s Playstation 3, the latest versions of digital televisions and some network appliances that need the benefits of always-on active power.

But with the persistent problems of writing general-purpose applications that can scale with multicore processors, SOI is quietly gaining more mainstream appeal. By running either faster or cooler—or both—it can provide the performance gains that multicore chips would provide if the software could take advantage of all the cores.

“SOI does offer a way out,” says Horacio Mendez, executive director of the SOI Consortium. “The big issue is the scalability of bulk CMOS, and there are significant challenges there. When you shrink the transistors, they’re not stable. And with stability comes a power consumption problem.”

The instability is caused in large part by voltage threshold variations. As companies continue down the Moore’s Law road map, short-channel effects (see Fig. 1 below), an increase in parasitic leakage as a result of scaling gate-length dimension and gate oxide leakage all contribute to power dissipation. SOI chips use up to 40% less power due to lower parasitic capacitance, and because they can use higher current they operate at lower voltages.

In practical terms, that means SOI chips can at least keep the number of cores constant and still add performance at each process node. And because they run cooler, they also can use less expensive packages—something that affects when they become economically feasible to use in lower-performance applications.

Short Channel Effects — Source: IBM

Given the advantages, it should come as no surprise that IBM has opened its SOI fab to commercial business at 45nm. Mark Ireland, IBM’s vice president of semiconductor platforms, said SOI is expected to be adopted by the Common Platform group—IBM, Samsung and Chartered Semiconductor—at 32nm.

“What we’re doing now is creating an industry ecosystem,” Ireland said. “From a design standpoint, this is more about education of engineers. At IBM we moved our entire ASIC business to SOI at 45nm. A lot of the hesitation is just about the unknown. But it’s the same design tools and ARM physical IP.”

Opening SOI technology to a broader market also should drop the cost even further, bringing it much closer to parity even at 45nm. But the biggest advantage is still on the software side. While many applications can be threaded to deal with between two and eight cores, far fewer will gain from the addition of more cores. On top of that, very few applications are scalable so they can be written once and recompiled for as many cores as become available.

“Customers already are coming to us looking for higher single-threaded performance,” Ireland said. “Clearly, that legacy market is not going away. Applications will not change overnight. And you do get a performance gain every time you move to the next node, so at 32nm vs. 45nm, there is a performance gain.”

Intel developed a similar technology called TerraHertz in 2000, but so far has done nothing with it commercially. It is one of several possibilities that Intel can tap into at future process nodes, along with its Tri-gate technology. Likewise, IBM has been developing its own tool bag of options, which includes everything from FinFETS to AirGap insulation between structures on a chip.

All of these technologies can be manufactured using existing equipment, and likely will have a significant role in future system development

This online graduate course covers the essentials of systems engineering management and its critical interconnection to program/project management. Systems engineering is the integration of several engineering fields into an efficient and effective process for the overall technical management of programs and development of systems and products. Students will gain detailed knowledge in management techniques applicable to activities within Systems Engineering, including evaluating new technology, integrating legacy systems, trade-off studies, technical performance measurement, cost-effective process tailoring, technical reviews and audits, and others. Several case studies projects will be studied throughout the course to illustrate key concepts and management techniques

Professor: John Blyler

Class Begins: September 28, 2009

Class Ends:  December 6, 2009