By Ed Sperling
The crossover for system on insulator (SOI) versus bulk CMOS was supposed to happen at the 22nm, but that was before software developers ran into problems programming multicore chips.
For years, SOI was considered the high-performance cousin of CMOS—more expensive, more difficult to manufacture and unnecessary for most applications. It is the heart of the Cell processor, for example, which drives Sony’s Playstation 3, the latest versions of digital televisions and some network appliances that need the benefits of always-on active power.
But with the persistent problems of writing general-purpose applications that can scale with multicore processors, SOI is quietly gaining more mainstream appeal. By running either faster or cooler—or both—it can provide the performance gains that multicore chips would provide if the software could take advantage of all the cores.
“SOI does offer a way out,” says Horacio Mendez, executive director of the SOI Consortium. “The big issue is the scalability of bulk CMOS, and there are significant challenges there. When you shrink the transistors, they’re not stable. And with stability comes a power consumption problem.”
The instability is caused in large part by voltage threshold variations. As companies continue down the Moore’s Law road map, short-channel effects (see Fig. 1 below), an increase in parasitic leakage as a result of scaling gate-length dimension and gate oxide leakage all contribute to power dissipation. SOI chips use up to 40% less power due to lower parasitic capacitance, and because they can use higher current they operate at lower voltages.
In practical terms, that means SOI chips can at least keep the number of cores constant and still add performance at each process node. And because they run cooler, they also can use less expensive packages—something that affects when they become economically feasible to use in lower-performance applications.
Fig. 1: SOI VS. Bulk-Stability Comparison
Much of the transistor instability is caused by Vth variation, causing higher leakage, increased power. SOI shows more stability.
Short Channel Effects — Source: IBM
Given the advantages, it should come as no surprise that IBM has opened its SOI fab to commercial business at 45nm. Mark Ireland, IBM’s vice president of semiconductor platforms, said SOI is expected to be adopted by the Common Platform group—IBM, Samsung and Chartered Semiconductor—at 32nm.
“What we’re doing now is creating an industry ecosystem,” Ireland said. “From a design standpoint, this is more about education of engineers. At IBM we moved our entire ASIC business to SOI at 45nm. A lot of the hesitation is just about the unknown. But it’s the same design tools and ARM physical IP.”
Opening SOI technology to a broader market also should drop the cost even further, bringing it much closer to parity even at 45nm. But the biggest advantage is still on the software side. While many applications can be threaded to deal with between two and eight cores, far fewer will gain from the addition of more cores. On top of that, very few applications are scalable so they can be written once and recompiled for as many cores as become available.
“Customers already are coming to us looking for higher single-threaded performance,” Ireland said. “Clearly, that legacy market is not going away. Applications will not change overnight. And you do get a performance gain every time you move to the next node, so at 32nm vs. 45nm, there is a performance gain.”
Intel developed a similar technology called TerraHertz in 2000, but so far has done nothing with it commercially. It is one of several possibilities that Intel can tap into at future process nodes, along with its Tri-gate technology. Likewise, IBM has been developing its own tool bag of options, which includes everything from FinFETS to AirGap insulation between structures on a chip.
All of these technologies can be manufactured using existing equipment, and likely will have a significant role in future system development
