By Ed Sperling
Mentor Graphics boosted the functionality of its PCB tools, adding 3D field solvers and thermal/power co-simulation analysis. This is particularly important for high-speed interconnects such as SerDes, which requires 3D modeling for signal integrity analysis.

Cadence roared back to life in Q4 with revenue of $308 million compared to $249 million in the same period in 2010, and net income of $11 million (or $46 million non-GAAP) compared to a loss of $37 million in 2010 (or $18 million non-GAAP). The company anticipates revenue will be in the range of $305 million to $315 million this quarter, with annual revenue in the range of $1.24 billion to $1.28 billion.

Sonics and Tensilica are working together to integrate Tensilica’s DSP processor interface with Sonics’ OCP-IP interface. The goal is to boost on-chip performance while making it easier to integrate IP. These kinds of deals are helpful in getting SoCs to market more quickly. Sonics also issued its formal response to rival Arteris’ countersuit.

By Ed Sperling
Mentor Graphics inked a preferred partner deal with Freescale to deliver a Vista-based virtual prototyping solution for its processors. The really interesting part of this one is that Mentor is now facing off against Synopsys and Cadence in the virtual prototyping market. Mentor also signed a deal with Ecrio to collaborate on Nucleus-based LTE IP Multimedia Subsystem platforms, and it acquired the Flowmaster Group for computational fluid dynamics simulation software. In the world of stacked die, this stuff will play an interesting role.

Tensilica introduced an audio DSP core that it claims improves performance more than 1.5 times for post-processing in smart phones and audio entertainment. Post processing is vital as the size of speakers continues to shrink. The smaller and flatter the device, the more complex algorithms that are required to reconstruct sound.

Cadence expanded its NAND flash IP lineup to include support for the Open NAND Flash Interface 3.0 spec. This spec is aimed at eliminating a bandwidth bottleneck in memory.

Arteris won a deal with Beijing Nufront for its network-on-chip interconnect IP and its shared memory technology. Beijing NuFront makes mobile phone SoCs.

By Ed Sperling
Mentor Graphics introduced protocol transactors written specifically for its Veloce emulator. This dramatically speeds things up because the transactors allow engineers to use stimuli generated by OVM, UVM, and SystemC, among others, and then to apply them to the DUT running on the emulator. The transactors work with a broad range of buses and interfaces, as well.

Tensilica added Dolby Volume to its HiFi Audio DSPs, which allows consistent playback volume for all content and using all sources. For anyone who has raced to minimize the audio assault of extremely loud commercials, this is a big improvement.

Taiwanese memory maker Nanya Technology endorsed Synopsys’ Proteus lithography rule check solution. This kind of technology will become increasingly important over the next couple nodes, particularly with double patterning and potentially even triple patterning.

For all the talk about design starts being down, the value certainly isn’t decreasing. What is changing, however, is that more is moving out of the hands of centralized processing companies and into the SoC ecosystem. A report from Markets And Markets says the SoC market will reach $225 billion by 2016, up from $85.9 billion in 2011.

CEVA introduced a low-power programmable DSP for camera-enabled devices, which includes most of the popular mobile devices these days. Video and imaging functions are distributed across multiple processor engines, which is definitely a plus in video and image processing.

Synopsys said it has reached an agreement to buy Magma Design Automation, putting it on a collision course with Cadence over analog and with Mentor Graphics in the DFY/DFM arena. The analog is particularly strategic for the stacked die market, where most experts believe it will be decoupled onto a separate die or multiple die. There is no indication when the deal will be finalized.

Synopsys also reported its fiscal Q4 earnings. Revenue was $390.5 million, vs. $375.5 million for the same period in 2010. Revenue for the full year was $1.536 billion, up 11.2% from $1.38 billion in 2010. Net income for the quarter was $39.9 million, vs. $25.4 million in 2010. The company is targeting revenue of $412 million to $420 million in Q1 2012. That line certainly points in the right direction.

Fujitsu Semiconductor standardized on Mentor Graphics’ signal integrity technology for PCB co-design. Recon Instruments also used Mentor’s Android professional services to develop micro optics for sports goggles. The goggles provide info about speed, jump airtime, GPS location, distance traveled, temperature, altitude and time. Well, that should take the guesswork out of skiing. Tree ahead.

SMIC and ChipEstimate launched a portal for SMIC-compatible IP cores ranging from 40nm all the way up to 0.25 microns.

Tensilica added RacyICs to its list of design center partners, this one for its Xtensa processor line. RacyICs sells verification and implementation services for IC design.

By Ed Sperling
Mentor Graphics’ numbers showed positive growth for the quarter ended Oct. 31. Revenues increased to $250.5 million from $238.9 million in the same period in 2010. Net income was $27.4 million, up from $24.3 million in 2010. Even more important, bookings were up 20% year over year, with a 55% increase in the design-to-silicon category. http://www.mentor.comcompany/news/upload/Q3FY2012-earnings_pdf Mentor also integrated its Inflexion user interface into the standard GENIVI infotainment base platform. When cars talk, people listen.

Synopsys rolled out a new version of its FPGA-based prototyping tools, improving performance and allowing faster design revisions. The rollout also includes improved debug capabilities throughout the entire design cycle. 0

Tensilica won a deal with Skyviia, a Taiwanese company that develops multimedia ICs, for its HiFi Audio DSP core. This moves Tensilica further into the Android and portable multimedia markets.

ARM also made a bigger push into Taiwan, expanding its R&D presence with a Hsinchu Design Center.

By Ed Sperling
Mentor’s Colin Walls questions whether embedded software engineers would write better code if time on their computers was limited. That’s like sharing a desk. Make sure you remove all valuables before you leave.

Synopsys’ Alex Seibulescu looks at coverage in the world of high-level verification and synthesis, and what the current best practices are. It still isn’t as simple as doing everything once, but at least companies are creating some interesting workarounds.

Cadence’s Richard Goering digs into a new methodology for easing 32/28nm designs. Here’s what most companies have to look forward to. The good news is by the time they reach this node some of these solutions will have been automated.

Mentor’s Jay Gorajia examines production schedules and the impact of factor strategic alignment, along with the list of complaints about whose fault it is when something goes wrong. One common theme emerges: “It wasn’t me.”

Semico’s Michell Prunty gives a short-term grim forecast of the IC market—don’t expect a turnaround until sometime next year. So far it’s still better than 2008, but does anyone actually remember a recovery?

Cadence’s Joe Hupcey reports some of the highlights from CDNLive in Bangalore. The flight over isn’t one of them.

And in case you missed the most recent Low-Power Engineering newsletter, here are some standout blogs:

–Synopsys’ Cary Chin takes a look at power efficiency in the iPhone 4S. Battery life has improved, but so has functionality.

–Mentor’s Barry Pangrle looks at three different implementations of a new ARM core. This is an interesting glimpse into innovation around a common platform.

–Cadence’s Luke Lang examines isolation, and how to do it, using the three main power formats—CPF, UPF 1.0 and IEEE 1801. Understanding the differences is critical for companies using multiple vendors’ tools and IP.

–Apache Design’s Aveek Sarkar raises the discussion up a notch, saying that a global view is necessary for simulation and validation of the power delivery network.

–Tensilica’s Chris Rowen equates building a business to running a marathon. It takes longer and much more energy than you initially thought.

By Ed Sperling
It was a good week for emulation. Mentor Graphics joined forces with MoreThanIP to create emulation solutions for multi-gigabit Ethernet SoCs.  Mentor also won a deal from ZTE for its Veloce emulator, and it added emulation solutions for USB 3.0 products.

Cadence and Samsung have developed a 32nm HD digital camera SoC for Ambarella, which has been creating digital still cameras with high-definition video capabilities. Translation: lots and lots of pixels. Cadence also teamed up with Xilinx for system design, software development and testing of Xilinx’s Zynq platform. And Cadence announced its quarterly numbers, showing net income of $28.1 million for the quarter ended Oct. 1 ($37.3 million non-GAAP) vs. $126.8 million in the same period in 2010 ($11.2 million non-GAAP). Revenue for the quarter was $292 million vs. $238 million in 2010.

eSilicon inked a deal to use Synopsys’ Custom IC design solution for 28nm SoCs. And Synopsys’ DesignWare Audio IP achieved first-pass silicon for 65nm and 55nm process technologies from multiple foundries.

Open-Silicon launched an ARM Center of Excellence to provide complete SoC development solutions for low-power chip development for the networking, telecommunications storage and computing markets. This is becoming a very cozy relationship. Open-Silicon already has a multi-year licensing agreement in place with ARM.

Atrenta introduced early PPA analysis for ARM’s AMBA designer using its SpyGlass and GenSys products.  Atrenta also joined Cadence’s System Realization Alliance, which is no surprise considering it was one of the first to adopt Cadence’s EDA360 terminology.

Arteris won a deal from VIA Telecom for its high-speed inter-chip communications IP between mobile phone baseband chips and application processors.

Tensilica won a deal from EnVerv, which licensed Tensilica’s ConnX DSP cores for its smart grid power line communications SoCs.

By Ed Sperling
Altera is embedding Synopsys’ virtual prototyping technology in its ARM-based SoC FPGA products. Considering FPGA vendors have been giving away their tools for years, much to the chagrin of EDA vendors that have tried repeatedly to win a foothold in the FPGA tools market, this potentially is a big deal. And considering the existing market for virtual prototyping is still small and the FPGA opportunity is quite large…well, this gets very interesting.

On another front, Synopsys is collaborating with UMC to develop IP for the foundry’s 28nm HLP Poly SiON process.

Mentor Graphics is working with Freescale to accelerate automotive infotainment that relies on ARM A9-based processors. Mentor’s In-Vehicle Infotainment base platform is compliant with the requirements of the GENIVI Alliance, the association of automotive and consumer electronics companies.

Russia-based IntegrIT has ported its NatureDSP Math Library to Tensilica’s baseband DSPs. The traditional emphasis on science and math is still alive and well in Russia—and expanding into some new markets. IntegrIT develops signal-processing routines for DSP functions.

By Ed Sperling
Cadence’s Jack Erickson documents a 17 million-gate 40nm design that was completed in eight months with two designers. Does that mean it would take 16 designers one month?

Synopsys’ Navraj Nandra says that near-field communications will open up new opportunities for marketing, payment and data interactions. Why waste gas on trips to the store? You won’t even have to get out of bed in the morning.

Mentor’s Colin Walls is doing his best to prop up the European economy. Check out his conference schedule—and then try to figure out why this is where embedded software conferences are being held.

Tensilica’s Grant Martin exposes the popular misconception about power vs. energy. This raises all sorts of interesting questions, like what exactly is a power play or flower power? And if you’re drinking an energy drink do you feel energized or powerful?

Cadence’s Joe Hupcey says Amazon’s new Kindle Fire is a next step toward the paperback computer—one so inexpensive you don’t really care if you lose it. Just don’t leave your personal data on it.

Synopsys’ Eric Huang examines the market for USB 3.0 and predicts a huge uptick by 2014. That’s just one process node away.

DeepChip’s John Cooley ran a user poll of the top tools at DAC last June. Mentor’ Olympus-SoC hierarchical design flow came in first. For all the runners up, someone had to win. And for all the potential complaints, we’ll add the caveat that the real proof is in the sales numbers, not these kinds of polls. Still, the user comments are interesting. Cooley says Vennsa OnPoint came in second, followed by Oasys RealTime.

Cadence’s Richard Goering covers an interesting panel discussion on PCB data transfer formats. This is particularly interesting in light of the fact that the definition of a system is changing—and getting far more complex, more mobile and much smarter.

Synopsys’ Alex Seibulescu is aiming for intelligent coverage in verification. You can’t cover everything, of course, but you at least should know what you don’t know.

By Ed Sperling
Synopsys created the first TLM Web portal, complete with an initial offering of 600 models, and inked a deal to distribute ARM’s Cortex processor models from its new TLMCentral site. Synopsys said it hopes the portal will spur investment in virtual prototyping.

Mentor Graphics won a deal with Fujitsu for its embedded software development environment, which will be used for Fujitsu’s general-purpose 32-bit microcontrollers. What’s interesting here is that Fujitsu chose Mentor’s Embedded Sourcery CodeBench for ARM’s microcontroller IP, which will be included in the Fujitsu product. It’s an unusual keyhole into the microcontroller space.

ARM cut another deal, too, which must have had the corporate lawyers hopping. Open-Silicon signed a multi-year agreement to license a broad portfolio of ARM technology, which allows Open-Silicon to offer ARM’s IP with its own design and manufacturing services. We may be witnessing a change in the wholesale distribution model.

Tensilica inked a deal with Fraunhofer IIS, which allows Erlagen, Germany-based Fraunhofer to become a design center partner for Tensilica’s HiFi Audio DSPs. Fraunhofer, incidentally, is part of the Fraunhofer-Gesellschaft research organization, which is partly funded by the German government.

ST-Ericsson reportedly gained a 10x improvement in time by using using Cadence’s mixed-signal flow for its 40nm baseband chip. Create automation tools for analog engineers, force them to hit tight schedules within budget, and apparently they’ll use these tools.