By Ed Sperling
Cavium’s Brian Hunter, writing for Synopsys’ Verification Martial Arts, resorts to a rather creative, if unusual, way of describing namespaces—a video of a chicken processing facility. This is the very free-range explanation.

Cadence’s Frank Schirrmeister offers a crash course on in-circuit acceleration. Get familiar with this concept because more and more will happen in-circuit at future process nodes.

Mentor’s Travis Mikjaniec questions why California law requires smokers to stand at least 25 feet away from doors and windows. How exactly did they arrive at that number? And which way was the wind blowing at the time?

IHS iSuppli’s Robert Braverman crosses concepts—value chains and supply chains—and explains why they’re so intertwined.

Synopsys’ Navraj Nandra expounds on how to test embedded IP—a serious problem when you’re using multiple IPs with different test access strategies, interfaces and descriptions.

Cadence’s Peter Heller looks into the role of verification IP in SoC verification and why it’s becoming so critical—not to mention why IP vendors are finally able to get paid for this stuff.

Mentor’s Nazita Saye has created a top-10 list of things she learned from engineers. You’ll like No. 4: Engineers are nice people. Funny, they never say that about writers.

DeepChip’s John Cooley goes searching for Samsung in the foundry rankings and finds them…well…all over the map. So much for consistency in math.

Synopsys’ Eric Huang questions the future of Thunderbolt vs. USB 3.0—while wearing a safari hat. That may not seem weird, unless you consider he was indoors.

And in case you missed the most recent Low-Power Engineering newsletter, here are some blogs worth noting:

—Synopsys’ Cary Chin tests the power efficiency of 4G and 3G phones and discovers, rather unexpectedly, the hidden cost of streaming data.

—Mentor Graphics’ Barry Pangrle digs under the covers of Intel’s new Tri-Gate processors and finds the real story is all about energy efficiency and reduced area.

—Cadence’s Luke Lang examines why there are different commands in CPF and UPF and how to navigate the macro models.

—Mimasic’s Bhanu Kapoor concludes that using all the features built into hardware will require some advances in software.

—Apache Design’s Aveek Sarkar looks at what’s needed to meet power, performance and price goals for stacked die and sub-20nm designs.

—Tensilica’s Chris Rowen cooks up the perfect SoC recipe with some advanced culinary techniques.

—Atrenta’s Kiran Vital charts the gap between a standard format for describing memory behavior and reducing dynamic power.

—And Docea Power’s Ghislain Kaiser points to a key problem in solving thermal problems. Blame it on a lack of training.

By Ed Sperling
A subtle but important shift is under way inside of EDA. While vendors are still focused on solving some thorny issues at the front end of Moore’s Law, much of the R&D effort lately has been targeted toward better and earlier integration of new or enhanced tools and toward combining IP blocks into subsystems.

To some extent this is simply good housekeeping—roughly EDA’s equivalent of making software backward compatible. Ensuring that that tools work with each other in a flow that now has to be concerned with hardware, software, power, electromigration, standards—and all the while making this work across a globally disaggregated supply chain—is an incredibly complex management challenge. But there is also at least an early indication, and one that apparently warrants big investments on the part of EDA vendors, hat at 28nm and beyond many of their customers’ in-house tools are running out of steam. Even better for EDA, there is far less money being appropriated to develop new internal tools.

This explains the rising clamor by customers for more standards. Chipmakers certainly don’t want to pay top dollar for EDA tools, and standards make it easier to chop costs—or at least to negotiate a deal. That’s partly what’s behind the increasing amount of noise about existing standards such as the dueling power formats, CPF and UPF/1801. It also explains why there is more collaboration under way between chipmakers and EDA vendors to develop complex solutions, because while chipmakers may experience a limited number of problems, EDA vendors deal with a much greater universe of the same or related issues and draw from a larger pool of chipmakers to offer advice.

All of the big EDA vendors recognize these changes, and their recent product releases clearly reflect it. Witness Cadence’s announcement today of tighter integration between its System Development Suite, with in-circuit acceleration, and its VIP catalog, which now has hooks for both acceleration and emulation. What that means, in a nutshell, is that simulation and emulation teams now can share a verification environment, and the VIP catalog is now compatible with the Accellera Co-Emulation and Modeling Interface (SCE-MI) standard.

“The goal is to push use models from NRE to automation,” said Michal Siwinski, group director for product marketing for Cadence’s System and Software Realization Group. “There are two elements to this. One is in-circuit acceleration to the System Development Suite. The second is a VIP catalog that has been expanded for acceleration and emulation.”

Both Mentor Graphics and Synopsys have been taking similar steps for their respective environments. Mentor, for instance, has been active in bridging a variety of its embedded software tools into a standard flow, and in making emulation far more attractive for software developers by adding a desktop virtualization layer. The company also has been working heavily on making it easier for chipmakers to develop and incorporate embedded software into their designs.

Synopsys has been integrating a number of pieces in other areas, most recently in the 2.5D/3D IC world where it has begun integrating test, IP, parasitic extraction, simulation, DFM and thermo-mechanical stress analysis into the same flow. It also has been working hard to integrate hardware and software.

“The interaction of components is much more important,” said Alan Gibbons, principal engineer at Synopsys. “A lot of this is not being modeled today, and if it is it’s happening on a spreadsheet. We need more intelligent algorithms to make this work.”

Along the same lines, but in different market, Cadence has launched an NVM Express memory subsystem for enterprise computing environments. “This will dramatically reduce the time it takes to integrate and optimize,” said Neil Hand, group production marketing director for Cadence’s SoC Realization Group. “NVMe was built on PCI Express. This is a natural move to a subsystem and it leverages a lot of expertise in storage and high-performance interfaces.”

This follows on the heels of similar moves by Synopsys in the audio subsystem arena (as well as its NVM Express VIP), and by companies such as Tensilica in the audio and video subsystem world.

Simon Butler, CEO of Methodics, said the move from IP to subsystems eliminates a lot of the “grunt work” by bundling in firmware and development tools.

“There’s a lot of history behind using the appropriate infrastructure with functional blocks,” said Butler. “The challenge is in trying to accommodate both of those. Generally speaking, the larger the block the more you need to remove the complexity, and the way you do that is to give it to the IP vendors and let them do it.”

Butler said that characterizing subsystems rather than just IP blocks is a big step forward. “The fact that programming and interacting can be done at a higher level means the use model is easier. How perfectly it behaves electrically is driven by the application. But if you see enough traffic going through a subsystem, you bring more to the table and are able to solve more problems. So basically your integration work as a customer is going down because the vendor is supplying the abstraction layer.”

With all of the big three EDA vendors on board, this focus on integration will likely establish the theme for the upcoming Design Automation Conference in San Francisco early next month. The big questions now are what else will be integrated, and by whom.

By Ed Sperling
Synopsys continued on its acquisition path, this time buying RSoft Design Group, which makes photonics design and simulation software. Synopsys has been pushing steadily into the optics design market, beginning two years ago with the acquisition of Optical Research Associates.

Cadence won a deal with Fujitsu Semiconductor, which is using Cadence’s Chip Planning System to build microcontrollers. Fujitsu ranks seventh in the world in the MCU business, with 5.5% of the market, according to Data Beans. The company was No. 3 in 2010, so apparently it’s time for some serious retooling.

Arteris won a deal with IC-Logic, which licensed its network on chip and interconnect IP for automotive infotainment SoCs. IC-Logic is based in Sulzbach, Germany.

Tensilica teamed up with VWorks to provide virtual prototyping platforms, especially for multi-core designs. VWorks does advanced simulation and modeling.

TSMC sales, which are something of a bellwether for chip activity, were up 9.3% in April compared with March, and 10.4% year over year. Things seem to be picking up. http://www.tsmc.com/tsmcdotcom/PRListingNewsAction.do?language=E

By Ed Sperling
Mentor Graphics rolled out the next generation of its Veloce2 emulation platform, adding virtualization capabilities. The key here is that it allows software engineers to use the platform to verify their software from their PCs, rather than having to go into a lab to work on their code. This is a new wrinkle in emulation, which is now being used as much for software verification as for hardware. Appealing to software engineers is a whole different world.

Cadence roared back to life in Q1, with revenue increasing to $316 million compared to $266 million in Q1 of 2011. Net income was $31 million compared with $6 million in the same period last year. On a non-GAAP basis, net income was $47 million compared with $23 million in 2010. The company expects revenue of between $315 million and $325 million this quarter.

Synopsys extended visibility in HAPS debug FPGA prototypes, adding about 100 times more storage capacity for signal traces while slashing memory utilization for complex designs.

Open-Silicon expanded its solutions portfolio to include architectural analysis and modeling, pre-silicon prototyping, embedded software, co-silicon system design and test and post-silicon validation. It also expanded its ARM Center of Excellence and boosted staffing at its design center in Pune, India.

Tensilica added support for China’s Dynamic Resolution Adaptation standard to its audio encoder/decoder library for its HiFi Audio DSPs. That should open up a huge market.

Soitec said it is ready to provide fully depleted silicon-on-insulator wafers for both 2D and 3D customers. The company claims significant cost savings over bulk CMOS at advanced nodes—a major shift from previous nodes.

By Ed Sperling
Synopsys’ Karen Bartleson looks at the effect of global markets on standards. This is particularly important because standards tend to stick around for a very long time—sometimes decades.

Mentor’s Colin Walls compares embedded and desktop processors with an old Cray supercomputer, which consumed 60 Kw/hr. We’ve come a long way. Check out the picture.

Cadence’s Richard Goering plucks the highlights from complex stacked die presentations at last week’s Electronic Design Processes Symposium. Stacking issues are coming to a design near you—and much more quickly than you might imagine.

John Cooley’s DeepChip taks a look at the formal and CDC tools available and what exactly they do. This should help take some of the mystery out of this market.

IHS iSuppli reports on the five most counterfeited semiconductor categories in 2011. Analog wins by a hefty margin, which says something about profit margins in the analog sector.

Synopsys’ Eric Huang has constructed a demo of the new SuperSpeed Interchip spec, which isn’t even quite at the beta stage. He rates it release 0.9. There’s a video to go along with it.

How much is experience worth? Mentor’s Robin Bornoff gave thermal modeling software to his 15-year-old son to find out.

Synopsys’ Helene Thibieroz picks out some of the highlights of the recent Synopsys User Group, including AMS verification using UVM and FinFETs to extend the life of transistors.

Cadence’s Ahmed Elzeftawi looks at real-number model development and its application in AMS verification. This is a great overview of some of the most common causes of re-spins.

And in case you missed the most recent Low-Power Engineering newsletter, here are some standout blogs:

–Synopsys’ Cary Chin solves the mystery of why the new iPad takes so long to charge and why it consumes more power.

–Mentor’s Barry Pangrle digs into the differences between FinFETs and TriGate transistors, and why not all FETs are created equal.

–Tensilica’s Chris Rowen expounds on what really makes the design process work—people.

–Docea Power’s Ghislain Kaiser details the reasons why general models don’t work—and the best approaches to reducing design time and problems.

–And along the same lines, Apache Design’s Arvind Shanmugavel looks at the need for accurately modeling thermal, mechanical and electrical behavior.

By Ed Sperling
As complexity increases and the industry increasingly shifts away from ASICs to SoCs, the concept of coherency is beginning to look more like a stack of issues than a discrete piece of the design.

There are at least five levels of coherency that need to be considered already, with more likely to surface as stacked die become mainstream over the next few years. Perhaps even more mind-numbing, this stack itself will have to take on a level of coherency over the couple generations of chips.

Let’s take a closer look.

Cache coherency
The concept of keeping data coherent historically was relegated to processor makers such as IBM, Intel and AMD, which have focused on improving performance through faster access to data. One solution to that improved performance has been multithreading and multiprocessing. Along with that, these vendors have added in various levels of cache memory for faster recall of important data.

More cores also makes it harder to effectively use these caches. Data has to be kept consistent, which requires more system overhead in terms of processing and power just to maintain that coherency. And it gets even harder as more cores are added into an SoC, which increasingly are not same size, do not run at the same frequency, and sometimes do not even connect directly to the main CPU.

“With cache coherency, some of the traffic may be serviced by the cache on another GPU,” said Drew Wingard, CTO at Sonics. “If you’re just using an ARM core, the CPU coherence is sufficient. But the GPU uses its own local memory. You really want it to be fully cache coherent across all of those.”

But even finding the data to maintain consistency may be a problem in a complex SoC.

“You can view what’s in memory, or view it and be able to change what’s in memory, but first you have to find it,” said Kurt Shuler, vice president of marketing at Arteris. “If you have four cores, the most efficient way to hook them up is for each core to have its own cache and graphics to have its own cache. If you change something, you have to snoop in all the caches to make sure it’s consistent.”

But there is also a move in the completely opposite direction—sharing memories among multiple cores—because it reduces the number of components on the bill of materials. The Low-Latency Interface specification from the MIPI Alliance is a case in point, where a memory can be shared between a modem and an applications processor. Intel, meanwhile, has added on-chip graphics that share memory with the CPU.

“The whole design gets more complex,” said Shuler. “You have more traffic beyond the cores, and from a power standpoint the overhead goes up.”

Still, cache coherency is one of the better-understood pieces of this stack. It has been an issue ever since multiprocessing was first employed in the 1960s. “Snooping” has been widely used since that time.

Software coherency
A newer facet of coherency involves embedded software. Because SoCs now include an increasing amount of software in the design, engineering teams now have to wrestle with coherency issues that previously were dealt with by the operating system.

“Fundamentally you’ve got two combined issues here,” said Andy Meyer, verification architect for Mentor Graphics’ Design Verification Technology Division. “You’ve got cache coherency, where the same data is being viewed in a couple places. And then you’ve got an issue with consistency in the simple code in a uniprocessor that now has to run on a second processor. The ordering of events can change in multiprocessing.”

Those problems crop up regularly in verification, but not always with the expected results. It’s difficult to effectively write the stimulus in a testbench for coherency. What happens, for example, when a core is shut down to save power?

“The scariest part is when there is no OS support,” said Meyer. “There’s also a big problem with heterogeneous cache, such as when you have a CPU working with a GPU.”

Another issue has to do with effective coverage in verification, already a problem for complex SoCs. States frequently are distributed across multiple chips and multiple boards. Timing varies from one state to another, and can be particularly problematic if snooping functions are tied to a state. And parallelism continues to baffle even the most advanced teams.

“Standard coverage methods don’t work well here,” said Meyer. “You have to query in ways you traditionally didn’t have the power to query and ask questions across months of regressions. For instance, ‘Have we been here ever—or in the last two months.’ Until coverage steps up, people with deep knowledge of verification running hundreds of full-time emulator systems are finding out at the last minute that it’s not okay to ship.”

I/O coherency
Tied in with both cache coherency and software coherency is I/O coherency. Increased communication on a chip, between chips, and between a chip and the outside world, have turned what used to be a relatively straightforward networking issue into a complex jumble of prioritization and synchronization.

“You have to deal with this even in single processors,” said Sonics’ Wingard. “You may have a PCI core streaming data into memory. Today, without I/O coherence, it’s difficult to determine what is coming in. The CPU has no way of knowing what was transferred when it dos a copy from non-cache to cache.”

He noted that personal computers had I/O coherency for a long time, particularly with direct memory access. DMA was developed initially to help solve the bottleneck that occurred when a CPU was involved in an I/O transfer. Rather than tie up the CPU with that transfer, the CPU continued running, then accepted an interrupt when the transfer was completed.

But with more of this being moved onto a chip, keeping coherency while moving data back and forth from more places is becoming much more difficult.

Ecosystem coherency
One of the least addressed facets of the coherency stack involves business and communication issues across a supply chain for a particular SoC rather than the actually technology itself. Even where competitive suspicions can be overcome, the very different approaches taken for designing components, IP and software, as well as language barriers, create one of the more difficult and less tangible challenges in the coherency stack.

“The challenge going forward is that you have a bunch of people who may not be that skilled in system development driving the chip and spec for one design, and other supplier trying to orchestrate things,” said Mike Gianfagna, vice president of marketing at Atrenta. “So you bring them together to solve a problem for one customer in 12 weeks and then they move on. You’ve got corporations coming together and bringing all these pieces together almost like the way a movie is done. But is there a coherent way to communicate data and information risks and still provide good visibility from a power/performance/area point of view?”

For decades this task has been handled by IDMs, but in the SoC world there are far fewer IDMs these days. Many of these chips are built using third-party IP such as cores from ARM or MIPS, DSPs from companies such as Tensilica, and standard IP from the Big Three EDA vendors.

Coherency in stacked die
It’s uncertain whether stacking of die, either in 2.5D or 3D configurations will make coherency easier or harder. The answer is likely to be a little of both.

“With 2.5D and 3D, you’re looking at low-power memory access,” said Arteris’ Shuler. “You put the DRAM closer to the CPU, the addressing is wider and you get rid of some of the latency. But you also need coherency across all of this.”

No one is sure yet how multiple high-speed communication channels between die will affect coherency. If the channel between the core is wider and shorter that will improve data speed, but if processors and DRAM are scattered on multiple die, with some of them shut down, some partially shut down, and others fully active, it may make it harder to keep track of data and make sure it is all synchronized.

By Ed Sperling
Synopsys issued a barrage of announcements, including new products, new relationships, and a new win. The company unveiled its next-generation verification IP based on its new VIPER architecture, with native support for OVM, UVM and VMM. Synopsys claims up to 4x performance over other commercial VIP. This is an interesting number, and likely will spark a volley of announcements from the other Big Three EDA vendors, all of which have been gearing up for what they see as a big opportunity in the VIP space. Synopsys also rolled out 28nm M-PHY IP that supports six different standards for mobile applications.

On the relationship side, Synopsys struck a deal with Arteris to jointly develop an IP solution based on the Low Latency Interface, which cuts the cost of the bill of materials by eliminating a memory chip and reducing the area of a PCB. In a related move, Arteris introduced its low-latency interface digital controller IP, which it says is already silicon-proven in TI’s OMAP platform.

Synopsys also is working to link Springsoft’s debug technology with its own Protocol Analyzer. It also won a deal with BiTMICRO for a slew of EDA tools.

Samsung teamed up with Mentor Graphics to create a DFM sign-off reference solution for Samsung’s foundry. This opens the door to a couple of other big deals for Mentor, as well, considering Samsung is one of the three main companies in the Common Platform. The others are GlobalFoundries and IBM.

Mentor also announced its Q4 financial results, which set a new record. Revenues for the quarter were $320.4 million, up from $307.3 million in the same period in 2011. For the 12 months ended Jan. 31, revenue was $1.015 billion—also a record—up from $914.8 million in fiscal 2010. Net income for Q4 was $57.8 million, up from $50.6 million in Q4 2011, and for the year it was $83.9 million, compared with $28.6 million the previous year. Mentor expects revenue to increase to about $1.1 billion this year.

Cadence unveiled the production release of a virtual platform for Xilinx’s Zynq-7000, which is based on the ARM Cortex-A9 MPCore. After years of EDA companies trying to gain a strong entry into the FPGA world, this is an interesting doorway.

Docea Power rolled out a new tool for architectural-level power and thermal analysis. Given the fact that the biggest savings in power and heat can be obtained at the earliest stages of a design, this is an important step forward. The next challenge is to implement this kind of capability into existing flows so that power and heat models can be integrated easily with other models. Functionality and performance are no longer enough.

Tensilica introduced its second-generation multimode baseband chip, which includes multiple dataplane processors. The chip was co-developed with NTT DOCOMO, Fujitsu, Panasonic and NEC.  Tensilica also rolled out Dolby Digital Plus for surround sound on its HiFi Audio DSPs, and it struck a deal with ClariPhy, which will license Tensilica’s dataplane processors for optical networking mixed signal processing.

By Ed Sperling
The push to “smaller, faster and cheaper” hasn’t changed since ICs were first introduced, but the context for those requirements is beginning to shift—with enormous consequences.

What was once done on multiple chips continue to migrate to a single chip or package because of cost, but in some cases the decisions about goes where go well beyond an individual device to include a network of systems. Power and heat have forced some of those decisions. Others are being driven by shorter market windows that affect business decisions about exactly when to move to smaller, faster and cheaper, and whether to keep a design in two dimensions or move to three. In some cases, it even has evolved into a tradeoff about sharing resources to make up for additional costs elsewhere in a design.

“Form factor is everything in a lot of these cases, and you’re being forced to make tradeoffs involving a lot of different pieces,” said Mike Gianfagna, vice president of marketing at Atrenta. “But that requires you to know exactly what you’re doing. A lot of times you don’t. What happens when you reduce the number of layers? Do you know the impact on the system? You may not. But competitive pressure is also forcing you to rethink everything.”

Rethinking designs
Some of these changes are as fundamental as where the processing gets done. While the concept of cloud computing has been around since the days of time sharing on mainframe computers in the 1960s, the ability to offload processing and storage on the fly—and to load balance across compute farms around the globe—adds a modern twist to it all.

The result is a handheld device with the performance capabilities of a compute farm—but with the design focused far less on local processing and storage and more on communication and battery life.

This is evident with a number of upcoming communications schemes and protocols in the handheld market. LTE Advanced, for example, which is expected to find its way into smart phones and base stations over the next four years, focuses on reducing power while increasing performance. One of the best ways to do that is by shifting what processing is done where.

“One of the key decisions is how much processing and intelligence is in the cell phone versus the cloud,” said Graham Wilson, a product marketing manager at Tensilica. “You also have to understand deeply what cores are being used for. There is no room for fat. We’re also going to see a big shift in infrastructure from homogeneous to heterogeneous.”

That means rather than a giant cell tower on the highest hill or building, smaller boxes will be mounted on houses and strung together in a mesh network. “Every house will have its own femto cell or pico cell box so they’re less reliant on the macro cell and they work off each other,” Wilson said.

That changes what resources can be committed within a design to processing, to communication, to storage, and where it can be done best—whether it’s a central processing unit or lots of smaller processors for individual uses. It also boosts the ability to cut some costs in different places than just by shrinking the process geometries in a design.

The Low-Latency Interface working group of the MIPI alliance, for example, is currently working on a new standard that allows DRAM memory to be shared between two chips. NoC technology vendors, in particular, have seen this push because it requires a highly efficient network-on-chip infrastructure.

“The big advantage is that it allows you to get rid of an entire memory chip,” said Kurt Shuler, vice president of marketing at Arteris. “The modem and the application processor are sharing the same memory. You also reduce the number of pins, which is important because it allows you to use those pins for other things.”

He notes there is a very slight performance hit. But the ability to eliminate an entire memory chip can save a couple dollars in a design. Multiply that times millions of units and the savings are huge—far greater than just shrinking the features on a die.

Rethinking packaging
Stacking die offers another alternative to improving performance and time to market, but the tradeoff will be in cost unless additional components can be eliminated. Adding an interposer layer or TSVs will be expensive—at least initially—even though 2.5D and full 3D stacking hold the promise of dramatically improving performance through shorter distances, bigger pipes for data, and lower power because signals will not have to be driven as far.

While this packaging approach is still under development, foundries report that chips are rolling out using this approach. “This is already happening,” said Luigi Capodieci, R&D Fellow at GlobalFoundries. “It’s mostly a decision of which design processes to use in the chip, and that decision will have to be made by the chip designers.”

Stacked die also allow IP developed at older nodes—particularly analog—to be attached through Wide I/O to other chips developed at more advanced processes. That, at least in theory, substantially reduces the time it takes to design a chip because much of it can be based on what has been previously developed.

“Re-use leads to a reduction in time to market,” said Shrikrishna Gokhale, COO and managing director of Open-Silicon’s India unit. “This opens up the lifecycle of different IP and puts the emphasis on packaging and re-use.”

It also puts greater emphasis on software-hardware co-design, he said, and requires more emphasis on defining partitioning earlier in the architecture phase. In addition, it requires a rethinking of what gets done where. Some portions of the design that used to be in separate locations now have to be co-located in the same place because of the constant need to update models and data for both hardware and software teams.

“The logic front-end design needs to be done at the same location as the software,” he said. “That’s less important at the back end, which is the physical implementation.”

Other tradeoffs are less obvious, though, particularly to design engineers. One involves weight.

“Half the weight of a tablet is the battery,” said Drew Wingard, CTO of Sonics. “You can’t afford to add a bigger battery so you have to do an increasing amount of computation with lower power. That means you look at more efficient ways of doing that computing. One is using the GPU as a general-purpose CPU, which allows you to get a lot of performance at low energy.”

He noted that utilizing the GPU requires it to be easily accessible to software developers. And it requires much better management of clock domains, voltages and on-off functionality within an acceptable power budget. And to be really energy-efficient, users need to be able to easily input their own usage models.

Rethinking manufacturing
Some of the changes that are under way are forcing a major shift in manufacturing, too. Staying on the Moore’s Law road map has always been a given for high-volume digital designs, but with double patterning required at 14nm and the delay in extreme ultraviolet lithography, alternatives are being considered that could have ramifications throughout IC design.

“Double patterning is the biggest issue we’re dealing with right now,” said Jean-Marie Brunet, director of product marketing for model-based DFM and place and route integration at Mentor Graphics. “We’re even looking at triple patterning, but there is no way to have density balance between the layers when you do that.”

Lars Liebman, an IBM distinguished engineer, said his company has been working on commercializing self-assembly for finFETs because even multi-patterning isn’t sufficient beyond 14nm. That has implications throughout the design chain. For one thing, it can increase the density on existing process nodes. For another, many of the tools for automating design, particularly on the DFM side, will need to be rewritten.

Conclusion
Area, power and performance have always been the standard metrics for tradeoff in any IC design. What’s changing significantly is why those tradeoffs are being made and where the benefits will show up. Changes targeted at an individual chip in the past, or even a block or subsystem, may now be aimed at a much broader level.

The good news is that infrastructure changes—everything from manufacturing approaches to communications networks—evolve much more slowly and deliberately than those made in the individual device or chip. The bad news is that sometimes that moves so slowly that it can affect what’s done elsewhere in this much broader system. But some change is underway at every level, and managing that change—and the tradeoffs it will demand—will be much more challenging in the future.

By Ed Sperling
Synopsys joined forces with Arteris to integrate Arteris’ network-on-chip models with Synopsys’ Platform Architect. What’s particularly interesting about this relationship is that it combines transaction-level modeling with a chip’s networking infrastructure. That’s important for complex SoCs, but it will be critical for stacked die.

Synopsys also introduced embedded memories and logic libraries for 28nm TSMC processes, and HDMI 1.4 PHY IP for 28nm processes at multiple foundries.

Tensilica won a deal with VIA, which will put Tensilica’s dataplane processors on its solid state drive SoCs. Tensilica also won a deal with mimOn for processors to be used in full LTE PHY reference platforms for user equipment, and another one with Acoustic Technologies, which will port its noise elimination and echo canceling software to Tensilica’s DSPs.

TSMC, a bellwether for the chip industry, reported net sales increased 11.4% between December and January, although they were down 1.1% between January 2011 and January 2012. Still, this is good news. The recovery continues.

By Ed Sperling
Mentor Graphics boosted the functionality of its PCB tools, adding 3D field solvers and thermal/power co-simulation analysis. This is particularly important for high-speed interconnects such as SerDes, which requires 3D modeling for signal integrity analysis.

Cadence roared back to life in Q4 with revenue of $308 million compared to $249 million in the same period in 2010, and net income of $11 million (or $46 million non-GAAP) compared to a loss of $37 million in 2010 (or $18 million non-GAAP). The company anticipates revenue will be in the range of $305 million to $315 million this quarter, with annual revenue in the range of $1.24 billion to $1.28 billion.

Sonics and Tensilica are working together to integrate Tensilica’s DSP processor interface with Sonics’ OCP-IP interface. The goal is to boost on-chip performance while making it easier to integrate IP. These kinds of deals are helpful in getting SoCs to market more quickly. Sonics also issued its formal response to rival Arteris’ countersuit.