By Ed Sperling
A series of recent announcements by the Big Three EDA vendors and their well-known partners from across the disaggregated SoC ecosystem is lending new credence to the impact of collaboration.

While IDMs such as Apple, Intel, Samsung and IBM continue to blaze their own trail, developing in-house tools, methodologies, processes and chips, fabless companies working with foundries and tools developers are beginning to show some of the same benefits for a much lower cost.

One such effort involves Cadence, ARM and TSMC, which together unveiled a 20nm Cortex A-15 chip. Mike Inglis, executive vice president and general manager of ARM’s processor division, said teams from each company worked closely together to find out what was broken on the process side, then fed that information back into performance optimization and packaging and worked it into the design flow.

“This is how you more easily get to a more optimized solution more quickly,” Inglis said. “It also enables the leading edge and the trailing edge to get to market more quickly.”

This is what IDMs have always done, taking information back and forth between the design teams and the fab and adding tweaks all along the way. But what’s changing is that fabless companies appear to be catching up more quickly than most industry observers believed was possible.

“We’re seeing collaboration that is both horizontal and vertical,” said Lip-Bu Tan, president and CEO of Cadence. “Horizontal involves industry standards among peers and does not differentiate end products. With vertical collaboration, the goal is an end product that is differentiated, whether that involves IP, EDA, the foundry or software.”

Mentor Graphics, meanwhile, rolled out the next version of its Nucleus real-time operating environment that was developed with partners such as Texas Instruments, GCT and Stonestreet One. In a move aimed at conserving power, Mentor has moved some of the power management capabilities such as dynamic voltage and frequency scaling into the kernel of the RTOS, according to Jan Klube, director of the Nucleus product line.

“The software design was built into the application from the beginning versus folding complexity onto the application,” said Klube. “So developers get a simple power management API and a power-aware RTOS.”

One of those developers is TI, which has been working with Mentor as well as ARM for its Stellaris microcontrollers. Miguel Morales, worldwide marketing manager for the MCUs, said the microcontrollers are sold with pre-written software wrapped up in kits.

“Collaboration will have to accelerate,” said Wally Rhines, Mentor’s chairman and CEO, who noted that Mentor is also working with TSMC on “reliability” kits. He added that it will be critical to respond together to new and emerging problems, particularly with stacked die where stress, thermal and parasitic effects will create as-yet unknown issues.

Synopsys, meanwhile, has been working closely with TSMC and ARM to improve yield and deal with process variations.

“As we look ahead, there is the notion that an upstream tool can know what a downstream tool must do,” said Aart de Geus, chairman and CEO of Synopsys. “We need to be able to move forward to place and route before we finish synthesis, and we need to be able to question why we should do all the work if an issue is not resolvable.”

De Geus noted that collaboration is the answer to systemic complexity. “We must be committed, and we will need to collaborate with partners that have competence.” He added that there also is a need for quick compromise, balancing a “great enough” solution against a better one that will take longer to develop.

By Ed Sperling
Mentor Graphics rolled out its Pyxis custom IC design platform, signaling that it has fully digested and integrated its acquisition last year of Pyxis, which made AMS routing tools. What’s particularly interesting is that Mentor says the new platform is tightly integrated with 2.5D interconnect parasitic extraction, taking yet another step alongside its role in test to position itself in the stacked die world.  Mentor also unveiled a new program for embedded software development that includes both professional services and a suite of tools for Linux, Android, open-source toochains and user interface product and design services.

Synopsys uncorked the next version of its LightTools for illumination analysis for the lighting industry. The focus will be on lighting and solar designs, which are both rapidly growing markets. Being able to apply advanced CAD tools to these sectors should produce some interesting results.

A standard for sharing memory between two chips, which was jointly developed by Arteris and Texas Instruments, has been licensed by 10 SoC vendors in the mobile and wireless markets. You might recognize some of these names: Intel, Samsung, LG, ST-Ericsson, HiSilicon and VIA Telecom.

Ansys’ proposed acquisition of Apache Design Solutions got a boost when the U.S. Justice Department and the Federal Trade Commission reduced the waiting period for the deal. The acquisition is expected to close next quarter.

TSMC issued its Q2 earnings report. Revenue was up 6.5% from Q1 and 16% year over year (in U.S. dollars). Net income was down 0.9% from last quarter. What’s most interesting in the earnings report, though, is the outlook. The company says the “global economic condition has weakened in the last few months,” adding volatility into the supply chain and impacting the demand for wafers next quarter. Consumer and computer sements are expected to decline while the industrial/standard segment will increase.

By Ann Steffora Mutschler
Skyrocketing software development costs, which for years have been “somebody else’s problem,” are now firmly part of the SoC development teams list of headaches. That has made virtual prototyping far more popular, particularly at 40nm and beyond, where engineers are looking at this approach as a way of managing complexity, doing architectural exploration and even performing very early functional verification using abstract models.

These models are meant to provide the design team with a view of the device and its environment at varying levels of accuracy, depending on the user requirements. The hardware model can then be executed within the virtual platform with device drivers to enable concurrent hardware/software development, rather than waiting to write the software until after the silicon came from the fab.

“We see customers going through this interesting next leap of adoption,” said Steve Brown, director of product marketing for system design and verification at Cadence. “Our perspective is that the market has experimented with commercial virtual prototyping tools for the last several years, and through that process the normal discovery of the real requirements has been going on. What I see happening is a real breakpoint where the problem the customer has is now so significant that they are rushing almost in desperation to find anything that can help them with the problem of software and multicore, and the set of challenges that come with that.”

Looking at how virtual prototyping is used today, Marc Serughetti, director of product marketing for virtual prototyping at Synopsys noted, “You have to go back to where the value is. Where does it make sense? What do you get out of those virtual prototypes? If you look at the range of customers we are talking about, the first group of customers—the semiconductor companies—this is where it starts. Especially in markets like wireless and consumer you really have a lot of pressure on the timeline, needing to make sure that the software is going to run fine on the hardware. The whole concept here is starting my software development much earlier. In semiconductor companies that means before any form of RTL is available. That’s really the starting point for all of this—doing software development earlier.”

Earlier doesn’t just mean shifting the development schedule to start sooner so you can finish on time. It also means finding ways to increase efficiency of the software development because the hardware platform complexity is growing, the software content is growing, but schedules are not shrinking.

Some users build their virtual prototypes themselves, but there might be a split within the customer community. For example, a modeling group may be involved in creating the virtual prototypes while an internal set of consumers such as the software engineers within the company actually use it.

“There are various ways of how a virtual prototype gets created,” said Shabtay Matalon, ESL market development manager at Mentor Graphics. “They can be created within a company, they can be created in a partnership between a company and an EDA vendor, but there is clearly a separation between those that are involved in the creation process and those that are on the software side that are using it, which usually are not involved in the creation process.”

Bill Frome, virtual platform manager at Texas Instruments, noted that his company has been leveraging virtual platforms for a number of generations of chips starting back to OMAP 1 days and now currently in OMAP 5.

“The focus has been on leveraging that time from pre-silicon development so we can begin verifying our software and more of our functionality before we actually get to silicon. Like a lot of companies we’ve got shorter and shorter cycle times as far as getting customers into production, so we are seeking to leverage that virtual platform to get more software running sooner to reduce cycle times. That’s really a key for us,” Frome said.

TI has been partnering with Synopsys on its virtual platform development to create the platforms. In some cases Synopsys develops the models for TI and in others TI develops the models. Then Synopsys does the final platform integration and turns it back over to TI.

“There are some other third parties that come in there as well including ARM,” said Frome. “We essentially take that final platform and then internally, we unleash our developers on that to where we can actually boot software on there, begin running some of our use cases before we get to the silicon level,” Frome continued.

Throughout the process communication is critical. Frome noted that there is definitely a communication path as far as when the architects are developing the specs. The specs are shared with the users so they can understand what that model is intended to do. Then, as a model is created, there is a feedback channel because the engineers developing the models may have questions about specific details. The final level of communication involves verification, when the models are actually being utilized.

“What we’ve seen is if we have really well written specs and there is good communication between the architects and the model developers, by the time we get to the final model, that usually goes fairly smoothly—it’s more a clarification,” said Frome. “There will be some updates that need to happen but they are fairly minor in nature at that point.”

Rules of engagement changing
None of this is done in a vacuum, however. The rules of business engagement are constantly changing. Kurt Shuler, director of marketing at Arteris, says some cell phone vendors that design their own chips are now providing requirements to their semiconductor suppliers. “They are communicating very specifically to the chip provider about the specific requirements and they are in the process of using the platform architect-type tools to say, ‘Here’s the scenario, give me a model of your [chip] and I will tell you back what changes I want you to make to your hardware to make it better for me.’ That is a totally new thing.”

Marc Serughetti, director of product marketing for virtual prototyping at Synopsys confirmed this activity. “There is definitely some of this happening. And that happens not only on the software side, but on the architecture of the SoC, too. They want to give feedback as early as possible in terms of making sure that what they have as software will run efficiently on the hardware they are getting from the semiconductor company. So we are definitely seeing this request going back and forth. One reason is to make sure the hardware and whatever software you’re getting from the semiconductor maker meets your requirements, but also to start developing that software earlier. In some markets, like consumer and wireless, it is so competitive that a two-month difference can be huge. The earlier they can start, the better.”

Some go as far as saying these business engagement changes are exactly why ESL is happening now.

“This is the key reason ESL and virtual prototyping is becoming a reality now,” asserted Mentor’s Shabtay Matalon. “In the current level of competitiveness that exists in the marketplace and the complexity and the amount of software that is embedded in each one of those devices, the software people don’t want to be treated as the afterthought in the design cycle. The only way that they will become part of it is if they get models not only before the boards are done and before the processors are fabricated, but even before the RTL is implemented. As soon as they know there is a set of processors that are in the works, they want to participate. They are putting significant pressure on the semis to give them early models of their designs even before RTL is solidified so they can influence the RTL.”

By John Blyler
Everyone talks about innovation. Start-up companies are the most visible vehicle for innovation, but also the most risky with a 1-in-10 chance of modest success. Less visible is the innovation that constantly must occur in fully formed, large companies if they are to continue to succeed. System-Level Design (SLD) talked with the three major EDA companies about the challenges to innovation: Michael McNamara, vice president and general manager of system-level design at Cadence; Serge Lee, vice president and general manager of new ventures in the system-level engineering division of Mentor Graphics; and Michael Jackson, vice president of engineering for physical design at Synopsys.

SLD: How do you foster innovation inside an existing, successful company? How do you create new products inside a large and often bureaucratic commercial organization?

McNamara: A good example was the C-to-Silicon product line, a high-level synthesis tool. This product started inside of Cadence labs back I 1998, originating from a project called Metropolis with UC Berkeley. This project focused on the system-level development space and was the genesis of platform-based design. The idea was that you would have a single platform that you then customize for different usages. A modern example is today’s Droid phones that use TI’s OMAP to incorporate an ARM process, graphics, Bluetooth and other radios into a collection of IP that is aggregated together. Others then start with this platform to add their unique innovation and, wham, in 6 months you have a cell phone.
In 2002, an internal design team was exploring the idea of high-level synthesis. The idea was that a C-code program running a microprocessor could serve as a specification for what would need to be done by the hardware device. In those days, we had a silicon compiler but needed to create a register-transfer-level (RTL) language as an in-between language. It was too hard to go all the way from C to transistors.

Interestingly enough, there was a product in the late 90’s called Behavioral Compiler, but it turned out to be a failure. The promise of high-level synthesis was huge, but it just wasn’t happening. Finding out why was the first goal of our research task and is a key difference between research and implementation (or product) groups. Research labs can step back and examine why things aren’t working as expected. We started by interviewing some two dozen companies that were doing various levels of high-level synthesis.

Our internal R&D group asked them why wasn’t high-level synthesis working? Those interviews identified a couple of issues. One was a manufacturing challenge correcting design issues, i.e., if RTL is automatically generated, how do you accommodate changes such as specification or place and route changes?

Another issue identified by the R&D group was the challenge of reuse. Designers really want a way to specify how the C-code program would be implemented in any given design. One example is the use of decoding and compression algorithms for video movies for different end user applications, from smart phones to laptop computer to large home entertainment theater systems. You are using the same exact algorithms, the each implementation requires a different set of power, performance and quality requirements. Quality issues might be that the smaller screen sizes on a smart phone don’t need the same display resolution as a home theater.

That was the nature of the research part of this project. The researchers gathered a bunch of data, then formulated three or four ideas that they believe constituted the major roadblocks for the adoption of this technology. Around this same time, Cadence had serendipitously purchased a high-level synthesis tool from a company called Get-to-Chip. Suddenly, the researchers at Berkeley labs had a high-level synthesis tool that they could play with and try to implement some of their ideas to address the technology roadblocks, like ECO implementation and the separation of constraints from design.

The Get-to-Chip tool read and generated Verilog, but it didn’t support C or C++ or SystemC. But the researchers could use this tool to develop a prototype. The first step involved research to identify an opportunity. The second step involved building a prototype.

SLD: Are there other ways in which large companies try to innovate new ideas?

Leef: I manage a non-traditional venture portfolio where we attempt to identify opportunities in markets or application domains that are adjacent to Mentor’s products, technologies or know-how. In other words, I’m looking for adjacent places where our current assets or expertise can be leveraged. As the IC and PCB markets are reasonably well understood and served, our focus tends to be mainly in the systems space. There are basically four operational models that we follow, which I’ll list from least to the most expensive.

Adaptation is the least expensive because it augments existing horizontal product with domain-specific libraries, design examples and application notes to create a vertical product. One example would be SystemVision, a horizontal megatronic simulator that is augmented with models applicable to implantable medical devices.

The next least-expensive approach is to repurpose a relevant in-house technology and retarget it to a different domain. For example, we have a good understanding of optimization techniques in the EDA space. We could consider retargeting this technology to a different, but adjacent, domain in the automotive electronic simulation market.
Let me explain. A modern vehicle is a complex distribute compute/control system with a myriad of possible trade-offs. Mapping of software modules to hardware subsystems has tremendous impact on cabling, performance, power, cost and weight. While these trade-offs are managed manually today, it is easy to see how the number of alternatives becomes impossible for a human to comprehend in a state-of-the-art vehicle containing 80 on-board computers and thousands of software modules. While the cost function needed to assess relative “goodness” of alternatives is quite complex, algorithmically, this problem is not very different from IC Place and Route. Thus, optimization algorithms that were originally created for IC optimization can be applied to automotive E/E design.

A third approach to adjacent markets is called incorporation. Here we identify useful third-party companies whose unique technologies can be plugged into one of our existing products. Of course, such plug-ins would need to drastically improve or alter the opportunity size for whatever it is that we have. For example, consider the development of virtual prototypes, which typically include models of microprocessors, microcontrollers and DSP cores. It is quite expensive to develop these models organically. Let’s imagine, that there is a third-party supplier of inexpensive, fast instruction-set simulators. We might acquire a license to such a technology, then snap it into multiple simulation products. We would incorporate that technology as opposed to doing a stand-alone business acquisition.

The last and most expensive approach would be development. In this situation, we have some unique know-how, but that is it. In those cases, we’d invest in R&D to create something new based purely on our understanding of the problem and requisite technologies needed to address it.

SLD: Would Calibre be an example of an R&D project?

Leef: Calibre didn’t come through any kind of structured venture portfolio management. Rather, Calibre was something of a skunkworks exercise, where a bunch of people worked for long periods (sometimes on their own time) without management noticing what they were doing. So they succeeded against organizational forces rather then because some infrastructure was in place to support the development. What I am trying to do is create an environment where programs like Calibre can be identified and nurtured in a repeatable way, as opposed to spontaneously, which is what happened with Calibre.

Overall, we tend to view our innovation effects in a similar way to venture capitalists (VCs). Currently, we are running projects that are in the A, B, and C stages of funding and development—similar to series funding in the VC world (see Figure 1). Basically, we have a Pre-A stage, in which we explore concepts to decide if business plan is warranted. In Stage A, a specific market and product opportunity are identified and we develop a prototype. Stage B consists of creating commercial strength product and engaging with early customers. Stage C is where we deploy the product to broad set of customers and hopefully start to generate revenue.

We do have a significant advantage over independent start-ups and that is a powerful sales organization. So if we determine that what we created has potential, we have mechanisms in place to sell and deploy the product and monetize the opportunity.

Fig. 1

SLD: How is R&D funded within a large company?

Jackson: We fund new technology and product development in our business units as opposed to an independent R&D organization. We have had many successful innovations doing this. Some recent examples include the creation of a new router (Zroute), new test compression (DFTMax), new RTL exploration (DC Explorer) and a new constraint analyzer (Galaxy Constraint Analyzer).

SLD: Do you favor internal development or acquisition as a way to innovate technology?

Jackson: Generally we rely more on home-grown development. This is especially true in areas where we are creating a replacement product or extending a product to address an adjacent area. Homegrown development is also used for new product areas, but acquisition also can play a role here.

By Ed Sperling
Synopsys expanded its Discovery verification platform with a regression and analysis extension called CustomExplorer Ultra. The focus is analog and mixed signal, which is a hot topic these days with the momentum over 2.5D stacked die with interposers. Case in point: Texas Instrument’s purchase of National Semiconductor.

TSMC filed its annual 2010 report with the U.S. Securities and Exchange Commission. The report shows that 2010 sales hit a record $14.5 billion, up 68% over 2009. Net income was $5.68 billion, an increase of 84% year over year. The foundry noted in the filing that capital expenditures this year will total about $7.8 billion, an amount that may fluctuate depending on market conditions. It plans to add capacity to its 300mm and 200mm wafer fabs, develop process technologies at 28, 20 and 14nm, and invest in solar and LED production facilities. Also of note is that fabless companies accounted for 79% of 2010 sales compared with 80% in 2009.

Intel showed remarkable resilience in its earnings, as well. GAAP revenue for 2010 was $12.8 billion, up 25% over 2009. Net income was $3.2 billion, up 29% over the previous year. For the first quarter, Intel’s data center group showed the strongest growth, up 32%. Atom sales were up 4% to $370 million.

Those numbers coincide with strong sales growth at IBM, which got a boost from increased mainframe sales, and at Apple, which was bolstered by both iPhone sales over the Verizon network and new Mac sales. The iPhone uptick helped Qualcomm, as well.

By David Lammers
Qualcomm CDMA Technologies said it will not use a high-k/metal gate (HKMG) process for most of the chips it makes at the 28 nm node, sticking with a poly/SiON gate stack. The company described the rationale behind the strategy, which because of Qualcomm’s size will have a major impact on the foundry business, at the 2010 International Electron Devices Meeting (IEDM) held in San Francisco.

Jim Clifford, senior vice president of operations, said the decision to stick with a poly/SiON process was related to timing and cost issues. “High-k inherently requires more mask layers, and there are defect density issues that make it a little more challenging,” Clifford said in an interview at IEDM.

Qualcomm is not closing the door on HKMG. “There is a class of products where you need it,” Clifford said, including some chips made for tablet computers and the “extremely high-end” smart phones. Qualcomm may use the HKMG processes at the later stages of the 28 nm node for those products, which require roughly 2GHz and higher frequencies. But for most of its high-volume smart phone chipsets, Qualcomm will stick with the less expensive poly/SiON process.

The company isn’t alone in taking that route. Texas Instruments is following a similar strategy, according to industry sources.

In a luncheon keynote speech at IEDM, Clifford emphasized that while Qualcomm is hungry for smaller and faster transistors, he is growing increasingly concerned about the costs involved with EUV lithography and other technologies required to stay on a Moore’s Law cadence. “I’m all about costs,” Clifford said.

In an IEDM paper on its 28nm technology, Qualcomm technology director P.R. Chidambaram said a high-k process without significant strain on the channel does not offer an advantage over a poly-SiON process with strain techniques. “A HKMG process with strong strain engineering offers a substantial speed gain but with a higher cost, making it more suitable for smartpad/tablets and extreme high-end smartphones. A poly/SiON process enables a quicker time to market with less process risk, and historical defect density reduction,” he said.

Most of the Qualcomm smart phone chipsets, based on the company’s Snapdragon processor core, run at 1GHz or less, and can be served by going to dual-core designs. Geoff Yeap, senior director of technology, said the Snapdragon-based chips sold by Qualcomm “have huge volumes,” adding that the high-k processes at the major foundries “are not ready yet.”

Yeap said Qualcomm will move a limited number of products to the HKMG foundry processes at a later point. While HKMG transistors generate higher drive currents from the increased inversion charge, the switching capacitance increases due to the need to charge up the gate to gain the higher drive current. Linear drive current (Idlin) is more important than saturation current (Idsat) for Qualcomm, he added.

Although HKMG helps out with power leakage at the gate, it doesn’t do much to improve power lost at the substrate and in the source-drain areas. Qualcomm has been able to contain power consumption by using well biasing, in addition to circuit techniques such as power and clock gating. A specially designed power-gating switch was described by Chidambaram, who cited it as an example of the close cooperation between Qualcomm technologists and engineers at an unnamed foundry partner.

The 28nm node offers major advantages to Qualcomm, which combines RF, digital processing, and analog functionality on its SoCs. Moving from 45nm to 28nm design rules supports a 2.4 times increase in gate density, a 55% reduction in power and a 30% gain in frequency, said Chidambaram.

Qualcomm calculated the gate leakage percentage contribution to the total leakage in various operation modes. Source: 2010 IEDM paper.

At IEDM, some technologists expressed surprise at Qualcomm’s decision to stick with a largely SiON process, citing better electrical control of the channel as well as improved variability from HKMG technology. Overall, the industry was in a holding pattern, unable to scale the effective oxide thickness after the 90nm node until high-k came along, resulting in a reliance on strain techniques to boost speeds.

GlobalFoundries has a technology road map that relies on a gate-first HKMG for all of its low-power and high-performance offerings. Qualcomm’s decision to stick with a largely poly/SiON process raises the question of whether GlobalFoundries will switch gears and offer a poly SiON process at the 28nm node, in part to support Qualcomm, the largest foundry customer worldwide.

Clifford was asked if Qualcomm would use GlobalFoundries as a foundry supplier at the 28nm node, but he said he preferred not comment, saying that choice of foundries is still under discussion.

A GlobalFoundries spokesman said all of the foundry’s 28nm offerings on its “public roadmap” are based on gate-first HKMG. “However, we are offering a 28nm Poly/SiON technology at the specific request of certain customers with product applications that do not require the performance and leakage benefits provided by our HKMG technology,” he said. GlobalFoundries will not be enabling a design ecosystem around 28nm Poly/SiON.

He added that the HKMG ramp is “still on track and we are seeing significant customer traction. We expect HKMG to be the volume leader at 28nm in both low power mobile applications as well as high performance wired applications.” Multiple customer designs have been silicon-validated, and test chips are in prototyping at the company Fab 1, in Dresden, Germany, and are on the way to early risk production.

GlobalFoundries and TSMC have engaged in a marketing battle over the benefits of their competing approaches to HKMG: gate first for GlobalFoundries and gate last for TSMC. GlobalFoundries claims that its gate first HKMG process has a 10% to 15% cost advantage over the TSMC gate last process.

Yeap said that at the 22/20nm generation, Qualcomm plans to use HKMG for nearly all of its products.

By Ed Sperling
Mentor’s Robin Bornoff does what any good engineer would do when the corporate beer fridge goes on the fritz. He figures out not only how to de-fritz it, but to improve it. But there are two things that stand out as suspicious here. First, non-Brits always assumed British beer is best served at room temperature, so why is the beer in a refrigerator in the first place? And second, it’s rather odd that no one has ever drunk it considering the British reputation for beer. We’re waiting for the WikiLeak.

Cadence’s Jack Erickson is in a self-described evolution mode. Even his wife has commented on it (his words, not ours). Finally, a family member who recognizes the importance of what we do in this industry. This may be real evolution.

Mentor’s Colin Walls pulls out the crystal ball from the closet and lays bare four consistent themes surrounding Android, multiple cores, power consumption and the growing functionality of graphical displays. The future is upon us.

ARM’s Ed Plowman expounds on when a pixel is not a pixel. This sounds like a magic trick. Now you see it, now you don’t.

Speaking of ARM, Daniel Nenni takes a look at Intel vs. ARM, and concludes the really interesting development is Linaro—an open source initiative that includes IBM, Samsung, TI, Freescale, ST-Ericsson. So far it only supports ARM processors, but given the amount of business these companies conduct with Intel don’t count on it to stay that way.

Si2′s Steve Schulz looks at how standards will support the industry’s five-year challenges in the first of what what promises to be many parts. Where were you five years ago?

Cadence’s Richard Goering reports on a presentation by STMicroelectronics’ Romain Feuillette about using the SKILL language to code parameterized cells. Hearing what companies like ST are doing in the real world is always interesting, and this one is very good.

Doulos’ John Aynsley, writing in Synopsys’ VMM Central, digs into transaction-level communication in VMM and which options are best. If you’re involved in verification, particularly on the VMM side, this is required reading.

By Ann Steffora Mutschler
For the first time ever, China recently earned fastest supercomputer bragging rights with its Tianhe-1A supercomputer, which can perform 2.57 quadrillion computing operations per second. The machine has been successfully used to survey mines, forecast weather and design high-end machinery.

While it has caused concern, it is important to note that the Tianhe-1A uses the latest off-the-shelf Intel and Nvidia processors. What set this supercomputer apart is the effort that went into streamlining the interconnects, realizing that was the bottleneck.

“Engineers don’t always do that with SoCs. They don’t think about the critical path. The interconnect is now the critical path,” said Kurt Shuler, director of marketing at Arteris.

With so much time today spent on individual bits of IP, developers don’t always think about how it’s all going to connect into a system. The sheer number of IP blocks being put on SoCs today demand that the interconnect be addressed differently than traditional techniques. The pain of trying to connect hundreds of blocks of IP and then make derivatives of the chip has become so intense that engineering teams are adopting new approaches to buses and crossbars in order to reduce the number of wires in an SoC.

“Mathematically, once you get to a certain point when you have so many blocks of IP, it becomes basically impossible to tie it together with wires because even though the transistors are shrinking to Moore’s Law, the wires don’t. The wires are the same size today that they were on a 286,” he pointed out.

Unfortunately, there have been a limited number of ways to address this. Metal layers can be added, but that just makes the profile of the SoC look like, “a wedding cake from hell,” with as many as nine metal layers, Shuler said. With each mask costing millions of dollars per metal layer, the problem is at a critical pain point.

Another way to address interconnect challenges is with early floor planning. Given the smaller diameter wires on the lower-level metal layers, initial floor planning has to be done early to map out the location of the CPU, memory, video, and other components on a block diagram. As more and more wires are added to the chip, they have to be spread further and further apart. This doesn’t just include the wires because there is some logic that comes into play. When a bus or crossbar is used, additional wires and logic must be added for crossbars.

As such, many semiconductor designers are turning to network-on-chip to solve these issues. The concept of network-on-chip originated with the realization that crossbars could no longer fit onto the chip between different IP blocks and did not do anything to address the growing number of wires.

Texas Instruments has been using network-on-chip technology from independent suppliers since the early part of the decade in its wireless business unit with a great deal of success, according to TI SoC architect James Aldis.

“We have an approach to using it that integrates system-level design, meaning transaction-level modeling and optimization of area and latency and throughput of the network and chip itself. That permits us to have networks-on-chip ready at the very earliest stages of system-on-chip integration. We are one of the most experienced users of really big networks-on-chip in the world of system-on-chip design and we are very, very positive about it,” he explained.

“Where the system-on-chip interface in the past has been a bottleneck for system-on-a-chip time-to-market has not been the case for us for a long time now and we are very pleased with that. I’m not trying to say there aren’t some significant challenges in the future, and certainly with the shrinking of process technologies things are going to get quite exciting in the next few years,” Aldis added.

With interconnects today the pain is enough that people know that if they drag their feet any longer, kluge things together, or add another crossbar, the design is going to break. That will affect the IP on the chip or make the chip worse. It is no longer a “nice to have,” Shuler said.

By Ann Steffora Mutschler
With the typical cost of software accounting for 40% to 60% of an SoC, semiconductor OEMs are under more pressure than ever to meet margins. As a result, they are drawing on their ecosystem partners to provide a more complete foundation including hardware, software, FPGA prototypes, verification IP and virtual models, as well as an increasing demand for open source software support for their SoCs.

To be sure, software acquired through an open source model can allow faster time to market by leveraging publicly available technology. But the biggest limitation is lack of support, unless the software comes from a commercial provider.

How does this play outside in the hardware world? “Software is something you can change relatively easily, whereas hardware IP, once it’s in silicon you’re stuck with it,” said Simon Davidmann, president and CEO of Imperas and founding director of Open Virtual Platforms (OVP). “Another big difference between hardware and software is that there are very few people designing hardware compared to people writing software. If there are 100,000 apps for an iPhone then there must be 300,000 or 400,000 people trying to write them. In the hardware world, there are only about 100,000 hardware engineers globally, and yet there are many times that just developing software for the iPhone.”

Clearly, then, the software scale is completely different from the hardware scale, and this has an important effect on open-source ideas.

“With the GNU tools they can apply to tens of thousands of people easily, but in the EDA world that’s not really the case,” said Davidmann. “The closer you get to the hardware, the less appropriate an open source community is. Open source is good from a, ‘Let’s have a compiler that you can use for free,’ but no user fiddles with the open source bits of GCC (GNU Compiler Collection) or GDB (GNU Project Debugger) that doesn’t fiddle with Linux. It’s very useful for the hardware guy to make use of, but then they tend to have to pay people to do it.”

Where it works best
One of the biggest challenges companies face in implementing a design is in the verification phase, which is why it consumes the largest chunk of the non-recurring engineering expenses in any design. Prasad Subramaniam, vice president of eSilicon’s design technology, said this is exactly where open source can help.

First, open source software could be of help in the actual verification of the IP that is being stitched together as part of the SoC, especially for IP that is standards-based like a USB interface or a PCI Express interfac. “Because it is in the public domain, you can develop verification IP in an open source manner. That’s one of the advantages. People who do verification today license this kind of IP from various IP providers, and it will be significantly helpful for them if such verification IP is available in the open-source model as it will make it easier to access, allow them to do what-if analysis, experiments and so on before they go on and purchase something that is industrial class,” Subramaniam said.

Second, open source software support can be helpful in system-level verification. “Once you have designed your SoC, you want to try and run system-level testbenches, for example. If you build an ARM-based subsystem, you want to try and emulate it in an FPGA type of environment. You can get a board that contains an ARM chip with an FPGA and you can implement your logic, and this has an interface to your PC and you can control the software from your PC but the actual software will be running on the ARM test board and the FPGA,” Subramaniam said.

Similarly, John Koeter, vice president of marketing for Synopsys’ IP and Systems Division, said the use of virtual prototyping at the system level has allowed a fair share of the top 10 global semiconductor companies to pull the time to ramp into production by as much as six months earlier than with older approaches.

“Today many companies still use what I call a waterfall model where they develop the hardware, they get to the golden RTL or even the chip and then that’s when they’ll start developing the software on the physical prototype itself or maybe on an FPGA-based prototype of the chip,” he said. “That process is done in a serial or waterfall manner, and obviously that pushes out the entire development schedule significantly. We are really working with the semiconductor companies to pull in the start of the software design much earlier using virtual prototyping. In a fast moving market, ramping to silicon six months or even three months your competition easily yields 10% to 15% revenue through additional early wins.”

Models Are Key
The key to virtual prototyping involves the models, and while not disclosing any plans, Koeter noted that Synopsys intends to enable a significant effort within the open source community for creating models. He said plans are in development. Also, with its recent acquisition of Virage Logic, Synopsys gained the ARC cores, and is fully supporting the various software stacks that run on an ARC core, including variants of Linux, etc.

On the surface, it appears that Synopsys may be finding out what Imperas did, namely that people want control over the simulation models. They didn’t want to get into the insides of the simulator. But they do want a commercial company to professionally service and support the tools, and they want control over the IP and the models, Davidmann said. “The great thing about open source is that it allows you to see what’s going on, modify it and use it, and then that way it gives you freedom and can take things further.”

Imperas has a closed-source commercial simulator and open-source models (developed from published documentation and in such a way that the user can extend them). “This is very different from the SystemC approach of an open-source simulator—developed and funded by the big EDA companies, but which isn’t really open because you have to be part of their club and paying to be able to enhance it and redistribute it,” he said. “What this means is that it is about three or four years old. It’s a commercial ploy in that Cadence, Mentor, Synopsys have their own tools and simulators that use SystemC as proprietary professional solutions and the OSCI simulator is the poor cousin so it is several versions of a standard behind.”

Imperas also uses an Apache License, which Davidmann noted is good for commercial organizations and does not have the same requirements as the GNU license.

“For a silicon vendor that makes them very nervous. If [they] download a bit of IP and put it in [their] chip, the rules aren’t very clear yet because open source is all about software, it’s not really about hardware. Hardware tends to be covered by patents and software by copyright. In software if you use a GNU public license, if you link it to any other pieces of software, all of that software has to be covered by it so it really promotes the spirit of ‘free to use.’ You are allowed to access the source, and if you use it you’ve got to make your source available so it furthers the usage of it. Whereas in a commercial organization, there’s no way you would want to include a piece of hardware on your chip if you had to give away your hardware design. You want to protect that and hide it because it’s all your tricks and magic. In the hardware world people are much more nervous about the licensing of open source.” Davidmann said.

A new approach to open source for ARM-based SoCs
There is another approach that ARM, IBM, TI, Samsung, ST-Ericsson and Freescale have come together on to address OEMs that demand the best open source support. “They want the latest kernels, they want the latest tools, they’ve got to be stable. It’s more than just throwing them a BSP and hoping it is good enough. They want more than that, and that’s what Linaro was born to do,” to make it easier for ARM partners to deploy the latest, optimized technology into Linux based products, explained Rob Combs, head of global alliances at Linaro, a not-for-profit open-source software engineering company that launched in June.

Linaro stemmed from conversations with OEMs about the difficulties of developing open source—the need for great tools, the latest kernel, not having to rewrite BSPs from silicon partners, he said. “They want more of that support in the upstream trunk rather than less and they want more investment so we can fix any problems that crop up. That’s more than any one company can deliver individually. There needed to be a collaboration vehicle to deliver this for the ARM partnership. Linaro was born to make it easier and quicker to develop complex open source products based on these new whizzy SoCs that are coming out.”

Linaro does essential engineering relevant to multiple verticals markets and to multiple distributions. At the application framework level, the organization aims to helps distribution creators get a better base to start from, which is enabled on multiple ARM platforms for more commonality, and less fragmentation. In terms of development tools, Linaro believes it can provide better tools to build optimal software, which is are used at all levels of the OS, and which is crucial to achieving the best PPA. All of this is part of the move toward a common kernel and is enabled on multiple silicon platforms, Linaro said.

In the process of ramping from 20 to 80 engineers, the organization will deliver every six months a harvest of all of the latest, freshest code, Combs said. Linaro’s next step is to show proof points at upcoming Linux conferences.

By Ed Sperling
Mentor Graphics’ Calibre Design-to-Silicon solutions were used in the development of TSMC’s 28nm Product Qualification Vehicle. No surprise there. The foundry already standardized on Calibre. TSMC also standardized on Synopsys’ Galaxy Implementation, including advanced routing rules, low power and signoff capabilities for the same chip.

Synopsys launched a DesignWare USB software alliance program to create an ecosystem for USB software providers for drivers.  And it rolled out the Time Division Duplex mode for its Long-term Evolution Model library for physical layer system simulation. And if that wasn’t enough, the company renewed its OEM relationship for FPGA synthesis software with Lattice.

TI licensed ARM’s Cortex-A series processor core, aka Eagle, for its future OMAP platform. This builds upon a similar relationship the two companies have had in the past for OMAP processors with ARM cores.

TSMC’s sales, which are a good gauge of how the design industry will fare, increased 3.0 in July vs. June. It was up 19.4% over July 2009, showing just how far things have improved.