By Ed Sperling
Mentor Graphics’ Calibre Design-to-Silicon solutions were used in the development of TSMC’s 28nm Product Qualification Vehicle. No surprise there. The foundry already standardized on Calibre. TSMC also standardized on Synopsys’ Galaxy Implementation, including advanced routing rules, low power and signoff capabilities for the same chip.

Synopsys launched a DesignWare USB software alliance program to create an ecosystem for USB software providers for drivers.  And it rolled out the Time Division Duplex mode for its Long-term Evolution Model library for physical layer system simulation. And if that wasn’t enough, the company renewed its OEM relationship for FPGA synthesis software with Lattice.

TI licensed ARM’s Cortex-A series processor core, aka Eagle, for its future OMAP platform. This builds upon a similar relationship the two companies have had in the past for OMAP processors with ARM cores.

TSMC’s sales, which are a good gauge of how the design industry will fare, increased 3.0 in July vs. June. It was up 19.4% over July 2009, showing just how far things have improved.

By Ed Sperling

Mentor’s Thomas Bollaert takes a look at what he calls modern Luddites and some of the change-averse comments he received on some customer visits. The Luddites, by the way, were a group of disgruntled English weavers who opposed mechanized looms in the early 1800s. (We looked it up.)

Along the same lines, Cadence’s Jack Erickson talks about the relationship between Madonna and chip design. Actually, Madonna has nothing to do with chip design. But think of how it might change if she did.

Andrew Piziali and Texas Instruments’ Jim Bondi, writing in Synopsys’ VMM Central, talk about getting the chip architect involved in the verification process. Sounds like a great way to make sure the chip can be verified relatively quickly. This is sort of like standing in someone else’s shoes when they’re two sizes too small.

Tets Maniwa, writing for Gabe on EDA, looks well beyond the presentation of next-generation tools for next-generation processes. It’s a great analysis of a lot of issues in SoC presented in very readable and digestible bites. Nice job.

Virage Logic’s Hezi Saar examines the rising risk of failure in the communications market, which is where the majority of leading-edge SoCs are going because those are the only markets that can justify the development cost with large enough volumes.

Cadence’s Samta Bansal takes a hard look at why 3D stacking has become such a hot topic and what it needs to move into the mainstream—lots of work.

Mentor’s John Day takes a stand on banning cell phones in cars. He’s against the ban because it will limit the safety advances that are in development. Interesting argument.

Cadence’s Tom Anderson, in the same vein, questions whether it’s good for participants to use social networking while they’re attending an Accellera meeting. In our view, no, but anyone over 35, not to mention people who occasionally use multi-syllabic words like disintermediation, will miss the importance of this social networking revolution.

Daniel Nenni takes a look at Mentor’s acquisition of Pextra for 3D field solver technology and why you should care. He even predicted the acquisition, so kudos to Mr. Nenni for that one (unless, of course, Mentor got the idea from reading his blog). Field solver technology is becoming increasingly important technology below 40nm for effective circuit simulation.

Cadence’s Jason Andrews digs down into accessing physical memory and registers from virtual platforms. There’s some good, solid technical insight here.

And last but not least, Mentor’s Jon McDonald compares ESL to an insurance policy and asks how lucky you feel. It sounds a lot like a line out of Dirty Harry movie: “You’ve got to ask yourself one question: ‘Do I feel lucky? Well, do ya punk?’”

By Ann Steffora Mutschler

The age-old question of whether to make or buy is time immemorial, and is particularly true for the cyclical semiconductor industry. At the end of the day, the answer comes down to how the decision maker feels about having or losing control.

Fifteen years ago, whether to make or buy something—be it the design, libraries, memory, implementation, verification, testing, mask set, even manufacturing—was not relevant because an alternative didn’t exist. All semiconductor companies were integrated device manufacturers (IDMs) and did everything from concept to finished product as their title implies. Chips were created by a company for their own purpose: to be put it into a system and sold in a box, whether that was a PC or a mainframe. Think IBM or Digital Equipment Corp. (DEC).

As Moore’s Law allowed for the increase of chip complexity, combined with demand for new and different products, along with other market dynamics, the fabless semiconductor industry was born. Until the mid-’90s, the majority of chips manufactured were used in data processing and computing applications. Then came the explosion in consumer-demand for technology, spawning new and varied semiconductor and systems companies to meet the needs of markets.

These changes drove the disaggregation of the IDMs and served as the genesis of the standalone EDA, capital equipment, tester, packaging, and foundry industries.

As time has moved forward, with leading-edge process technology at 40nm, it now makes increasing sense in many cases to buy some of the individual pieces in a chip. And for many companies, it is not enough to simply purchase individual pieces. They now want a third party to pull everything together. It all comes down to the numbers, said Kalar Rajendiran, senior director of marketing at eSilicon.

“In 2004, when 0.13 micron was the leading edge, a mask set probably cost $300,000. Today, the bleeding edge is 40nm and a mask set is about $1.5 million, depending on the number of layers. That is a five-fold increase in the mask set cost over five years. Leaving out really large semiconductor companies like nVidia, Broadcom, and others, who are in the billions of revenue, there are lots and lots of companies that are in the $100 million dollars or less range,” he said. “These companies have good products, but in terms of the investments they need to make in order to get a product out it could easily be $30 to $40 million to completely produce a chip from the idea all the way to fully qualified product.”

Most semiconductor companies don’t have that kind of funding in big pieces. Even in the heyday of VC funding, a semiconductor company would never get $30 million or $40 million in one chunk. “When you are doled out a few million here and there, you can’t really use that to build an entire team,” he added.

The past five years have seen complexity and costs increase so much that if you look at it just from the cost side, it is impossible for all but the largest IDMs to go it alone. That leaves the majority of semiconductor players weighing the pros and cons of outsourcing.

Brani Buric, executive vice president of marketing and sales at Virage Logic, observed that for customers the ‘make vs. buy’ decision can be broken into three categories.

First, more noticeably today than five years ago, is whether the company going to do design in-house or buy complete design services. “Five years ago I would say that the whole COTS business as a part of the fabless process was at a high,” Buric said. “What has happened in the meantime, especially as we are moving to new processes, the cost of development has become very, very high. That includes having an engineering team, having folks in-house developing IP, doing test chips, test process, paying for mask sets—every single component is going up. So the first ‘make vs. buy’ decision occurs once somebody has a spec. Do they need to do design in-house or they can find somebody who is in business of doing designs and get the design done or even get silicon back?”

Buric believes this is the driving force behind companies such as Global Unichip, eSilicon, Open-Silicon and VeriSilicon. Even traditional ASIC companies such as Texas Instruments, LSI Corp. and NEC have outsourced their manufacturing. “There is definitely a new trend where people have an idea, they have a spec, but they don’t need to implement the spec [themselves], and that is the first breaking-point decision in the ‘make vs. buy’ process that we didn’t see five years ago.

Second, if the customer believes they must do their design in-house, it would likely be in a case where they believed their spec had tremendous value that they didn’t want to share. Then, they would make the decision about what they had to build in-house vs. what they could buy or outsource.

In some cases, a company may do its own RTL design but outsource the physical implementation and the back-end implementation possibly to a company such as eSilicon or Open-Silicon. Connected to this is the choice of whether to completely own the design. The difference is basically long term and what they want to accomplish with the design. “If they believe that long-term they have a manufacturer that will give them good prices for silicon and they stay with a single source (which are typically designs that have high value beyond the cost of silicon), then they may stay with them and just say, ‘You own IP, I don’t care. My IP is in my specification,’” Buric noted.

However if the company is more price-sensitive, they may decide at the beginning to go with outsourcing and later on decide to move. For example, they may do the design and back end in-house because they are strong enough and don’t need external help. In that case, they would immediately become the owner of the IP rather than let their design services provider own the IP because that gives them independence in future decisions. That gives them the freedom to move from one foundry to another.

Third, for every single piece of IP that a company must use and decides to own, critical decision-making points concern whether that IP is available and if it is silicon-proven. “If it is available, is silicon proven and fits their needs, then in 99% of cases the decision will be to buy. If it is not silicon proven then they may think about making it. The only time when people don’t make the decision to buy is if there is no IP available or if there is no service company that has a proven track record of developing a specific IP,” Buric said.

Texas Instruments is intimately aware of the ‘make vs. buy’ decision, especially in regard to its manufacturing. Since November 2001, the company has gradually shifted all of its logic manufacturing to foundry partners – a big change for the chip giant, which at one time in its history was one of the world’s biggest IDMs, and owned everything from the wafers to the capital equipment.

However, the changes have allowed the company to remain nimble in the market. Tom Thorpe, vice president of external development and manufacturing at Texas Instruments explained, “One thing that we are really clear about at TI is that we want to maintain independence and be able to move loadings from one foundry to another based on quality, cost, delivery and service so that we can maximize our responsiveness to our customer base. The IP is a big part of that discussion because if you partner with a foundry and use IP that has been designed only for that foundry, or which that foundry has paid for, then you can’t take that IP somewhere else.”

Thorpe noted that one of the key factors in TI’s decision-making process is figuring out how to maintain independence. “We’re outsourcing a whole lot of our production, especially on the leading edge, so we have to figure out how to maintain our independence. That means you have to either do the IP yourself or contract with some firm to do it for you. And we have to pay for it. Otherwise the foundry pays for it and it’s going to lock us in. Certainly you want to have components of the IP which are owned by your company.”

A major part of that decision is what makes one company’s product different from another’s, but that differentiation changes over time. “There is always something new that you want to keep internal in order to have a competitive advantage,” Thorpe said. “Over time, whatever it is that you were keeping to yourself becomes common enough that other people start to do it and then it is no longer a competitive advantage. When that happens you might as well buy it from some third party. It’s just a natural progression. There’s nothing we can do in this industry that people don’t know about over time.”

By Ed Sperling

For the better part of two decades there has been a steady stream of predictions about the abrupt end of Moore’s Law, but it now appears the formula for doubling the number of transistors on a die every couple years will simply dissipate rather than fall off a cliff.

While companies such as Intel and IBM continue to develop road maps that extend their road maps all the way to 11nm and 7nm, respectively—at least carrying development through the end of the next decade—the reality is that SoCs will likely contain components built using multiple process nodes. There will undoubtedly continue to be development at the most advanced nodes, but there also will be some components that reach back to 130nm, and some all the way to 180nm.

“At some point Moore’s Law runs out of steam and there will be a crossover to different approaches,” said Charlie Janac, CEO of Arteris. “You can make 11nm steppers and do physical vapor deposition, but they’re going to be very pricey.”

Developers and chipmakers say economics already make stacked die viable. Now it’s just a matter of putting all the pieces in place to make it technologically possible.

Texas Instruments, for one, is looking at a number of different integration models including vertical integration using through-silicon vias (TSVs), said Robert Tolbert, TI’s OMAP platform marketing manager.

“When you have a chip that includes wireless, LAN connectivity, Bluetooth and GPS (global positioning systems), all of those technologies have to be integrated with each other,” Tolbert said. “Through-silicon vias are one approach we are looking at. There also has to be more integration at the package level.”

The stacked die approach
TI isn’t the only company looking at stacked die as a potential solution. All the major chip developers are. In fact, the standards group Si2 currently is working to develop standards for 3D stacking, which should speed its adoption once those standards are ready.

“We’re seeing a lot of attention being paid to 3D lately,” said Bernard Murphy, chief technology officer at Atrenta. “It’s getting a lot of air time with companies like ST and Qualcomm. Folks are trying to figure out how to combine more functionality into a chip. It’s a difference of using known pieces or trying to develop an overall optimized problem. A stacked die allows you to partition on the fly for a known device because you are not building those functions as part of a die.”

This is different from the system-in-package approach taken by memory makers, which have been churning out a rudimentary stacked die for several years in the form of flash or DRAM. That’s more of a system-in-package approach to put more memory into a single package.

The real work is under way inside R&D department at large companies and inside universities to develop chips that stack processing, logic and memory in various vertical layers, thereby reducing the amount of distance between the pieces and greatly simplifying timing and verification—currently the two biggest problems in developing SoCs. Initial versions most likely will contain two layers, but more layers will be added over time.

“The technology is not ready, and neither are the standards and the way all this technology gets used,” said Javier Delacruz, director of eSilicon’s packaging group. “But there is definitely a need for this. As we move down technology nodes and you can fit more on a chip, the cost per unit area is increasing. The best way to address that is to take the non-critical pieces off the chip. It’s a no-brainer. So you take out the memory and add an interface.”

Figure 1: 3D structure with through silicon vias. Source: MicroMagic

That also eases some of the power modeling issues for chips, he said. “Right now, everything is very high power because of the power supplies needed for all the parts of a chip and it’s thermally intensive. But with TSVs, you don’t need to drive a DDR at 1.8 volts.”

What also makes this approach attractive is the ability to mix and match lithographic geometries. A core for one function can be manufactured at a different process node than a core for a different function or a block of memory. In addition, the distances needed to reach various components can be shortened by stacking them rather than routing across a chip, where it can be affected by other traffic, Delacruz said.

What’s here, what’s missing
While this is considered a likely solution for building chips, it’s still largely a research project.

“3D TSV adoption is very application-driven,” said Rajiv Maheshwary, senior director for customer marketing at Synopsys. “In 2010 you will see MEMS, CMOS image sensors and homogenous memories in production. Heterogeneous system integration (logic + memory, logic + RF, logic + logic) will take some time—probably somewhere between 2011 and 2013—for several reasons. First, the supply chain is not ready. That includes the foundries, outsourced assembly and test and EDA tools. Second, the cost of building fine-grain TSVs in the 5 to 10 micron range needs to come down before design teams can move to 3D. And third, business issues exist such as who is best suited to make 3D devices and IP-related issues.”

Thermal issues also are a problem. Getting the heat out of a chip is hard enough in a single layer. In multiple layers, the heat generated through leakage can impact signal integrity or, in the worst case, destroy a chip. Maheshwary said that over time he expects to see three types of TSVs because of this—signal, power and thermal—each with a different pitch.

In addition, there need to be standards for design rules and via patterns, which need to be developed by the memory makers. Also needed are interfaces to improve communications across the chip. The long-term outlook includes separate clocks, separate power and logic to manage communications between the various components, said Geert Rosseel, vice president of technology at Arteris.

“The question from our standpoint is what happens in the middle,” he said. “You want a unified architecture but you also need to turn off certain parts of the chip. You need some way to manage all of that because on chip you may have 32-bit, 64-bit and 128-bit signals. The only way we know of doing that is by packetizing the communications over a unidirectional link with a network on chip structure.”

And finally, the existing tools need to be evolved to be able to do place and route and verification on stacked die. EDA companies say tools will have to be enhanced to focus on TSV modeling, which is largely thermo-mechanical analysis, design for test, physical design, and signoff, which includes parasitic extraction, timing/IR drop and thermal analysis.

By Ed Sperling

“What if” is an indelible part of the lexicon of every SoC architect and design engineer from the front end of the design flow all the way to manufacturing, but while the terminology will persist for years to come the answers and the value of those answers are starting to change.

Complexity, cost and the need for better integration have simultaneously increased the number of variables and limited the amount of variation that is acceptable. It also has pushed more responsibility to the front of the design process where these kinds of tradeoffs can be made, while increasing the risk that something can go very wrong downstream.

“Complexity has tremendously affected the what-if scenarios for developing chips,” said Jon McDonald, technical marketing engineer for the design creation business unit at Mentor Graphics. “Historically, hardware development has been fairly straightforward at the high levels. An experienced designer could make an educated decision on what should be done in hardware, how much parallelism was required and what performance was required from each block. The number of choices was relatively small and the tradeoffs between the choices was relatively clear. Today the explosion of gates, performance points, IP and tradeoffs between software and hardware has made it much more difficult to make an educated decision on what should be done in hardware and what performance is required from each of the hardware blocks.”

McDonald said the only way to quantify architectural tradeoffs is to create a model and run a simulation. That’s a lot different than the old way of creating the architecture and fiddling with the layout after the fact, which some companies continue to do even at 65nm. Even with advances like computational scaling for manufacturing, most foundries still believe new rules will be imposed by advanced processes, starting at 32nm and continuing forever afterward. The changes at the architectural level add rules at both sides of the design.

“This what-if analysis on the users application scenarios is even more important today than in the past simply because the number of choices has exceeded the ability to understand the interaction of those choices,” said McDonald. “Yes, figuring out the variables and deciding which variable combinations to run the simulations on is more difficult today, but it’s the best option for making the tradeoffs that need to be made.”

More choices but less freedom
At 45nm and beyond, there are far more choices to be made. Smaller geometries mean more real estate, whether that’s taken up by additional CPU cores, more memory or different sizes of buses. In the future, it is likely to be split into multiple power domains, as well, which so far has largely been a challenge for the smart phone chip makers.

“We have a ton more gates available and that gives us a lot more wiggle-room in some ways,” said James Aldis, SoC architect at Texas Instruments. “But I suppose it is true that in other ways we are more restricted. Our power architecture is more complex and the constraints imposed by software are more severe, for example. So working out how to integrate that extra CPU is a more detailed and challenging task than it used to be.”

What that also means is the answer to “What if” has to be more accurate than in the past. Instead of an estimation of possibilities, they need to be more tightly defined further up in the design process.

“There isn’t an explosion in technical capability, but there is an explosion in the complexity of what the tool users need to do,” said Bernard Murphy, chief technology officer at Atrenta. “This is being driven by handset applications where there is incredibly complex optimization of everything from the power domain to retention and clock and voltage states. If you’re using a cell phone and you flip to an MP3, how do you optimize the battery charge life.”

While in the past, answers to “What if” often cam in the form of estimations, they increasingly are looking like specifications. Murphy noted that the gap is growing between the architectural “What if” and the implementation side. “If you place all your trust at the architectural end vs. implementation, is that overly trusting of the architecture?”

The risks of rigidity
Murphy isn’t alone in asking that question. Frank Schirrmeister, director of product development in Synopsys’ solutions group, said that with each new solution to the complexity problem there are risks.

“You need more rigid data, but your also have to be more careful because the impact you have with your decisions early on is much bigger,” said Schirrmeister. “That makes it riskier. If you make a wrong decision and go down the wrong path, it’s much harder to reverse that.”

At least part of that has to do with the goals of a chip developer, which is yet another facet of what’s changed in the “What if” approach.

“You have to be very precise about the orders of importance of the properties you’re looking at,” Schirrmeister said. “Let’s assume you’re interested in power, time to market and cost. If you’re not clear about what’s most important, then you’re potentially making unwise decisions. If it’s time to market, people will always go toward a solution with more cores and more flexibility. You put more flexibility into the software. If cost is your biggest concern, you may have to put some effort into accelerators to get everything into a smaller footprint, but you may have to sacrifice on time to market. If power is your most important element, you will probably go away from too many flexible processors and do more things in a dedicated fashion. That means you have to create more.”

By Ed Sperling

As the semiconductor industry digs out from one of the worst downturns in decades, the business of semiconductor design and engineering is changing. While the architecture and features are still being developed by chip companies, the actual work of developing the chip increasingly is being done by third parties.

Outsourcing is hardly new concept in business. In the early part of the 20th century, most automobile makers recognized that it was far more efficient to design a car than produce the parts needed to run it. Outsourcing the design itself, however, has never proven successful because otherwise there would be no differentiation from one manufacturer to the next.

Even within this outsourcing there is specialization and stratification.

IDMs as foundries

Over the past decade, almost all the major integrated device manufacturers have offered foundry services to customers to help offset these costs, usually within the bounds of very restrictive designs. IBM, AMD, Toshiba and now Intel have all taken this approach, and so far none has been particularly successful. Others, such as Texas Instruments, have handed their manufacturing over to major foundries and given up trying to keep pace with rising costs for digital or advanced mixed signal chips.

The latest player to put a stake in this market is Globalfoundries, the AMD joint venture with Advanced Technology Investment Company (ATIC), the investment arm of the Abu Dhabi government that recently announced its intention to buy Chartered Semiconductor. Globalfoundries’ approach is to become a virtual IDM, creating design kits, IP, processes, and even transistor tuning and metal stacks. It does not do the place and route, however, which some of the other IDM foundries have done in the past.

“What we’re doing differently is providing feedback to customers,” said Subramani Kengeri, vice president of design solutions at Globalfoundries. “The disaggregated supply chain model was broken. We’re able to provide very early access, certification for IP—that’s product grade qualification—and we can emulate an SoC so the building blocks are verified at almost the SoC level. We also have a ‘gate first’ approach, while Intel has a ‘gate last’ approach. That gives us more than two times the gate density, and we offer SOI for super high performance.”

This is no ordinary foundry play, and Intel’s approach is to focus on a menu of possible services ranging from power and memory choices to the number of layers and transistor strategy. (See Figure 1) Paul Otellini, Intel president and CEO, said at the Intel Developer Forum last month that he expects SoCs to surpass processors as the company’s revenue stream over the next decade.

Figure 1: Intel's SoC offering.

IBM, meanwhile, has been offering what it calls end-to-end integration from design to manufacturing to characterization and test, and Toshiba has been providing complete design services for the past several years.

How successful these ventures are is unknown. None of these companies break out their revenues for these operations.

Foundries as design houses

While the IDMs seek to recoup their development costs with design and manufacturing services, pure-play foundries aren’t looking so pure-play anymore, either.

The problem with the pure-play model is that majority of designs are being manufactured at older process nodes, which is not where foundries can generate the highest profit. It’s also not where they gain the money to develop new processors or the experience on those new processes to mature them, thereby simplifying the move to the most advanced nodes and amortizing the whole investment.

This explains why TSMC took a 49% stake in Global Unichip Corp. six years ago (it has since reduced that investment), and why the big names on the GUC board of directors are the same ones on TSMC’s board. In fact, looking at the two boards it’s hard to differentiate the companies.

Rival UMC, meanwhile, struck a design services agreement with Bangalore-based Wipro Technologies for the entire design cycle for ASICs and SoCs.

Until recently, when ATIC made a bid for Chartered, it was Chartered that was claiming it was the last major pure-play foundry because of these outside relationships.

Design houses as advanced chip engineers

The last piece to change in the supply chain is the one that was predicted first—but differently. As designs become more complicated and time-to-market pressures mount for companies, many thought they would outsource some of their older designs to companies that could churn them out relatively cheaply while focusing design work on the bleeding edge of Moore’s Law.

What’s happened, however, is quite different from the predictions. Companies like eSilicon and OpenSilicon are now developing much more complex designs than anyone would have guessed. In fact, eSilicon now views 40nm as mainstream, according to Prasad Subramaniam, the company’s vice president of design technology.

Subramaniam notes that complexity is becoming so great that it’s difficult for many companies to turn out a chip or two every year. Engineers don’t have enough experience with some of the tools and difficult techniques such as multiple power islands and complex verification to work at these nodes.

Open-Silicon has reached the same conclusion after initially pitching its design services for older process nodes.

“The downturn convinced people to outsource,” said Naveed Sherwani, Open-Silicon’s president and CEO. “Three years ago our customers were startups. Now they’re large companies. We’re finding that our real competition now is the internal teams within these companies. The VP of engineering services now sees us as competition. We’re writing RTL for them.”

System-Level Design sat down with Keith Barkley, senior engineer in IBM’s systems and technology group; Steven Schulz, president and CEO of Silicon Integration Initiative (Si2); Yatin Trivedi, director of standards and interoperability programs at Synopsys; Ian Mackintosh, chairman of the OCP International Partnership (OCPIP), and Michael Meredith, vice president of technical marketing at Forte Design Systems. What follows are excerpts of that conversation.

By Ed Sperling

SLD: Problems lead to standards, followed by new problems that require standards. What are the problems that need addressing now?

Schulz: Our next effort will be to create a standard for 3D chip integration. This is an important area as Moore’s Law runs out of economic steam, if not technologically. The need for stacking die, and having standards for through-stack vias, how you handle the electrical modeling of that and the geometrical positioning and synchronizing of them has to be done not only across a multivendor flow for a particular die, but across different companies that are putting together the different die that you’re assembling into a package. Many companies have said they’ve gone as far as they can go without standards. You need the processor and stacked memory. If you’re doing a wireless communication device you’ll need the RF fabric with analog baseband on top of some digital and some memory. Often it’s easier and cheaper to do it with different die.

SLD: Is that because of heat?

Schulz: Both heat and economics. To continue integration in 2D is getting too costly, the line lengths are too long, there are uncertainties of how you do the routing, the design fabric—everything has its own specialty from a manufacturing standpoint. The real estate is a problem.

Meredith: As a general rule of thumb, the need for standards in EDA are always at the top and at the bottom. At the bottom, it’s where new process geometries create new challenges. And at the top, as we try to raise the level of abstraction we’ve got SystemC and ESL standards.

Trivedi: Whether it’s top and bottom or front and back, the IP goes all over the place. How you use it, deploy it, verify it and integrate it may be in the middle of the design process. I think of it more as exigencies, not top or bottom

Mackintosh: I think the hotspot right now in all of this is the economy. The result is that more people are open to standards and need to share costs. They’re far more open to collaborating and getting to market faster because there are fewer opportunities these days. Standards allow you to commoditize expert knowledge.

Barkley: Even internally at IBM we’ve been trying to share IP among the P series and Z series. We had to enforce internal standards just to be able to share things among our own groups. In terms of sharing costs, IBM years ago had its own internal models, GL1, NBRs, which really gave us a competitive advantage. What we found is that we couldn’t afford to do everything ourselves. We started working on OpenAccess in 2003. We’ve gone from GL1 to Oasis. We’ve gone from internal data models like VIM and CDBA to OpenAccess. We’ve moved away from our internal models and rules to industry standards, which allows us to use some of the vendor simulation and analysis tools we had to develop internally. That actually prevented us from using some of the vendor-provided software, which we had access to for years.

SLD: IBM has always trumpeted its proprietary tools as a competitive advantage. Has it gotten too expensive to continue with that?

Barkley: Yes, and that’s no longer the case. At the end of the day we have to make designers productive. There are some conflicting opinions inside of IBM, but from a high level our design executives never considered this stuff proprietary. Over the last five years we’ve been collaborating with Cadence on the advanced routing and chip optimization. We shared technology, design rules and software IP. There’s not a whole lot we consider proprietary now except product road maps. We are not an EDA organization.

Trivedi: From a user perspective, you can see why sharing makes sense. They are creating a subsystem that needs to prototype outside, so they need to have certain standards and well-defined processes, or they need to import things because they can’t do everything themselves. It’s a matter of what the rationale is for you to share. At one time IBM, HP, Intel and TI did everything themselves. Everyone was an IDM (integrated device manufacturer). There was no need to share. The only thing you knew was how many pins it had and there was a data sheet. That was the interface. Now you’re working at a much more granular level. I can only produce libraries, for example, that everyone else uses. Or I produce this IP block and everyone else uses it. Or I develop the software and I need to know your register definition.

Meredith: The financial model is the same, whether you’re collaborating or sharing. People don’t have the money to do everything themselves. They need to be able to collaborate with specialists in some areas. What that requires is the creation of an ecosystem of specialists working together.

Trivedi: The question is really how much control you want to exert and how much you can exert. The more control you can exert, the less need for standards.

Schulz: That also means you’re self-sufficient, from A to Z.

Meredith: But if there are five gorillas in the industry, that means each job is being done five times and their customers are paying for it to be done five times. It’s an inefficient approach to delivering value.

SLD: Let’s roll this back a little bit. When did big companies like IBM and TI stop developing their own tools and begin using off-the-shelf tools? And why?

Schulz: It’s a function of the maturing of the industry. Back in the 1970s at TI we grew our own crystals. As the industry matures, you specialize. And a bad economy forces those issues. In the past, we weren’t at the level of complexity involved now in moving from concept to packaged device. In the past, the IDMs owned their own fabs. Many of them are fab-lite these days. The business is much more fragmented. We have more integration, more features, and more levels of abstraction.

Mackintosh: The issue is integration. Because of that, there’s much more compartmentalization across the chain. The result is that people can only afford to play in certain areas.

SLD: And they need to extract value from those areas.

Mackintosh: Yes. They need to decide which areas to play in and eventually they have to learn to share.

By Pallab Chatterjee

The Continua Health Alliance has approved two wireless formats for their next generation standard for personal and clinic medical devices.  The two formats are Bluetooth Low Power, when the specification and protocol is finalized and all the currently available ZigBee protocols.

PAN is aimed at device-to-device communication for body-worn devices, while ZigBee includes low-power LAN applications for device-to-device and device-to-station communication.

Freescale was a key participant in the creation of the demo for qualification and adoption of the ZigBee (IEEE 802.15.4 format) supporting the ISO/IEEE 11073 for point-of-care medical device communication standard. The solution that was presented at the Barcelona meeting was based on not only the technology merits of the communication method, but also availability of parts and sub-systems, component and IP providers, software providers, and products that are incorporating the technology.

Freescale makes sensors, low-power embedded processors and battery-saving power-management technologies that are used extensively in pulse-oximeters, glucose meters, insulin pumps, infusion pumps, blood pressure monitors and personal monitoring products such as activity monitors, gait sensors and wearable panic alarms. Several end product providers, both smaller start-ups and large established medical device providers such as Philips, presented to support the ZigBee adoption.

The ZigBee solution is based on a mesh network format that includes both device/patient identification as unique network elements, but also data-transfer protocols. The use of the mesh network format provides for high reliability multi-path data communication to base options for home, fitness center, retirement communities, nursing homes and a variety of medical care facilities where direct line of sight is often interrupted by temporary obstructions such as people, fixtures and movable metal objects (chairs, lights, poles, etc). The use of the mesh network environment, in addition to the data collection capability, allows for location and proximity identification, which are key aspects of patient monitoring and management for ageing and chronic disease care. In order to address privacy and HIPA compliance, the ZigBee protocols support multiple types of data security including 128 bit AES encryption.

The adoption of the ZigBee protocol by Continua Health Alliance and their device certification means that devices using the wireless solutions from Freescale, Philips, Texas Instruments and others will be able to interact on the network without conflict or interference.

The ZigBee Device Object (ZDO) is a predefined class of functionality so the product developer can focus on writing on the application code rather than low-level details. The Health Care targeting has created a custom Application Support Sub-layer (APS). The ZDO is responsible for starting the APS, and the Network layer and the Security Service Provider in the communication channel. The figure, highlights in Blue, the ZigBee Health Care definitions based on the Zigbee specification. This figure is from the ZigBee Alliance Web site in the white paper on application for Health and Wellness.  Compliance with the IEE 11073-20601 protocol provides methods for: (1) establishing logical connections betwen devices, (ii) presenting capabilities of the devices, and (iii) servicing the communications needs.

The selection of the Bluetooth Low Power protocol and ZigBee protocols, means that Z-Wave, WiFi (802.11), LTE and other wireless protocols are not targeted and certifiable solutions for this application space.

By Ed Sperling

San Jose, Calif.—The rising cost of developing chips and the inadequacy of many existing design tools is adding new impetus to electronic system-level design.

This follows typical adoption cycles in electronics, where marketing hype typically builds, followed by a slew of startups and market doubters and seemingly nothing beyond that. That’s followed by widespread adoption that seems to come out of nowhere. The problem is that at 45nm and beyond, complexity is so enormous and costs are getting so high that many systems engineers have little choice but to look for new approaches if they want to get projects finished on time and budget.

Simon Bloch, vice president and general manager of ESL/HDL Design and Synthesis at Mentor Graphics, broke the growing list of challenges into four areas during a keynote speech at ISQED this week. First of all, he said that chips that cost $39 million to design at 65nm will cost $57 million at 45nm, $82 million at 32nm and $120 million at 22nm.

“The main contributor to that is engineering costs,” Bloch said. “We are seeing an increase in complexity and a flattening in the productivity of traditional design flows.” He said that at 32nm, hardware-dependent software will cost $20 million, architectural design will add another $20 million and chip implementation yet another $20 million.

The second problem is shorter product lifecycles. The old cycle was three to five years, and was shaped more like a bell curve. The current one is one to two years, with a very sharp upswing and drop-off, and fluctations in between.

Third is power, performance and area. Bloch said optimization with ESL provides a 50% to 100% improvement over other approaches. “The next generation of IC technology will be dominated by dynamic power,” he said. “That will cause circuits to exceed 1 watt, which is what most mobile applications demand.”

Finally, complexity is overloading RTL tools. “Systems are becoming too complex for RTL abstraction when you look at the functions and how they relate to transactions, bus utilization, power consumption and software,” Bloch said.

Companies have taken several different tacks to resolve this. The first solution was to shift engineering resources to software and lower-cost locations, but that has mostly been done. Incremental gains in this area will be minimal. Bloch said a second solution is to utilize older process nodes and mature design flows, which is a strategy taken by companies such as Sigma Designs, Trident Microsystems and Atheros.

The third approach is to use ESL to boost productivity, which is what companies such as STMicro, Texas Instruments and Qualcomm have done. That will provide the gains in productivity and, ultimately, cost containment that will be necessary for the industry to progress, he said.

By Ed Sperling

The network on a chip (NoC) approach is gaining ground as an essential part of a system on a chip (SoC), providing the same kind of time-to-market advantage that well-tested intellectual property blocks provide.

This follows almost eight years of hype about NoCs potential with little to show for it. Times have changed and there appear to be two main drivers, one technological and the other business-related. From a technology standpoint, the real key is that chip designs are becoming far too complex to create all the interconnects necessary to get an SoC out the door on time and on budget. From a business perspective, the downturn has cut into staffing of design teams so severely that most companies don’t have the manpower left to develop complex interconnects on a chip that also has multiple cores, multiple power islands, as well as shared busses and memory.

“The key trend that makes such technologies more important is simply the increasing levels of integration, which significantly increase the amount and complexity of the on-chip communication—particularly in the sharing of key resources such as external DRAM,” said Jim Hogan, a venture capitalist familiar with this market. “This complexity permeates every part of the SoC design, from the increasing fraction of circuit delay due to wiring at deeper process nodes up through the massively deeper pipelining required to keep modern DRAMs operating at high efficiency, to the QoS scheduling required to ensure that general purpose software on CPUs can co-exist with real-time communications and multimedia traffic. NoCs provide a structured framework for managing these growing complexities and will therefore become the dominant approach for complex SoCs.”

But structured does not mean standardized. Far from it, in fact. While NoCs fit into standardized EDA flows and work with standards, they are one of the key components that must radically change from design to design.

“At 45nm, and with some designs at 65nm, companies have started to see issues with interconnects” said Charlie Janac, CEO of Arteris. “Projects cost more, they last longer, or they’re being canceled. There’s more problem solving, and the interconnect is more important. When we had single-core chips, it was a choice between a mainframe versus distributed network computing. Now we’re dealing with four to six cores, algorithmic engines, graphics, peripherals and on-chip/off-chip memory. All of this requires more communication on a chip.”

Defining NoC

So what exactly is a NoC? Definitions vary, and likely will evolve as NoCs become both more necessary and more widely deployed. And some of the standard definitions are fuzzy at best. Wikipedia, for example, defines a NoC as “an emerging paradigm for communications within large VLSI systems implemented on a single silicon chip.”

Most chip architects view NoCs as more of an evolutionary step than a radically new concept, though, with the difference being that a NoC is now a discrete part of the development process instead of including it as a piece of something else.

“I like to use the phrase ‘network on chip’ to describe what we do and have been doing for a few years,” said James Aldis, SoC architect at Texas Instruments. “My definition is based around the idea of the NoC being a separate component in the top-level assembly, with a point-to-point interface to each other top-level component. This is distinct from a traditional ‘bus’ where the bus is the top-level assembly. The alternative view is that a NoC is really something with a network-style architecture, where you send out bus requests and responses on the same wires. This alternative view means that the external interfaces of the NoC are not traditional ‘bus-style’ but rather ‘network-style.’ Transactions are captured in packets rather than being represented by separate address, data and command busses. This alternative view is not yet real in the IP industry. You can’t buy IP with this sort of interface on its boundary. It may be used internally in some companies.”

The NoC is particularly attractive at advanced process nodes because of the increasingly complexity and the ability to isolate some of that complexity in the network.

“With the advent of SOCs, a lot of complexity has moved into the interconnect. No one building such chips is really using the old “bus” paradigm anymore,” said Geert Rosseel, senior director at Pixelworks. “The interconnect now has to manage communication between IP blocks having very heterogeneous bandwidth and latency requirements and possibly living on different clock and power domains. The interconnect is now managing CPU-type requests with networking and real-time media (video and audio) traffic, usually all directed to shared resources such as memory. In my opinion, everyone building an SOC is already implementing some kind of complex on-chip communication system.”

But the NoC takes that one step further.

“What sets the concept of a NoC apart is the idea of developing an architecturally clean and unified approach to solving this problem,” Rosseel said. “You put all communication complexity in the network with the IP conforming to some simple interface standard. Once you have this ‘clean’ separation, you can develop an interconnect based on internal protocols that are optimized to meet the performance, area and power requirements.”

Looking forward and backward

The final caveat for most NoCs is that they have to embrace both new and existing technology. That includes a number of existing on-chip protocols, the Open Core Protocol (OCP), ARM’s Advanced extensible Interface (AXI) and AMBA High-Performance Bus (AHB), as well as an alphabet soup of proprietary and lesser-known acronyms.

Ian Mackintosh, chairman of OCP-IP, said the real key is to maintain openness, while embracing existing standards. “The world is heterogeneous,” Mackintosh said. “People have worked up from single bus generators to intelligent networks on chips where you need predictive performance of the NoC.”

OCP-IP has been working on a way to standardize NoC benchmarking to help sort through years of attempts to get this right. For further reading on this subject, check out the white paper entitled: “An Iniative Towards Open Network-on-Chip Benchmarks.”