By David Lammers
Through-silicon vias (TSVs) are in various stages of late development, but design and manufacturing challenges remain before companies can gain the full benefits of the third dimension.

Two camps are pushing hard to introduce TSVs—the design community and the manufacturing equipment companies. The initial goal is to connect graphics memories to graphics processors in mobile systems. Integrated device manufacturers (IDMs) such as Samsung Electronics are racing to use TSVs to couple high-bandwidth DRAMs with processors. Samsung counts Apple as a major customer. Qualcomm and foundry partner TSMC are creating their own design and manufacturing ecosystem for TSV-enhanced mobile IC solutions.

Sesh Ramaswami, senior director of strategy for the TSV program at Applied Materials said Applied has had about 50 people working on TSV-related technologies since 2008, and now has a complete toolset ready. “We are extending all of the knowledge gained from Damascene processing (for copper chip interconnects) to TSVs,” he said.

The equipment and materials companies have gained valuable learning from the early adoption of TSVs in CMOS image sensors, said Didier Louis, a project leader at the Leti R&D consortium in Grenoble, France. Leti worked closely with STMicroelectronics and Nokia to develop a TSV process flow, used to create image sensors in which the TSVs connect the CMOS image sensor and memory. Leti is not yet working on a logic-to-memory TSV solution, but Louis said, “We have in our toolbox all the knowledge. To manage a logic-memory TSV integration it helps if the dice are the same size, and if the manufacturer knows where to drill the vias.”

Fig. 1: Signal and ground TSV architectures may be needed for video applications. (Source: Robert Geer, CSNSE)

Getting the bandwidth increases promised by TSVs will require careful interconnect design optimization, said Robert Geer, a professor at the College of Nanoscale Science and Engineering in Albany, N.Y.. “Every time a designer uses a TSV, you are losing device area,” Geer said, noting that about 10% of the typical die area is consumed by the vertical interconnects. While performance gains are there to be had, Geer reminded an audience at Semicon West that “as nice as TSVs are, they are still copper, which has a frequency limit of about 1GHz” for a 5µm-diameter TSV. For memory access, bandwidth of 2 terabits per second (Tb/s) is sufficient, but logic-to-logic computation requires 5 to 6 Tb/s, and RF signals need much more bandwidth, 50 to 100 Tb/s.

Fig. 2: Video and RF will require up to 100 Tb/s of bandwidth. (Source: Robert Geer, CNSE)

Power is a critical issue. “You want the signals to go through (from logic to memory) at a femtoJoule rate,” Geer said.

For power-conscious mobile systems, TSVs are the only realistic way to connect a graphics/video processor to several layers of graphics memory, where 12.8 GB/s of bandwidth is needed between the processor and DRAM memory for high-definition video. A conventional (non-TSV) HD video solution would require high-frequency operation over 2,000 I/O pins, a non-starter for any battery-operated system, said Pol Marchal, director of IMEC’s TSV development effort.

Geer and CNSE colleague Wei Wang have studied the interconnect architectures needed for “many-core” SoCs with the processor blocks running at relatively low frequencies. Network-on-chip (NoC) architectures for these TSV-enhanced many-core solutions will be required. For video processing and other high-bandwidth requirements, Geer said a coaxial interconnect design, with each signal TSV surrounded by four ground/buffer TSVs, may be required.

While the design community develops the expertise and EDA tools required for TSV-enhanced interconnect architectures, the equipment and materials vendors are ironing out their own challenges. Fusen Chen, executive vice president at Novellus Systems, said TSVs of 5 to 6µm are difficult to fill without voids. Because of the CTE mismatch between copper and silicon, “the copper wants to pump out” from the via, Chen said, adding that for Novellus “the key is our ability to pre-wet in a unique way.”

Keeping the cost of electroplating down, particularly for high-aspect ratio (20:1) vias, is another challenge, Chen said. Novellus introduced its Sabre 3D electroplating system, optimized for TSVs, redistribution layers (RDLs), and other wafer-level packaging applications at Semicon West this month. That sets the stage for an intense electroplating competition between Novellus and Applied Materials, which last year bought electoplating vendor Semitool Inc. (Kalispell, Mont.).

Also at Semicon West, Applied introduced the Avila CVD system for the vias-last TSV process flow, where temperature control is critical. In the vias-last flow, TSVs are formed from the backside after the wafer is thinned. In the vias-middle approach, the TSVs are created in the wafer fab after formation of the contacts.

By David Lammers
Pol Marchal recalls putting a stacked 3D prototype on his desk at IMEC in Leuven, Belgium, last year, which a visitor picked up and examined two months later. “I don’t think this chip will work,” the visitor said, causing Marchal, principal scientist at IMEC’s 3D system integration program, to put the stacked die under a microscope. Sure enough, Pol found that mechanical stress had relaxed over time and the top die had delaminated.

3D researchers around the world are paying much closer attention to thermal and mechanical stress, particularly as ever-thinner die are stacked and connected. At last week’s 2010 Symposium on VLSI Technology in Honolulu, IMEC researchers described the mismatch in the coefficient of thermal expansion between copper through-silicon vias (TSVs) and the surrounding silicon. Using a 45nm digital analog converter test chip, the IMEC team measured transistor drive currents with TSVs located at various distances from the active circuits. Tensile stress near the TSVs was in the range of mega Pascals (MPa), declining to zero stress at a distance of about 10 microns from the TSV edge – a distressingly long distance for today’s leading-edge devices.

That kind of fundamental information (IMEC will deliver a more-complete paper at IEDM in December), Marchal said, is allowing EDA vendors and chip manufacturers to begin creating stress models. “Thermal and mechanical stresses induced by TSVs is a big worry for the community, but I believe there are different ways to mitigate them. A lot depends on what type of devices you use. Stress is not uniform for different types of devices; for example, long channel devices see more impact.”

At its Leuven facility, IMEC is fabricating a series of test chips, named after volcanos, which have sensors positioned at various places on the die to measure thermo-mechanical stress. “We position the smart sensors at the most critical places inside the stack, with the DRAM on top, to study the thermal and mechanical impacts. Then we provide the information to our supply chain partners, including the DRAM makers and packaging houses. Our partners, such as Qualcomm and STMicro, want to gain a head start. When they start RTL-level design they want to know what is feasible and what is not.”

Fig. 1: IMEC is working with several EDA partners to create a pathfinding flow for 3D prototype creation. (Source: IMEC)

While the EDA community is making progress, Marchal worries about is the relative absence of the packaging design community. Co-design of the die and package is particularly important as top die are thinned to 50 microns or less, positioned on top of a much thicker die.

“The die are becoming as thin as aluminum foil, and if you have the wrong glue, or different heat cycles, the die do not remain flat. That builds up stress across the die. The EDA and packaging communities need to be more active in how to analyze this,” Marchal said.

These challenges will be solved, particularly as increasingly large investments are being made in 3D TSV technology. At the DAC conference last week, Myung-Soo Jang, a design infrastructure manager at Samsung Electronics, described Samsung’s plan to use TSVs to link a mobile logic device with a 400 MHz DDR3 memory. “Because we are the world’s largest memory maker, which also has systems expertise from our cell phone business, we believe we have an advantage in this area,” Jang said.

Memory manufacturers such as Samsung and Toshiba, bring certain advantages, but fabless and foundry vendors are forming their own alliances, including EDA vendors and packaging houses. At DAC, L.C. Lu, director of the design methodology division at TSMC, called 3D TSV “the next killer application” and outlined a 3D design flow that TSMC is developing.

The mobile systems vendors need TSV interconnects to support the bandwidth needed for new data services, which include point-to-point video, a market set to accelerate over the next five years. High-definition video encoding requires about 12.8 GB/s of bandwidth between the processor and DRAM memory. The only way to do that in a mobile system is with TSV-connected logic-memory solution, using three or four tiers of die thinned to 30 to 40 microns. To achieve the same bandwidth, conventional DRAMs would require the power-hungry GDR5 DRAM standard, some 2,000 I/O pins, and a frequency that would kill any cell phone battery quickly.

Sitaram Arkalgud, director of Sematech’s 3D interconnect initiative in Albany, N.Y., said Sematech is focused now on a copper-copper bonding, vias-middle manufacturing flow that will come into use in several years. To tackle the stress challenge better standards are needed for how to measure and report thermal and mechanical stress levels. At next month’s Semicon West in San Francisco, Sematech and Germany’s Fraunhofer IZFP research center will hold a workshop on 3D stress management, including DFM-like approaches for managing stress, material properties, and measurement techniques.

Arkalgud said Sematech and SEMI are working on a data exchange format for TSV applications, and will hold a meeting on the subject at Semicon West and again at Semicon Europa in the fall.
“Especially as we go to thinner die the TCE and stress issues will be something we need to watch. To do that, we have to agree on how to measure it, so a data exchange specification needs to be there,” Arkalgud said.

System-Level Design sat down to discuss where the value has shifted in the supply chain with Tom Quan, director at TSMC; Kalar Rajendiran, senior director of marketing at eSilicon; John Koeter, vice president of marketing in Synopsys’ solutions group, and Phil Yastrow, product marketing manager at Avago. What follows are excerpts of that conversation.

SLD: Do you get more value as a customer than before?
Rajendiran: The rule of thumb used to be that you got 15x your investment that was good. If you invested $30 million and you were going after a $450 million market that was good enough. The problem is that it’s no longer $30 million to do a 40nm chip, it’s more like $80 million. And on the other side the markets are no longer generalized. It’s no longer a $450 million market. It’s probably a $200 million market. So in the past you might have been satisfied with 30% market share. Now you need 80% market share. Moore’s Law is great, but the reality has changed the problem from a technology issue to a business issue. The ROI has to be higher. You can’t change the end market.

SLD: What differentiates one chip from another in the future? Is it software or hardware?
Rajendiran: It’s both. If you ask a software engineer and a hardware engineer they’ll have their own take on which one is more complicated, which is harder to test and which is harder to break. But the real smart companies figure out a way to not just build a chip, but also the firmware and the software stack. If software is completely new, there’s a higher probability it will have bugs in it.
Koeter: At 40nm, if you look at the total cost of a chip, the cost of the software will just exceed the cost of the hardware.

SLD: Is that the whole stack?
Koeter: It’s what a semiconductor company would develop. It used to be low-level drivers. Now it’s highly integrated, sophisticated software. But 40nm is the crossover point. So if you look at semiconductor companies, increasingly they’re creating value through software engineers and also their architects. They absolutely want to move up. Unfortunately, every semiconductor company I talk with says that while they put 50% of their costs into developing software, they don’t get any return on that. They don’t get to charge for the software.

SLD: Does that mean Synopsys going to buy an RTOS company?
Koeter: We have a very strong push in this area. Recently we announced an M-language synthesis tool (Synphony). We’ve also been in virtual platforms for three or four years. Systems historically has been a very fractured space, but that’s getting to be a strong opportunity for EDA companies.

SLD: Is the value in the pieces or the integration?
Yastrow: Both. You have to have good IP and you have to have a way to integrate it. You have to have a way to make it work in a customer application. This comes back to channel modeling and how the package fits in. But it’s interesting when we start talking about software vs. hardware. It’s easy to argue that everything is software. People are writing RTL, getting the code to work, making sure they’ve covered all the corner cases and verifying it all. We’re seeing with Moore’s Law that verification is becoming a huge, huge chunk of the work.
Koeter: It’s 70% for the hardware, and then it depends on how you validate the software.
Yastrow: So not only do you need the great IP—memory, logic and I/Os—but you need someone to take that and integrate it first in the form of RTL, and then for the physical designers to make sure it meets timing and it meets power budgets.

SLD: At 32nm and 28nm we’re starting to see restrictive design rules. How does that affect all of this?
Quan: That’s for better yield in the long run.

SLD: But TSMC also is rating IP, right?
Quan: At 40nm we started asking customers and IP providers to run full DFM checks on IP blocks or the full design. It used to be recommended but not mandatory. One of the reasons for this is we’ve seen a lot of layout patterns that might not be reproduced perfectly in silicon. That will affect yield. At 28nm it gets even more difficult in terms of lithography, CMP and DFM. If we give the designer less freedom then it’s easier to validate and check and have better yield. You used to be able to put a lot of bends and jogs into a polygon. Now you try to have more regular structures with no bandwidth jogs. That will facilitate double patterning at future nodes, too.
Rajendiran: Customers don’t like restrictions of any kind. People are talking about orthogonal routing, which gives more flexibility. And companies are developing libraries so that when lithography progresses everything works fine at future geometries. If that can be achieved, every designer will be happy.
Quan: We build our own libraries and we collaborate with IP providers on theirs. Once you get the signal out to the pin and you do place and route, you also know which direction it should go. But it does require a joint effort from the IP provider, the company building the library, and the tool provider to make sure the whole design flow can use these new cells.
Koeter: It certainly makes life harder for an IP vendor. Now we have to worry about multiple layouts of the same IP block. You’re going to see more consolidation in the physical IP space.
Yastrow: We will find a way to deal with it. Competitively, everyone is dealt the same cards. But that’s not the only challenge. Voltage levels are also a problem. You’re trying to comply with standards back to the system level and getting the customer channel to work. You get a performance hit from a higher voltage level, and then the standards run at 1 volt instead of 0.85.
Koeter: USB has to have backward compatibility to 5 volts. Try doing 5-volt tolerance in a 1.8 volt I/O device.

SLD: Does a 3D stacked-die approach change where the value is—providing it works?
Quan: It’s a way to put more stuff in the same area. People have been going down the path of shrinking the die and getting more performance. But there’s always some technology that cannot scale down that easily, like analog and RF. In memory if you have 1 megabit and you want 4 megabits you build them horizontally or you stack them. That’s already been done. From an SoC perspective, where you’re mixing different blocks—memory, analog, RF, digital baseband—it’s a different approach to how you build them. But there will certainly be challenges. Through-silicon vias present more challenges in terms of validating the timing through these vias. And when you stack up things, the thermal profile will be different.
Yastrow: There are two things we know for sure. One thing is customers need more memory. The other thing we known is it’s becoming more difficult to combine an eDRAM process with a logic process and to be able to have them both optimized. Now you end up with tradeoffs. You optimize for the embedded memory or the logic. That’s why 3D where you have a memory chip and an ASIC that are tightly coupled is very real.
Koeter: One of our concerns as an IP vendor is whether 3D ICs will change the fundamental way chips are partitioned. Will all the analog be put in a 130nm or 180nm and the digital be put in a 32nm or 22nm chip. We’re looking at it all the time and talk to customers about it, but right now there’s no indication that’s a significant trend. People continue to integrate analog and digital with big ‘D’ little ‘a’ chips. What they’re doing in 3D is stacking memory on top of those chips.
Yastrow: Besides stacking we’re also seeing new standards developing beyond DDR3. You will still have a discrete chip. But I don’t think you’ll see as much embedded memory on chips. Maybe there will be some SRAM and DRAM, but it’s getting harder and harder to make those two match. So maybe you’ll have two side by side, instead of on top of each other, with an extremely high-speed link between them. That’s why some of these standards that are being developed, like GDDR5 (graphics double data rate, version 5).
Quan: There has been talk about a silicon interposer where instead of stacking them you connect them through a silicon substrate.
Rajendiran: That’s already happening. 3D is taking it to the next level. Will it happen? I think it will. The question is how soon. I don’t think it will happen in the next two or three years because it is easier said than done. It’s a bigger floor plan issue.

SLD: Does the highest value go to people solving the hardest problem, such as power modeling?
Yastrow: It’s a table stake. You have to reduce the power. You won’t necessarily get more money but you won’t lose the design.
Koeter: I absolutely agree. At least you won’t lose money.
Quan: The system-level spec is only getting harder and harder. Even though you leverage the latest process, so you can reduce power and leakage, you still have to have a lot of design techniques. If you have better power consumption, you have more chance of winning the design.

By Cheryl Ajluni

At the 46th Design Automation Conference in San Francisco last month, attention turned to a discussion of how to extend the momentum of Moore’s Law into the next decade. One plausible solution, according to Philippe Magarshack, the general manager of Central CAD & Design Solutions at STMicroelectronics, is 3D stacking for complex System-on-Chips (SoCs).

The concept of 3D stacking or integration technology is not new. In fact, 3D stacking of dies has been successfully demonstrated and is currently being commercially employed in some embedded domains (e.g., stacking DRAM memory on CPU cores). A recent 3D IC report from Yole Développement suggests that by 2012, the number of 3D IC-processed wafers could surpass 10 million units, driven in part by handset, wireless and computing applications. Given the intense interest and work going into developing 3D integration technology, this prediction seems just about right—assuming, of course, that a few challenges can first be met.

Exploring the third dimension

Very simply put, 3D integration consists of stacking integrated circuits and connecting them vertically so that they behave as a single device. A 3D chip is therefore just a stack of multiple device layers with direct vertical interconnects tunneling through them. So what’s the big deal about 3D integration?

Today’s semiconductor chips face extreme pressure to achieve increased performance, while reducing their size and accommodating lots of new functionality. When these factors coalesce in traditional 2D chips, longer interconnects result. In SoCs, longer interconnects translate into reduced speed and increased power consumption.

A key benefit of 3D integration is that it can reduce the length of interconnects. Additionally, it provides higher transistor density, faster interconnects and heterogeneous technology integration, with potentially lower power, cost and faster time-to-market. As Matt Nowak, director of engineering in the VLSI technology group of Qualcomm’s CDMA technology division, pointed out in a DAC 2008 presentation, the 3D approach “achieves extremely high densities, allowing us to use heterogeneous technologies and reduce form factor. The key is that it enables the use of new differentiating technologies to build new architectures that cannot be built in existing technologies.”

Eyeing recent developments

Up to this point, most efforts in 3D integration have focused on developing different fabrication techniques for stacking multiple device layers and forming the vertical interconnects. Much of the work has been done through collaborations with academia, industry organizations and government-sponsored laboratories around the world. One of the key technologies to come out of this research is a next-generation interconnect technology known as Through-Silicon Via (TSV). The TSV is a vertical electrical connection that passes completely through a silicon wafer or die to produce multilevel chips with an optimum combination of cost, functionality, performance, and power consumption. By using TSV technology, 3D ICs can pack greater functionality into a smaller footprint and realize shorter critical electrical paths, resulting in faster operation.

Some of the other developments to come out of ongoing 3D integration research were recently recognized at the Electronic Components and Technology Conference. Sandia National Laboratories presented details of its W TSV process, which is said to provide a suitably low-resistance metal with a coefficient of thermal expansion close to Si, a via fill that is conformal, and can be readily integrated into IC fabrication. IMEC introduced a novel process for die-to-wafer bonding (using Cu-Cu bonds) of its 3D SIC technology and a scalable TSV technology for 3D wafer-level packaging. Its TSV technology is designed for 3D structures where interconnects are fabricated after standard CMOS processing.

SEMATECH also is focusing its 3D research on TSV technology, particularly for implementation. The industry organization is actively working to bring together partners from across industry—chipmakers, equipment and materials suppliers, assembly and packaging service companies—to make 3D TSV suitable for high-volume manufacturing (Figure 1).

Figure 1. In contrast to the 2D-SoC or 3D System-in-Package, 3D TSVs offer a cost-effective way to achieve high density and performance, while also being able to integrate non-CMOS products with CMOS. The SEMATECH 3D project is based on cost modeling to assure products will be both manufacturable and affordable.

Help: tool support needed!

While ongoing research and development is absolutely critical to the success of 3D integration, perhaps one of the greatest challenges it faces is tool support in terms of design techniques and methodologies. Without it, engineers have virtually no efficient way to exploit the technology’s benefits. Tool support is especially critical when it comes to 3D integration because vertical stacking tends to increase thermal resistances, further exacerbating temperature-induced problems that can negatively affect system reliability, performance and leakage power. The use of 3D also will significantly complicate the typical design flow.

The key, of course, lies in creating a standardized design environment and methodology for physical design of 3D chips that could support a range of different tools. Having the tools integrated in one place would make it easier for designers to explore and make architectural decisions and then, to hand those decisions off to next stages in the design process.

3D IC integration is still in its infancy and, as a result, tools developed today for one specific application (e.g., stacked memory) may not be suitable for heterogeneous integration tomorrow. Nevertheless, there are some tools available now, with more in development. Some of these tools include:

3D PathFinding

Javelin Design Automation. 3D PathFinding provides a detailed 3D flow for accurate performance/power/cost estimates that can be used for rapid design exploration and optimization of 3D stacked ICs. Developed in collaboration with IMEC and Qualcomm, the solution extends Javelin’s existing PathFinding methodology and j360 Silicon PathFinder physical design prototype platform to support virtual chip design (Figure 2).

Figure 2. Javelin’s 3D PathFinding solution allows the designer to assess the impact of various 3D interconnect strategies throughout the IC design and fabrication process, in a matter of just a few hours or days. Silicon process engineers can use it to fine-tune their technology to the system architecture specifications.

MAX-3D, R3Integrator, R3CAD, and R3Artist; R3Logic

These tools, developed through work conducted as part of research programs sponsored by the Defense Advanced Research Projects Agency (DARPA), enable 3D IC design and analysis (Figure 3). MAX-3D is a 3D mask layout tool whose technology file includes all properties of stacking process, wafer orientations, bond materials, via electrical/material properties, and also incorporates 2D foundry design kits. R3Integrator is used for die/interposer/package co-design with TSVs. R3CAD is a java-based, multi-platform tool for 3D design research and prototype study and R3Artist is an embedded 3D layout editor (Figure 3).

R3Logic is currently collaborating with STMicroelectronics and CEA-LETI to develop a full 3D design flow for 3D heterogeneous system and system-in-package design.

Figure 3. R3Artist features single and multiple wafer technologies, integrated material properties database and solid model extraction, including dielectric layers.

3DCACTI

3DCACTI estimates the optimum access times and power dissipation of a cache using 3D IC technology for a given number of active device layers and by partitioning device layers for various technology nodes. Based on the estimation, it searches for the optimized configuration that provides the best delay, power and area efficiency trade-off according to the cost function for a given number of different 3D partitions.

3D Magic and PR3D, Massachusetts Institute of Technology

3D Magic is a comprehensive layout methodology for 3D circuit-layout editing and extraction with MAGIC, an open source layout editor developed by UC Berkeley. PR3D is a placement and routing tool for standard cell design in 3D. Both tools were developed through MIT’s Interconnect Focus Center Research Program. MIT also developed SysRel (System-Level IC Reliability) for assessing the interconnect reliability of 3D ICs from a thermal-aware perspective at the circuit-layout level.

Conclusion

With the pressure on traditional 2D chips mounting, 3D integration has begun to establish itself as a viable means of breathing more life into Moore’s Law. It certainly touches on all the hot buttons in the industry today, namely low power, cost and time-to-market. The challenge will be in ensuring that these benefits are realized in a timely and efficient manner. 3D-specific design tools and methodologies are coming to meet this challenge head on. In the meantime, the tools available now and the groundwork for future tools and methodologies being laid by industry organizations, academia and commercial companies alike, will go along way in ensuring 3D integration plays a critical role in the future of the semiconductor industry.