By Ed Sperling
Synopsys issued a barrage of announcements, including new products, new relationships, and a new win. The company unveiled its next-generation verification IP based on its new VIPER architecture, with native support for OVM, UVM and VMM. Synopsys claims up to 4x performance over other commercial VIP. This is an interesting number, and likely will spark a volley of announcements from the other Big Three EDA vendors, all of which have been gearing up for what they see as a big opportunity in the VIP space. Synopsys also rolled out 28nm M-PHY IP that supports six different standards for mobile applications.

On the relationship side, Synopsys struck a deal with Arteris to jointly develop an IP solution based on the Low Latency Interface, which cuts the cost of the bill of materials by eliminating a memory chip and reducing the area of a PCB. In a related move, Arteris introduced its low-latency interface digital controller IP, which it says is already silicon-proven in TI’s OMAP platform.

Synopsys also is working to link Springsoft’s debug technology with its own Protocol Analyzer. It also won a deal with BiTMICRO for a slew of EDA tools.

Samsung teamed up with Mentor Graphics to create a DFM sign-off reference solution for Samsung’s foundry. This opens the door to a couple of other big deals for Mentor, as well, considering Samsung is one of the three main companies in the Common Platform. The others are GlobalFoundries and IBM.

Mentor also announced its Q4 financial results, which set a new record. Revenues for the quarter were $320.4 million, up from $307.3 million in the same period in 2011. For the 12 months ended Jan. 31, revenue was $1.015 billion—also a record—up from $914.8 million in fiscal 2010. Net income for Q4 was $57.8 million, up from $50.6 million in Q4 2011, and for the year it was $83.9 million, compared with $28.6 million the previous year. Mentor expects revenue to increase to about $1.1 billion this year.

Cadence unveiled the production release of a virtual platform for Xilinx’s Zynq-7000, which is based on the ARM Cortex-A9 MPCore. After years of EDA companies trying to gain a strong entry into the FPGA world, this is an interesting doorway.

Docea Power rolled out a new tool for architectural-level power and thermal analysis. Given the fact that the biggest savings in power and heat can be obtained at the earliest stages of a design, this is an important step forward. The next challenge is to implement this kind of capability into existing flows so that power and heat models can be integrated easily with other models. Functionality and performance are no longer enough.

Tensilica introduced its second-generation multimode baseband chip, which includes multiple dataplane processors. The chip was co-developed with NTT DOCOMO, Fujitsu, Panasonic and NEC.  Tensilica also rolled out Dolby Digital Plus for surround sound on its HiFi Audio DSPs, and it struck a deal with ClariPhy, which will license Tensilica’s dataplane processors for optical networking mixed signal processing.

By John Blyler and Ed Sperling
Next to computation, memory is the most important function in any electronic design. Both processor and memory devices must share the limited resources of power and performance. The relative weighting of these tightly coupled constraints varies depending upon the application.

At one extreme of the power-performance spectrum are applications that sacrifice performance to maintain the lowest possible power, e.g., a simple 8-bit microcontroller. For example, STMicroelectronics has recently introduced a 16-kbit EEPROM kit that can harvest enough energy from ambient radio-wave energy to run small, simple and battery-free electronic applications like RFIC tags. The growth of wireless power technology is an emerging field that includes other major players such as Intel and Texas Instruments. (see “Tesla’s Lost Lab Recalls Promise Of Wireless Power”)

Another example of an extremely low power-low performance memory application is in the emerging market of flexible, plastic electronics (see Figure 1). A team from the Korea Advanced Institute of Science and Technology (KAIST) recently reported such a device, i.e., a fully functional, flexible non-volatile resistive random access memory (RRAM).

Fig. 1: An image of flexible memory wrapped on a quartz rod. (Courtesy of KAIST)

The challenge with flexible, organic-based memory materials is that the devices have significant cell-to-cell interference due to limitations of the memory structures within the plastic material. One solution to this problem involves the integration of transistor switches into the memory elements. Unfortunately, transistors built on plastic substrates (organic/oxide transistors) have such poor performance that they were unusable. But the team at KAIST solved the cell-to-cell interference issue by, “integrating a memristor with a high-performance single-crystal silicon transistor on flexible substrates.” Similar breakthroughs have been reported at IMEC, (see, “Organic Processors Offer Microwatt Applications.”)

In addition to low power, memristor technology promised to provide significantly higher memory densities with a smaller footprint than today’s devices. A memristor is a two-terminal non-volatile memory technology that is seen by some as a potential replacement for flash and DRAM devices. Hewlett-Packard, the developer of memristor memory, recently announced a partnership with Hynix to fabricate memristor products by the end of 2013.

One anticipated growth market for memristor technology is in solid-state drives (SSDs), which are replacing traditional hard disk drives (HDDs) in mobile notebook applications. SSDs require less power and space than HDDs, which makes SSDs well suited for the rise of ultra-light and ultra-thin notebook computers. These ultra-“books” aim for at least 8 hours on a single battery charge. Among others, Intel recently heralded it entrance into the ultra-book market during the last Intel Developer Forum (see Figure 2). The company is shifting its focus away from traditional notebooks toward ultra-books to deal with competition from Apple’s MacBook Air and ARM processor-based tablet computers.

Figure 2: Intel’s Ultrabooks are planned to align with the release of low voltage Sandy Bridge, Ivy Bridge, and Haswell processor models.

One consequence of the rise of Ultrabook laptops is the further erosion of the DRAM growth market (see Figure 3). Mike Howard, principal analyst for DRAM and memory at HIS, noted that, “the single biggest reason for DRAM’s reduced growth outlook in notebooks during the next four years is the Ultrabook.” Howard believes that the emphasis on form factor with minimal size and weight in Ultrabook will lead to fewer DRAMs on average than traditional notebooks.

Figure 3: DRAM market faces many challenges. (Source: IHS iSuppli Research, November 2011)

Let’s look at the other extreme of the performance-power spectrum, i.e. high(er) power and high performance. Today, server-grade multicore processors are needed to support both ever-increasing network data bandwidths and increasing data-crunching analytics for context-aware applications. In sync with the need for more processors is the complementary need for more memory. For example, networking applications require the constant movement of massive amounts of data into and out of each processor in a multicore system.

Such high-performance processor applications may soon grind to a halt in what Linley Gwennap describes as, “the looming memory wall.” Others have echoed Gwennap’s concerns that the throughput needs of high performance multicore processors will not be met by today’s memory technology.

What can be done? Several solutions are possible, notes Gwennap:
> Increase L3 cache to help reduce traffic to external memory.
> Add more memory channels to tradition slow speed DRAM devices.
> Follow Intel’s lead on its Xeon processors by adding buffer-on-board (BoB) chips to convert traditional processor serial interfaces into standard parallel DRAM connections.
> Follow MoSys’s lead by implementing a standard high-speed serial interface directly to DRAM.
> Add Micron’s prototype Hybrid Memory Cube to re-engineer the memory subsystem.
(see, “Samsung, Micron Unveil 3D Stacked Memory And Logic.” )

Not everyone agrees with that approach, however. Sam Stewart, chief architect at eSilicon, says that off-chip memory could greatly improve performance over L3 cache and do it much more efficiently. “When you have L3 cache, you have 2 megabytes per CPU that’s shared,” said Stewart. “With a Hybrid Memory Cube you may have 17 die with 8 gigabytes versus a total of 12 megabytes. Plus it’s lower power because it’s closer and there’s high-bit bandwidth.”

Add to that custom memory, which is right sized to the specific function, specialty memories that can run at higher frequency, and the performance numbers go up even further. Put them in a stacked die package and they can go up still further. While stacked die exacerbates some issues, such as heat dissipation and electromigration, it eliminates another problem—the need for termination on signal paths. The close proximity of chips means there is insignificant reflection of electromagnetic waves as they travel through wires at the speed of light. That alone improves performance, said Stewart.

There are other technologies in the works, as well, including phase-change memory, STTRAM (spin-transfer torque RAM), and resistive RAM, according to Philip Wong, professor of electrical engineering at Stanford. He said the goal is to improve energy efficiency in all these types of memory while improving performance.

But with an estimated 50% of processing now tied up with memory and memory controllers, there is plenty of research underway to improve every aspect of memory. Not all of them will roll out in time for the next couple of designs, however, which means engineers will have to push existing boundaries a little bit further until they’re ready.

By Ed Sperling
The growing importance of software and off-the-shelf IP in semiconductor design is beginning to change the dynamics of the entire EDA tools business, setting off a string of acquisitions as the largest players realign themselves to take advantage of this shift.

The most recent example: Mentor Graphics’ acquisition this week of CodeSourcery, a GNU-based Linux toolchain and services company. The public face on the deal is that while no one can make money directly selling open source, there is plenty of money to be made in the tools and support around it.

But there’s more to this acquisition than meets the eye. Over the next couple of years some very significant changes will materialize in the SoC design world. First, more and more fabless companies will be required to develop at least some software with their hardware. Many chip companies don’t necessarily see this as a big opportunity, however. The general consensus is that no one really makes enough money selling software to warrant the investment, so open-source drivers, firmware and libraries will be very much in demand.

Second, as the industry moves to 3D stacked die, beginning in late 2012, it’s highly likely that chips won’t just have one embedded processor on them—they will have multiple processors, possibly from multiple vendors. And all of this will need to be controlled through software, most likely open-source. While it’s cheaper to use open-source software, there’s also a requirement that the tools and support be of the same caliber as commercial tools.

“We’ve seen an explosion in the software stack,” said Nick Lethaby, manager for software partner networks at Texas Instruments. “There is more connectivity and there are more sophisticated tools.”

He said that while some customers still want a slimmer real-time operating system, the bulk of the market is heading to Linux and Android (which is based on a modified Linux kernel). But he noted that customers are wary of software that is not fully supported. “From TI’s perspective, an ecosystem with commercial support is really important.”

Mentor is not alone in seeing this shift. All three of the large EDA players are now heavily invested in software tools. (Even emulators are increasingly a software verification tool, despite the fact that most of them are bought by the hardware engineering groups.)

Cadence’s entire EDA 360 push is focused on getting the EDA industry to shift direction so that application software drives everything below it. Linux and Android are key pieces of that market, and developing the tools to integrate the hardware and the software and commercial, off-the-shelf IP marks a fundamental change in how chips are architected.

What’s interesting is just how quickly this shift is occurring. Pre-downturn, companies developed much of the IP themselves and the device manufacturers developed much of the software. Post-downturn, as much as 90% of all content in a chip is re-usable IP and a greater part of the stack is now in the hands of the chip developer. That helps explain Cadence’s purchase earlier this year of Denali, which makes tools to model IP.

This shift toward commercially available IP poses huge issues, as well. The IP has to be power-aware, it has to work in complex environments for which it may not have been designed, and the various power states and voltages must be managed through software. This is a potential bonanza for EDA companies, which have been dealing with a shrinking number of design starts and relatively flat revenues for at least the last several years.

Synopsys, the third player in this EDA triumvirate, has pushed heavily into the IP itself with the development of standard I/O IP and the purchase of Virage Logic last summer. Synopsys is particularly well suited to take advantage of this shift to commercially available IP, with its expertise in tools and its understanding of proximity and power effects. The company is one of the very few that can provide users with detailed information about how its IP will perform under a variety of conditions, such as voltage or process variations and in noisy conditions.

The company also has invested heavily in software prototyping so that chipmakers can begin developing software earlier in the design cycle, thereby shrinking the time it takes to get a functioning chip out the door.

So what does this mean for EDA tools? If the large bets placed by the Big Three EDA vendors are correct, it will mean significantly greater sales to new customers rather than more tools to a shrinking number of customers. The challenge will be getting customers to pay for the perceived value of those tools, which the software industry—and increasingly the FPGA prototyping industry—have been reluctant to do in the past.

The question now is whether they can educate the software industry about the economics of automated development and change the thinking among the software engineering management. So far, no one knows the answer. But given the complex issues that need to be solved in future designs, as well as the recent spate of acquisitions, at least everyone is in agreement that an opportunity exists to tap a new customer base.

By Ed Sperling
ARM introduced its Corelink 400 System IP to deal with coherency, virtualization, latency and power management in multiprocessing systems. This is important because multiple cores all share the same resources, and it’s far less efficient to do this kind of job with an operating system than scheduling with a cache coherency layer.  The company also uncorked its Mali GPU, which allows the graphics to be embedded onto the same piece of silicon as the CPU. Both of these products were rolled out at ARM Techon3 this week.

Mentor Graphics extended its ReadyStart embedded software platform to TI’s Stellaris ARM Cortex-3 MCUs. ReadyStart includes its Nucleus RTOS, the Inflexion platform user interface, board support tools and a debugger. Mentor has announced similar deals for Atmel and other TI platforms.

Synopsys is one of 12 finalists in Armenia to receive the U.S. Secretary of State’s 2010 award for corporate excellence based upon the role U.S. business play abroad as good corporate citizens. Given the backdrop of Russia-U.S. relations and spy chasing, this couldn’t come at a better time. In addition, Cavium used Synopsys’ NanoTime static timing analysis tools to achieve full-chip timing analysis signoff of its multicore Octeon II Internet application processor.

Mobileye, meanwhile, is using MIPS’ 34K multithreaded core for its collision prevention system. This is really cool technology. Driving is about to get much safer.

By Ann Steffora Mutschler
With the typical cost of software accounting for 40% to 60% of an SoC, semiconductor OEMs are under more pressure than ever to meet margins. As a result, they are drawing on their ecosystem partners to provide a more complete foundation including hardware, software, FPGA prototypes, verification IP and virtual models, as well as an increasing demand for open source software support for their SoCs.

To be sure, software acquired through an open source model can allow faster time to market by leveraging publicly available technology. But the biggest limitation is lack of support, unless the software comes from a commercial provider.

How does this play outside in the hardware world? “Software is something you can change relatively easily, whereas hardware IP, once it’s in silicon you’re stuck with it,” said Simon Davidmann, president and CEO of Imperas and founding director of Open Virtual Platforms (OVP). “Another big difference between hardware and software is that there are very few people designing hardware compared to people writing software. If there are 100,000 apps for an iPhone then there must be 300,000 or 400,000 people trying to write them. In the hardware world, there are only about 100,000 hardware engineers globally, and yet there are many times that just developing software for the iPhone.”

Clearly, then, the software scale is completely different from the hardware scale, and this has an important effect on open-source ideas.

“With the GNU tools they can apply to tens of thousands of people easily, but in the EDA world that’s not really the case,” said Davidmann. “The closer you get to the hardware, the less appropriate an open source community is. Open source is good from a, ‘Let’s have a compiler that you can use for free,’ but no user fiddles with the open source bits of GCC (GNU Compiler Collection) or GDB (GNU Project Debugger) that doesn’t fiddle with Linux. It’s very useful for the hardware guy to make use of, but then they tend to have to pay people to do it.”

Where it works best
One of the biggest challenges companies face in implementing a design is in the verification phase, which is why it consumes the largest chunk of the non-recurring engineering expenses in any design. Prasad Subramaniam, vice president of eSilicon’s design technology, said this is exactly where open source can help.

First, open source software could be of help in the actual verification of the IP that is being stitched together as part of the SoC, especially for IP that is standards-based like a USB interface or a PCI Express interfac. “Because it is in the public domain, you can develop verification IP in an open source manner. That’s one of the advantages. People who do verification today license this kind of IP from various IP providers, and it will be significantly helpful for them if such verification IP is available in the open-source model as it will make it easier to access, allow them to do what-if analysis, experiments and so on before they go on and purchase something that is industrial class,” Subramaniam said.

Second, open source software support can be helpful in system-level verification. “Once you have designed your SoC, you want to try and run system-level testbenches, for example. If you build an ARM-based subsystem, you want to try and emulate it in an FPGA type of environment. You can get a board that contains an ARM chip with an FPGA and you can implement your logic, and this has an interface to your PC and you can control the software from your PC but the actual software will be running on the ARM test board and the FPGA,” Subramaniam said.

Similarly, John Koeter, vice president of marketing for Synopsys’ IP and Systems Division, said the use of virtual prototyping at the system level has allowed a fair share of the top 10 global semiconductor companies to pull the time to ramp into production by as much as six months earlier than with older approaches.

“Today many companies still use what I call a waterfall model where they develop the hardware, they get to the golden RTL or even the chip and then that’s when they’ll start developing the software on the physical prototype itself or maybe on an FPGA-based prototype of the chip,” he said. “That process is done in a serial or waterfall manner, and obviously that pushes out the entire development schedule significantly. We are really working with the semiconductor companies to pull in the start of the software design much earlier using virtual prototyping. In a fast moving market, ramping to silicon six months or even three months your competition easily yields 10% to 15% revenue through additional early wins.”

Models Are Key
The key to virtual prototyping involves the models, and while not disclosing any plans, Koeter noted that Synopsys intends to enable a significant effort within the open source community for creating models. He said plans are in development. Also, with its recent acquisition of Virage Logic, Synopsys gained the ARC cores, and is fully supporting the various software stacks that run on an ARC core, including variants of Linux, etc.

On the surface, it appears that Synopsys may be finding out what Imperas did, namely that people want control over the simulation models. They didn’t want to get into the insides of the simulator. But they do want a commercial company to professionally service and support the tools, and they want control over the IP and the models, Davidmann said. “The great thing about open source is that it allows you to see what’s going on, modify it and use it, and then that way it gives you freedom and can take things further.”

Imperas has a closed-source commercial simulator and open-source models (developed from published documentation and in such a way that the user can extend them). “This is very different from the SystemC approach of an open-source simulator—developed and funded by the big EDA companies, but which isn’t really open because you have to be part of their club and paying to be able to enhance it and redistribute it,” he said. “What this means is that it is about three or four years old. It’s a commercial ploy in that Cadence, Mentor, Synopsys have their own tools and simulators that use SystemC as proprietary professional solutions and the OSCI simulator is the poor cousin so it is several versions of a standard behind.”

Imperas also uses an Apache License, which Davidmann noted is good for commercial organizations and does not have the same requirements as the GNU license.

“For a silicon vendor that makes them very nervous. If [they] download a bit of IP and put it in [their] chip, the rules aren’t very clear yet because open source is all about software, it’s not really about hardware. Hardware tends to be covered by patents and software by copyright. In software if you use a GNU public license, if you link it to any other pieces of software, all of that software has to be covered by it so it really promotes the spirit of ‘free to use.’ You are allowed to access the source, and if you use it you’ve got to make your source available so it furthers the usage of it. Whereas in a commercial organization, there’s no way you would want to include a piece of hardware on your chip if you had to give away your hardware design. You want to protect that and hide it because it’s all your tricks and magic. In the hardware world people are much more nervous about the licensing of open source.” Davidmann said.

A new approach to open source for ARM-based SoCs
There is another approach that ARM, IBM, TI, Samsung, ST-Ericsson and Freescale have come together on to address OEMs that demand the best open source support. “They want the latest kernels, they want the latest tools, they’ve got to be stable. It’s more than just throwing them a BSP and hoping it is good enough. They want more than that, and that’s what Linaro was born to do,” to make it easier for ARM partners to deploy the latest, optimized technology into Linux based products, explained Rob Combs, head of global alliances at Linaro, a not-for-profit open-source software engineering company that launched in June.

Linaro stemmed from conversations with OEMs about the difficulties of developing open source—the need for great tools, the latest kernel, not having to rewrite BSPs from silicon partners, he said. “They want more of that support in the upstream trunk rather than less and they want more investment so we can fix any problems that crop up. That’s more than any one company can deliver individually. There needed to be a collaboration vehicle to deliver this for the ARM partnership. Linaro was born to make it easier and quicker to develop complex open source products based on these new whizzy SoCs that are coming out.”

Linaro does essential engineering relevant to multiple verticals markets and to multiple distributions. At the application framework level, the organization aims to helps distribution creators get a better base to start from, which is enabled on multiple ARM platforms for more commonality, and less fragmentation. In terms of development tools, Linaro believes it can provide better tools to build optimal software, which is are used at all levels of the OS, and which is crucial to achieving the best PPA. All of this is part of the move toward a common kernel and is enabled on multiple silicon platforms, Linaro said.

In the process of ramping from 20 to 80 engineers, the organization will deliver every six months a harvest of all of the latest, freshest code, Combs said. Linaro’s next step is to show proof points at upcoming Linux conferences.

By Ed Sperling
Mentor’s Colin Walls looks at the uses of asymmetric vs. symmetric multiprocessing and where each gets the most traction. Better get used to this stuff. If chip design goes 3D there’s going to be a lot of the asymmetric stuff to contend with.

Synopsys’ Karen Bartleson has a schedule of old media, new media and non-media speakers to be held at Conversation Central at DAC, and posted forever afterward. And just in case you’ve missed that, check out Rick Jamison’s blog. He has a copy of the same schedule attached to his blog.

So whom can you believe? Old media? New media? Non-media? Cadence’s Tom Anderson takes a stab at that question and what makes a professional blogger…well…professional. There’s no clear answer, but a lot of people get quite emotional over this subject. It’s sort of like talking about politics or religion at Thanksgiving dinner. More turkey, anyone?

Daniel Nenni sheds light on TSMC’s new analog/mixed signal flow, version 1.0. You’ve got to start somewhere, but most software companies now start products at version 3.0 so it doesn’t look like it’s the first version. Apparently that logic doesn’t apply in foundry reference flows. Still, this is a big step in the right direction.

Rumors are flying that Synopsys is on the hunt for more acquisitions. You don’t have to go very far to confirm that, of course. Ask any top exec at Synopsys and they’ll gladly offer up that acquisitions are part of the growth strategy. Scratch the surface a little deeper and you find the company has $1.08 billion in cash. Which begs the question, who’s on the short list? John Cooley’s DeepChip offers some ideas.

If you’re looking for a succinct definition of clock-gating retention latches, check out the entry from Synopsys’ Godwin Maben.

What’s behind Lenaro, the open-source consortium of companies that includes ARM, TI, Freescale, ST-Ericsson and IBM? ARM’s Kerry McGuire takes a look under the covers.

Mentor’s Ping Yeung is bucking the trend on static verification. He’s a fan.

Finally, Si2’s Steve Schulz reveals what the group is doing at DAC next week. It’s a serious effort to add standardization into semiconductor engineering, but the location may cast a different tone on the overall proceedings. Anaheim is the only city that can give a different meaning to “Mickey Mouse design.”

By Ed Sperling

System-Level Design sat down with Antun Domic, senior vice president and general manager of Synopsys’ Implementation Group; Serge Leef, vice president of new ventures and general manager of the System-Level Engineering Division at Mentor Graphics; John Busco, CAD manager and blogger, and Sanjiv Kaul, executive chairman at Oasys. What follows are excerpts of that conversation.

SLD: The EDA industry often gets the blame for lack of progress in semiconductor design. Why?
Domic: Sometimes the EDA industry gets criticized that we haven’t invested in systems—whatever that means at a certain level. Part of the issue is the wide spectrum of the problem and the lack of definition. We can get you a tool to get from ‘D’ to ‘G’ in a certain sequence.
Leef: And combined with that are poor economics. People interested in solving the system-design problem at the front end are not very numerous. When I used to run the internal EDA organization inside Silicon Graphics we had a guy who was the architect of the graphics pipeline. He had all sorts of fascinating problems and all kinds of things he wanted to model—but he was only one. If a commercial EDA vendor could satisfy him they would sell one copy of the product and charge $1 million for it. The areas with the problems also have poor economics.

SLD: With modeling environments like TLM 2.0, hardware-software co-verification and high-level synthesis, there are a whole bunch of new areas that are not well defined or included in the flow. How do you deal with this?
Leef: There is a dimension of co-verification that has been well understood, which is at the RTL level where you have your design in RTL and you introduce a processor that is expected to run embedded software. The co-verification problem is essentially solved. You have a transmission mechanism that allows the software to be simulated very rapidly with hardware that is not all relevant, and the transmission slows down when you want to observe the bus cycles. At that level of abstraction, this has been solved. But at the higher level of abstraction what we’re running into is a lack of commonly accepted practices as to how people model systems like that. There are numerous examples where people decide to create abstract models that go really fast, and at the end of the day these models are rejected because they do not have enough details to be useful. And once they have enough details to be useful they lose the speed.
Kaul: Most of EDA is not market-sector dependent. RTL-to-GDSII uses the same synthesis tools and place-and-route tools. But when you get to system-level design, people designing cars have very different needs from the people designing airplanes, who have very different needs from the people designing DSPs. The models are key to that. The amount of detail needed on the models varies based on the kind of analysis you want to make. That’s one of the reasons why the market requires very deep domain problem about what the end customer is doing. For most of EDA, you need to understand semiconductor design. But with system-level design you also need a deep understanding of the end market. It’s hard to build, and especially to build it in a cost-effective way.
Leef: If you look at Bosch in the automotive sector, they really do need to model the hardware. However, once they deliver their solution to BMW, then BMW no longer cares what’s inside the electronic control unit. They care about the software and the network. They assume the electronic control unit and all the underlying hardware works correctly. Even though they characterize the problem as system simulation or co-verification, what they’re trying to analyze is drastically different from what Freescale or Infineon are trying to analyze before they gave it to Bosch.
Domic: The problem there becomes how many. In general, the EDA industry is investing much more. EDA has had emulation for quite awhile. We offer boards based on FPGAs where you can map and do some of the software verification. The reason a larger investment is going into these areas is the need for models. It may be hard to create a model for BMW when all they care about is the connection with the outside world. But when a platform gets standardized like a TI OMAP, where you have a couple of ARM cores and DSPs, you can’t provide a virtual platform. The problem has to be bound and specified.
Leef: The back-end part is relatively predictable. At the end of the day you’re going to build silicon. But the front-end part is more and more application-specific. IBM uses similar language to what we use, but once you dig into what they’re trying to accomplish it’s quite different. For example, they were talking about doing simulation at the car level and they were talking about simulating a network that contains 80 computers with sensors and actuators, gigabytes of software, all united by different types of networks. You’re not trying to verify the correctness of a Freescale semiconductor that lives on the ABS (antilock braking system). You’re trying to figure out when a customer presses the brakes, what are the external things that can be tolerated. That involves simulation of traffic on the network, mechanical modeling of the brake system.

SLD: Is this even an EDA problem?
Busco: And how have companies solved this in the past? Is it through in-house modeling? Or have they not even used automation?
Leef: The degree of design automation declines as you move further from tier-two suppliers. The silicon providers in this case—Infineon, Freescale, Renesas—are no different than TI and Intel in terms of the problems they’re trying to solve. When you go to Bosch and Delphi, they start to look more like PCB players. And then you go to the next set of players, they’re airframe designers. It’s a system of systems. The people who run those companies come from either a mechanical background or a financial background. They don’t have a direct appreciation of design automation. They wouldn’t think twice about spending $300 million to $400 million on prototypes, but they would argue over a $5,000 or $50,000 piece of software forever.
Kaul: People in those areas would use C models or The Mathworks.
Leef: The degree of automation in automotive is variable. One company has been trying to use MatLab Simulink, which only allows them to look at one dimension.
Domic: Given this lack of uniformity, and everyone trying to build something ad hoc, people try to answer very specific and narrow questions. Does the ABS react and work with the steering system? It’s a very specific question. You’re not trying to create a model that describes everything that happens to the car because that’s impossible with the current technology. On the other hand, when you do RTL for a chip you have an expectation it is an incredibly complete description of what a chip does. We have no tools that would synthesize a transaction-level model into a C model down to RTL. One part of the problem is that when you build a model you are trying to answer a very specific question.
Leef: The problems you’re describing are deterministic. In distributed systems, determinism is lacking. The problem they’re trying to find as the customer presses the brakes is why the signal doesn’t get to the brakes. It’s because the network is jammed with the temperature reading from the rear seat. The traffic on the bus is something that is irrelevant.
Kaul: These are very domain-specific and very hard to make a commercial business out of. That’s why customers end up doing a lot of this on their own.
Busco: To take a baby step of synthesis and try to raise the abstraction of that hasn’t been more accepted in the design community. Everyone does RTL synthesis. There are so many different domain languages, whether it’s C or SystemC or something based on MatLab, and yet designers are very hesitant to let go of the control and the quality of results they get from RTL.
Leef: The hardware guys are really married to this idea of precision and concurrency and timing being embedded into the language and the software guys see it differently.

SLD: Is it becoming a choice? You’re no longer designing the RTL. You’ve got power issues, software and signal integrity issues. Can you ignore these new techniques and still progress with a chip?
Kaul: Why haven’t people moved higher? Because getting from RTL to silicon is still such a problem. People need to have the level of control they get from RTL, and they need the visibility downstream to be able to design those chips.
Domic: The tools have progressed in terms of taking care of these things. But 20 years ago, if you look at RTL description languages, Intel had its own language, IBM had its own, and Digital [Equipment Corp.] had its own. VHDL took over. There are a myriad of descriptions above RTL.
Leef: But they don’t have a link to implementation.
Domic: I don’t think that’s a problem, because RTL methodology in large companies took over before synthesis was a viable alternative. Intel was using IHDL in the mid-1980s. I don’t think the key issue is a lack of a path to synthesis. But we have not done a good job in telling developers that C may not be perfect, but it’s more than enough to make good progress. Verilog may not be perfect, but for a lot of people it solved 90% of their problems.

By Pallab Chatterjee

The mobility that is best associated with “smart phone” functionality is making its way into most other electronic systems. At ISSCC and even the Strategies in Light conference, systems and products were being shown featuring standard RF interfaces.

The RF is being made available as standalone die for multi-die and 3D packaging, as well as in SoC IP blocks. The functions that were displayed were full radios in the 802.11, WiMax, 3G, Bluetooth, and in the 802.15 (Zigbee) space.

The availability of wireless access to remote systems, such as through the Internet or to local household/office environments, has changed modern SoC architectures. New systems embracing this functionally include medical devices, home automation (lighting, A/V, environment, security), smart appliances and fixtures, automotive, sensors and asset tracking. The standard SoC now being created incorporates the microcontroller(s), program store memory, power management, custom control logic, sensor interface (data converters) and now an RF interface block. On most of the systems, the RF block is replacing the video and standard wired communication block, and is closely integrated with the power management function to ensure the operational life, especially with battery-powered systems.

At Strategies in Light, which focused on new low power, high-brightness LED (light-emitting diode) lighting solutions, Marvell Semiconductor and NEC both displayed wireless control systems for lighting. In addition to dimmer systems that support LEDs in DALI applications (DALI is an international standard for ballast control), NEC was showing new modules based control systems that have a receive module in the lighting unit and a controller based board with RF that features a full software and GUI based control panel. This allows for full programming of lighting banks, color and intensity of LEDs, as well as light output, duty cycle and degradation of the units. It also provides for advance scheduling of maintenance on the lighting modules in industrial applications rather than having to do in-the-field response to a lighting head failure.

Marvell was showing off a control system that fits inside the base of a standard light bulb, which transforms an LED bulb into a smart system. It includes an RF interface – either Zigbee or Bluetooth for home automation application or 802.11 to interface to a home /office network. The company demonstrated the system using an iPhone as a controller, and it has a full SDK for application developers to create their own interface and feature set. With the iPhone users can remotely turn on/off and dim the device, as well as track hours of operation and power use. The same controller ICs can be used in combination systems that have motion sensors, temperature sensors and other function to supplement the lighting function, and send data through the RF channel.

At ISSCC a tutorial on RF integration into SOCs and design of Smart Sensor Systems led off the conference. Following the tutorials, papers were presented on a wireless 32-channel neural recoding SOC, a supply current modulated AFE based neural recording tag. The keynote from Bosch Electronics and TI both discussed the wireless interface to sensor devices and MEMS and the prevalence in current communication and automotive systems. The Emerging Medical Application session, was filled with telemetry based and wireless power based SOC applications.

The extension of this wireless integration is projects such as HP’s CeNSE (Central Nervous System for the Earth) project. CeNSE is a meta-project involving multiple HP Labs focused on enabling a planetary system of a trillion nanoscale sensors and actuators embedded in the environment and the networks to exchange their information among analysis engines, storage systems and end users. It is a system based on building nanoscale sensor nodes to wireless and photonic networks to storage and computation to data visualization, information theory and analysis. It is entering it first phase of delopyment in 2010.

System-Level Design sat down with Keith Barkley, senior engineer in IBM’s systems and technology group; Steven Schulz, president and CEO of Silicon Integration Initiative (Si2); Yatin Trivedi, director of standards and interoperability programs at Synopsys; Ian Mackintosh, chairman of the OCP International Partnership (OCPIP), and Michael Meredith, vice president of technical marketing at Forte Design Systems. What follows are excerpts of that conversation.

By Ed Sperling

SLD: Problems lead to standards, followed by new problems that require standards. What are the problems that need addressing now?

Schulz: Our next effort will be to create a standard for 3D chip integration. This is an important area as Moore’s Law runs out of economic steam, if not technologically. The need for stacking die, and having standards for through-stack vias, how you handle the electrical modeling of that and the geometrical positioning and synchronizing of them has to be done not only across a multivendor flow for a particular die, but across different companies that are putting together the different die that you’re assembling into a package. Many companies have said they’ve gone as far as they can go without standards. You need the processor and stacked memory. If you’re doing a wireless communication device you’ll need the RF fabric with analog baseband on top of some digital and some memory. Often it’s easier and cheaper to do it with different die.

SLD: Is that because of heat?

Schulz: Both heat and economics. To continue integration in 2D is getting too costly, the line lengths are too long, there are uncertainties of how you do the routing, the design fabric—everything has its own specialty from a manufacturing standpoint. The real estate is a problem.

Meredith: As a general rule of thumb, the need for standards in EDA are always at the top and at the bottom. At the bottom, it’s where new process geometries create new challenges. And at the top, as we try to raise the level of abstraction we’ve got SystemC and ESL standards.

Trivedi: Whether it’s top and bottom or front and back, the IP goes all over the place. How you use it, deploy it, verify it and integrate it may be in the middle of the design process. I think of it more as exigencies, not top or bottom

Mackintosh: I think the hotspot right now in all of this is the economy. The result is that more people are open to standards and need to share costs. They’re far more open to collaborating and getting to market faster because there are fewer opportunities these days. Standards allow you to commoditize expert knowledge.

Barkley: Even internally at IBM we’ve been trying to share IP among the P series and Z series. We had to enforce internal standards just to be able to share things among our own groups. In terms of sharing costs, IBM years ago had its own internal models, GL1, NBRs, which really gave us a competitive advantage. What we found is that we couldn’t afford to do everything ourselves. We started working on OpenAccess in 2003. We’ve gone from GL1 to Oasis. We’ve gone from internal data models like VIM and CDBA to OpenAccess. We’ve moved away from our internal models and rules to industry standards, which allows us to use some of the vendor simulation and analysis tools we had to develop internally. That actually prevented us from using some of the vendor-provided software, which we had access to for years.

SLD: IBM has always trumpeted its proprietary tools as a competitive advantage. Has it gotten too expensive to continue with that?

Barkley: Yes, and that’s no longer the case. At the end of the day we have to make designers productive. There are some conflicting opinions inside of IBM, but from a high level our design executives never considered this stuff proprietary. Over the last five years we’ve been collaborating with Cadence on the advanced routing and chip optimization. We shared technology, design rules and software IP. There’s not a whole lot we consider proprietary now except product road maps. We are not an EDA organization.

Trivedi: From a user perspective, you can see why sharing makes sense. They are creating a subsystem that needs to prototype outside, so they need to have certain standards and well-defined processes, or they need to import things because they can’t do everything themselves. It’s a matter of what the rationale is for you to share. At one time IBM, HP, Intel and TI did everything themselves. Everyone was an IDM (integrated device manufacturer). There was no need to share. The only thing you knew was how many pins it had and there was a data sheet. That was the interface. Now you’re working at a much more granular level. I can only produce libraries, for example, that everyone else uses. Or I produce this IP block and everyone else uses it. Or I develop the software and I need to know your register definition.

Meredith: The financial model is the same, whether you’re collaborating or sharing. People don’t have the money to do everything themselves. They need to be able to collaborate with specialists in some areas. What that requires is the creation of an ecosystem of specialists working together.

Trivedi: The question is really how much control you want to exert and how much you can exert. The more control you can exert, the less need for standards.

Schulz: That also means you’re self-sufficient, from A to Z.

Meredith: But if there are five gorillas in the industry, that means each job is being done five times and their customers are paying for it to be done five times. It’s an inefficient approach to delivering value.

SLD: Let’s roll this back a little bit. When did big companies like IBM and TI stop developing their own tools and begin using off-the-shelf tools? And why?

Schulz: It’s a function of the maturing of the industry. Back in the 1970s at TI we grew our own crystals. As the industry matures, you specialize. And a bad economy forces those issues. In the past, we weren’t at the level of complexity involved now in moving from concept to packaged device. In the past, the IDMs owned their own fabs. Many of them are fab-lite these days. The business is much more fragmented. We have more integration, more features, and more levels of abstraction.

Mackintosh: The issue is integration. Because of that, there’s much more compartmentalization across the chain. The result is that people can only afford to play in certain areas.

SLD: And they need to extract value from those areas.

Mackintosh: Yes. They need to decide which areas to play in and eventually they have to learn to share.

Not everyone is feeling the pinch of the downturn. Synopsys’ income for its second fiscal quarter, ended April 30, grew 10.5% compared with the same quarter in 2008. In dollars, net income was $65.9 million.

Considering the downturn was still going on in 2008, this is an apples-to-apples comparison. But there’s a word of caution that needs to be infused in here. Next year, when everyone is comparing their growth in a normal year (hopefully) to the current downturn, it will give the illusion that we are in a period of booming growth. The better way of looking at that will be a five-year trend line, which will smooth out the radical swings and give a much more meaningful picture.

For fiscal 2009, Synopsys anticipates $1.35 billion to $1.38 billion in total revenue. Break out the champagne and party hats.

Cadence inked a deal with Virtutech to add metric-driven verification to Virtuatech’s virtual systems development platform. This is definitely a step in the right direction—get as much modeled and verified up front as possible to avoid problems prior to, or after, tapeout. How many re-spins did you have on your last project?

Speaking of getting more done up front, ARM’s new approach with its RealView Development Suite is to make it vendor-specific to create pre-tested and configured solutions for its IP. The good news is this makes the job easier. The bad news is that ARM can actually count its top customers on one hand—TI, Atmel, Freescale, Samsung and ST.

And in the memory IP space, Virage Logic introduced a 65nm version of its multi-time programmable non-volatile memory on TSMC’s low-power process. Considering that’s where all but a handful of companies see the leading edge of technology these days, this is a smart business move on Virage’s part.

–Ed Sperling