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Manufacturing Challenges 3D NAND Deployment

Thursday, August 31st, 2017

Jim Feldhan, president of Semico Research and veteran semiconductor analyst, shares his views on the challenges of moving from 2D planar to 3D NAND flash.

By John Blyler, Editor-in-Chief, Electronic Systems Design

3D NAND flash is touted as the eventual replacement for bit density limited 2D planar NAND flash. Its arrival into the mainstream memory market has been delayed by several years but should commence toward the end of 2017.  The delay has been caused by a steeper than expected learning curve in the manufacturing process. To understand why, Electronic Systems Design spoke with Jim Feldhan, founder and president of Semico Research Corp. What follows is a portion of that interview. – JB

Blyler: What are the general trends in NAND flash technology?

Jim Feldhan

Feldhan: 3D NAND is an evolutionary, architectural change that was needed to deal with the scaling limitations faced by planar 2D NAND memory. One major benefit of 3D NAND is that it will be manufactured on slightly older and less expensive process nodes.

Blyler: What unique costs are incurred for the manufacturing of 3D NAND Flash?

Feldhan: Depending upon the architecture, manufacturing at higher process nodes like 40nm can save money in terms of lithography requirements. However, since a common practice is to make 32 to 48 vertical layers or more in the 3D design, a significant increase can occur in etch costs. Holes must be etched between the different stacked layers to serve as inter-connections between the vertical layers.

Even though 3D NAND go back to older, higher process nodes for the lithography, the bit density is still increased via vertical stacking. The trick has been to fine tune the etch processes so that the yields remain good while achieving lower costs. Like any new process technology, it takes a while to get up that learning curve to maximize the yield.

Blyler: Increasing the need for additional etching should be good news to the semiconductor capital equipment companies.

Feldhan: Yes. With 3D NAND, you’ll have an array that is more like a cube or a three dimensional chess board with interconnections and wires going horizontally and vertically through the matrix. That is why companies like Applied Materials and Lam Research are thrilled since memory manufacturers will have to buy 5 or 10 times the amount of etch tools.

On the technology side, there has been interesting things with the resist, specifically, they can do several etches with the same coating of resist. More specifically, new materials on the resist allows for multiple etches without recoating. This process will save both time and money. [Editor’s Note: A resist is a thin layer used to transfer a circuit pattern to the semiconductor substrate which it is deposited upon.]

Blyler: Is 3D NAND more reliable than planar?

Feldhan: One of the original questions was how reliable is 3D NAND flash. The relaxed lithography node means you are not squeezing everything together so cross-talk is less. Also, 3D NAND has substantially more interconnections with vertical architecture that might provide you with access to more redundant cells. These redundand cells could be used if or when other cells fail. As 3D NAND has only been out for a few years, I haven’t really seen any lifecycle test data. But what I hear from Samsung and Micron is that 3D NAND is getting good acceptance from their customers. That’s impressive as many of the early customers are in data center applications that are really particular about failure rates.

Blyler: How does the Intel-Micron Optane differ from other 3D NAND flash technologies?

Feldhan: The Intel-Micron technology is called 3D Xpoint. They’ve described it as changing the physical properties of the material, which sounds more like a phase-change technology than a 3D NAND architecture. Further, the description made it seem different from the phase-change technology announced by IBM many years ago. Apparently, Intel-Micron have spent quite a bit of time working on a new material that they think solves all the problems faced by the original phase-change memory devices.

Blyler: So the Intel-Micron 3D Xpoint technology seems like it will be competing with 3D NAND flash. Is that correct?

Feldhan: Well, the XPoint platform is a different technology than with what everyone else is doing on 3D NAND. But Intel is doing both approaches, as I understand it. Their fab in China is gearing up for 3D NAND in production. My estimation would be that the Xpoint is a new technology and probably has a much higher bit cost, which would explain why they are focusing on SSDs and more so on the enterprises and server farm apps.

Blyler: Let’s return to 3D NAND manufacturing issues. At some point, won’t that technology need to move to the latest process nodes and/or contain ever-increasing layers to stay competitive with the bit cost?

Feldhan: Yes, they will eventually have to move to finer levels of lithography or be able to continue to go up in vertical layers. Or some type of combination. When the major manufacturers rolled out the first 3D NAND, they were saying it would be scalable, i.e., 24 layers at first, then 32 layers to 48 layers and etc. But I haven’t seen them progress as quickly as they mentioned. So I think they are now more focused on maximizing yield and reliability. [Editor’s Note: At the 2016 IEDM conference, SK Hynix discussed stacking technologies that could potentially enable over 256 memory cell layers.But it wasn’t clear when those levels would be reached.]

Blyler: When will 3D NAND become a mainstream memory technology?

Feldhan: On the plus side, the cost of 3D NAND is reaching equivalence with 2D planar NAND. Over the last year or so, NAND flash memory prices have been driven upward from tight supply and strong demand (see Figure). These aggregate average selling prices (ASP) are average prices for all densities and technologies.  As 3D NAND production comes down the manufacturing learning curve, the cost per bit for 3D NAND will fall and 2D NAND will have to match the price to remain viable in the market. Ultimately, 3D NAND will have the lowest cost per bit and will supplant 2D NAND especially in the large density parts.

NAND Pricing

Figure: With a tightening supply and strong demand, prices for all NAND devices are climbing. Before too long, 3D NAND will be on par with 2D planar memory. (Courtesy of Semico Research).

Blyler: Thanks, Jim.

Predictions About Technology and Future Engineers

Tuesday, November 19th, 2013

By John Blyler, Content Officier

What follows is a portion of my interview with Dassault Systemes’s “Compass” magazine about the most critical technologies and issues faced by the technical community to manage increasing complexity within shrinking design cycles. My list includes hardware-software co-design; cyber-physical systems; wireless chips; low power; and motivating students to high-tech. - JB

COMPASS: The past decade has seen many milestones in hardware/software co-design. What do you think will stand out in the next decade?

JB: Thanks to Moore’s Law and the efficiencies of engineering chips and boards, these things have become commodities. Companies have been forced to differentiate themselves with the software. Also, when you design a chip, you have to think about designing the board at the same time, so you get into the co-hardware/hardware design with software tying everything together.

That trend toward tighter integration is only going to accelerate. The time to get your product to market is shrinking, so you need to have software designed while the hardware is being designed. In many instances, the software demands at the user level are dictating what the chip design will be. Before, it was the other way around.

Compass: What are today’s biggest challenges in systems modeling, integration, and designing for the user?

JB: When I tell my engineering friends the movement is toward designing for the end user’s experience, they scratch their heads. It’s easy to see how that applies to software, because with software it’s easy to change on the fly. But for hardware, that’s trickier. How is that going to be implemented? That’s something the engineering community and manufacturing community are still wrestling with.

You see it in cell phones. The end-user input must come early in the design cycle as it will affect both the software and electrical-mechanical subsystems. Further, everything has to be low-power and green. You have a mountain of considerations, aside from just getting the product to work.

Read the full interview at Compass magazine.

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