By Ann Steffora Mutschler
Driven by high-speed interfaces, the demand for TSVs and the complexities that new process nodes bring, older packaging technologies like wirebonding can’t keep up.

The latest and greatest flip chip technologies offer much more flexibility, but at a cost. As such, the package plays a larger role than ever in determining system specifications because, depending on the packaging technology used, certain system parameters are either limited or not. For these reasons packaging is being considered up front in the design process—even at the very earliest planning stages. Moreover, the cost of packaging comprises a non-trivial portion of the total system cost. Throw 2.5D and 3D ICs into the mix and things get really interesting.

These issues are breaking down the brick walls between the IC designer and the packaging designer, observed Brad Griffin, product marketing director for Cadence’s Allegro product line. “I think we have hit a point where if you don’t at least consider some of the aspects simultaneously you’re going to end up with a system that either doesn’t perform like you would like it to or has additional cost than you would like it to have.”

Shafy Eltoukhy, vice president of manufacturing operations at Open-Silicon, agrees. “Essentially when we talk to the customer initially we try to understand from them what their thermal requirements are, like power, the footprint of the package, the thickness of the package and the cost. Also, if it’s a consumer part it will be different than if it’s a networking part. The cost has a big impact on the selling price. There are a lot of factors that come in at the very beginning, that being the power dissipation, signal integrity, form factor of the package and so on.”

There’s a complicated matrix to designing a package. “In some cases, at the very beginning, you don’t know exactly what the die size is going to be because customers keep adding functions and the die size keeps changing in the early stage. Having all the requirements from the mechanical to power to this and that, as well as the layout or the floorplan of the die, is also changing up front. The package has to be part of the very early stage of the design,” he said.

The company ties the package to the floor planning and the requirement as far as the speed and other considerations. Package design engineers get on board very early in the process—even before designing the die itself—to look at it from the floor planning point of view. That includes where to put high-speed interfaces, how fast these are going to be, packaging technology, i.e. flip chip or wirebond, power expectations, and so on. “It’s very complicated and people have started putting a very good interface between the packaging and floor planning engineers,” Eltoukhy added.

Broadcom recently detailed its experience making early tradeoffs during Cadence’s CDN Live event in March. The presentation can be viewed here (registration required).

In this case, using Cadence technology under development, Broadcom enabled its PCB designer to look at what the package footprint should be to best match the components on the board. From there it drives up from the package footprint to the bump matrix for the chip. They were able to determine the ideal bump matrix for the chip to be able to match the package footprint. Then from the bump matrix that drove the I/O pad ring to get the I/Os and chips placed properly.

Then, when it comes to 2.5D design, packaging issues are actually more complex than what they will be with true 3D ICs, according to John Park, methodology architect for IC packaging and pathfinding technologies in the Systems Design Division of Mentor Graphics. “I believe—and many of my customers believe—it is more complex because you have this intermediate substrate in which the die connect through these small microbumps, and there’s this die-to-die connectivity that happens on some unknown number.”

Engineering teams really want to save costs, or at least make the tradeoff of cost and thermal, etc., Park added. “They want some global routing technology that allows them to say, ‘What if, on the interposer, I limit it to three metal layers? Does that mean I need to add two more layers to my package substrate or does it mean that I have to add eight more layers to my package substrate?’ In that case, maybe they say, ‘I’m going to add one more metal layer to my silicon interposer so that I can reduce the layer count of the package.’ Now the costing gets very complex because you have this new intermediate routing structure that sits in between the traditional die to package connectivity that greatly impacts cost, routability, signal quality—all these types of things.”

Although some of these issues won’t be a problem with 3D, don’t expect a mass exodus from 2.5D when 3D becomes mainstream because it may be more expensive, noted Cadence’s Griffin. “You’re going to have to get to a certain quantity before you’re going to realize the value in going to 3D IC, so there’s going to be still a fair amount of chips in the lower to mid quantities for which they want to realize the performance gains of going to a silicon substrate to connect things together but they can’t necessarily go to the expensive TSMC to be able to connect all these things together properly. [Systems companies] will rely on less-expensive silicon interposer technology; it will have a little less performance but cost-wise, it will just be more efficient for them. I think you’re going to see both for quite some time, but i think you’re going to see the very-high-quantity things move to 3D IC as much as possible.”

By Ed Sperling
Synopsys continued on its acquisition path, this time buying RSoft Design Group, which makes photonics design and simulation software. Synopsys has been pushing steadily into the optics design market, beginning two years ago with the acquisition of Optical Research Associates.

Cadence won a deal with Fujitsu Semiconductor, which is using Cadence’s Chip Planning System to build microcontrollers. Fujitsu ranks seventh in the world in the MCU business, with 5.5% of the market, according to Data Beans. The company was No. 3 in 2010, so apparently it’s time for some serious retooling.

Arteris won a deal with IC-Logic, which licensed its network on chip and interconnect IP for automotive infotainment SoCs. IC-Logic is based in Sulzbach, Germany.

Tensilica teamed up with VWorks to provide virtual prototyping platforms, especially for multi-core designs. VWorks does advanced simulation and modeling.

TSMC sales, which are something of a bellwether for chip activity, were up 9.3% in April compared with March, and 10.4% year over year. Things seem to be picking up. http://www.tsmc.com/tsmcdotcom/PRListingNewsAction.do?language=E

By Ed Sperling
Cadence rolled out a low-power reference flow for SMIC’s 40nm process, from RTL to GDSII. What’s particularly noteworthy is just how fast SMIC moved ahead in process technology.

Arteris won a deal with MtekVision, which licensed its MIPI Low Latency Interface inter-chip link IP for multiple SoCs. The big selling point on LLI is it reduces the bill of materials by an entire memory chip.

TSMC’s net sales increased 9% in March compared with February, while revenue for Q1 increased 1.7% over the same period in 2011.

Intel inked a joint development agreement with the Beijing municipal government and the Chinese Academy of Sciences for research into a Chinese “Internet of Things.”

By Ed Sperling
Synopsys rolled out a suite of integrated tools specifically for both 2.5D and 3D stacked die, setting the stage for a huge change in how ICs are designed and packaged over the next decade. The company also introduced its audio subsystem, complete with IP, tools, a processor and audio codecs. In addition, Synopsys teamed up with Altera and TSMC for silicon-accurate parasitic modeling and extraction at 28nm, and it created parasitic extraction models for double patterning with an industry consortium.

Mentor Graphics added support for the Yocto Project, allowing its embedded Linux middleware to support the various flavors of Linux development without putting the burden on developers. This is an important step forward in the commercialization of Linux, where development has been piecemeal in keeping with its university/scientific roots. Mentor’s tools allow developers to build embedded systems without worrying about which hardware to use. Mentor Graphics also teamed up with Triad Semiconductor to create a low-cost, mixed-signal tool the companies claim can slash costs and development time for mixed-signal ICs. Triad is based in Winston-Salem, N.C.

Cadence announced verification IP support for two new enterprise-level cloud storage standards, NVM Express and 12GB/second SAS (serial-attached SCSI).

By Ed Sperling
Cadence rolled out new LPDDR3 memory IP, upgrading the bandwidth management engine to improve performance while lowering power consumption. The company also expanded its Shanghai office for R&D, as well as sales and technical support.

Synopsys rolled out verification IP for Non-Volatile Memory Express (NVMe), which allows solid state drives to connect directly to PCI Express. Synopsys also announced its VDK family of products for ARM Cortex processors, including big.LITTLE.

Altera has jointly developed its own 3D IC test vehicle using TSMC’s chip-on-wafer-on-substrate integration process. This puts Altera head to head with Xilinx on stacked die.

And GlobalFoundries shipped its 250,000th 32nm high-k/metal gate wafer, thereby ending speculation about whether HKMG will ever go mainstream. The 28nm node uses the same technology.

By Ed Sperling
Synopsys is working with Applied Materials on TCAD models for 14nm and 11nm logic and memory chips. The collaboration covers front-end-of-line to back-end-of-line reliability. The two companies previously collaborated on of projects, including TSV development for stacked die. Synopsys also has been working with Global Unichip to enable 30 tapeouts ranging from 130nm to 40nm.

eSilicon added Korea to its TSMC value chain aggregator program. Given the fact that Korea’s electronics market is booming—witness Sony’s downplaying of its digital TV future and Samsung’s growth in a variety of sectors—being able to pull together the right components and IP for OEMs there and to create designs is a significant opportunity.

Methodics integrated its VersIC platform with Synopsys’ Galaxy platform, allowing engineering teams to manage design data and IP within Synopsys’ design flow. This is particularly useful in complex designs, which increasingly rely on third-party and re-use of internally developed IP, and where libraries are now measured in terabytes.

By Ed Sperling
Synopsys’ Karen Bartleson looks at standard IP, which will become critical as more third-party IP makes its way into SoCs. Third-party IP accounts for less than 50% of IP in designs, but that’s changing quickly—which is why all of the big three EDA vendors have a big stake in IP and VIP.

Mentor’s Nazita Saye expounds on some myths, notably earthquake weather, shirt-sleeve management—and the idea that CFD tools are difficult to use. Well, there had to be a relevant point somewhere in this.

Cadence’s Richard Goering sums up his chief’s keynote speech at CDNLive, which focused on cloud computing, early and deep collaboration, and drivers such as video and mobility. More chips equals more tools.

IHS iSuppli’s Richard Cooper backs up the video growth numbers. He said that movie consumption revenue will rise steadily through 2015. Big growth markets include Asia-Pacific, Latin America, and Central and Eastern Europe. But are they all dubbed?

Synopsys’ Eric Huang trumpets USB 3.0 while his colleague, Navraj Nandra, rings praise for changes in USB 2.0. Anyone for 1.0?

Mentor’s Colin Walls spills the beans on a UBM survey of embedded developers. The unusual trend is the increase in custom OSes. But what exactly is an OS these days?

Cadence’s Joe Hupcey rolls out a series of pictures and videos from DVCon. Check out the robot that solves Rubik’s Cube. So much for brain twisters. You now can outsource that frustration to a machine. But there’s something inherently odd about buying toys for machines.

DeepChip’s John Cooley reports on hardware forum discussions about 28nm process tweaks at TSMC. There doesn’t appear to be any lasting damage, but it is an indication of just how nervous customers are getting about production at leading-edge process nodes. TSMC, incidentally, says everything is “normal.”

Synopsys’ Doug Amos rolls out part two of his epic on keeping RTL clean while mapping SoC RAM into FPGAs. This part focuses on wrappers.

Cadence’s Kari Summers is back with another five-minute tutorial, this one on selective blockage in EDI 11. If you take small bites you’ll never need a Heimlich maneuver.

By Ed Sperling
Mentor Graphics introduced a new Calibre DFM flow for GlobalFoundries 45/40nm and 32/28nm processes, which it claims can significantly boost yield and improve turnaround time for full-chip designs. Also on the DFM side, Mentor rolled out the next version of its PADS suite for PCB design through manufacturing, adding the ability to link high-speed associated nets and assign constraints.

Cadence introduced its Encounter RTL-to-GDSII flow for high-performance and giga-scale designs down to 20nm. What’s especially interesting here is support for double-patterning, one of the big issues with progressing down Moore’s Law because foundries have unique ways for doing this. Cadence also launched a business incubation program in Australia to boost entrepreneurship in this market. Nice design, mate.

Arteris inked a deal with Carbon Design Systems to enable NoC interconnect IP to be generated, managed and distributed using Carbon’s IP Exchange portal.

Atrenta announced that 10 IP providers have qualified soft IP for TSMC’s 9000 IP library using Atrenta’s IP Handoff Kit. The tool checks for syntactical and semantic correctness, power consumption and clock domain issues, among other things.

By Ed Sperling
Synopsys joined forces with Arteris to integrate Arteris’ network-on-chip models with Synopsys’ Platform Architect. What’s particularly interesting about this relationship is that it combines transaction-level modeling with a chip’s networking infrastructure. That’s important for complex SoCs, but it will be critical for stacked die.

Synopsys also introduced embedded memories and logic libraries for 28nm TSMC processes, and HDMI 1.4 PHY IP for 28nm processes at multiple foundries.

Tensilica won a deal with VIA, which will put Tensilica’s dataplane processors on its solid state drive SoCs. Tensilica also won a deal with mimOn for processors to be used in full LTE PHY reference platforms for user equipment, and another one with Acoustic Technologies, which will port its noise elimination and echo canceling software to Tensilica’s DSPs.

TSMC, a bellwether for the chip industry, reported net sales increased 11.4% between December and January, although they were down 1.1% between January 2011 and January 2012. Still, this is good news. The recovery continues.

By Ed Sperling
NXP has incorporated Tensilica’s ConnX baseband engine DSP core into its software-defined radio platform for satellite and terrestrial digital radio. The chip is being used in everything from digital radio and mobile HDTV to traffic system electronics.

Cadence published what it claims is a definitive book on advanced verification. Given the time it takes to do verification, this certainly can’t hurt.

Picochip churned out a femtocell for the consumer electronics market using Synopsys’ Galaxy flow, which speeded up migration to the 40nm process node.

TSMC reported a 4.5% year-over-year decrease in Q4 revenue, with a net margin of 30.2%. While that’s an interesting bellwether for the semiconductor industry, what’s really interesting in the earnings report are some of the other numbers. In 2012, the company expects capital expenditures to be about $6 billion. In addition, 28nm process technology accounted for just 2% of total wafer revenue; 40nm was 27% and 65nm was 30%.