By Ed Sperling
System-Level Design sat down to discuss the future of stacked die with Riko Radojcic, director of engineering at Qualcomm; Prasad Subramaniam, vice president of design technology at eSilicon; Mike Gianfagna, vice president of marketing at Atrenta; and Herb Reiter, 3D/TSV working group chair for the GSA. What follows are excerpts of that conversation.

SLD: Where are we with 2.5D and 3D?
Radojcic: I think 2.5D was a misnomer, because that implies they are sequential. It’s clear that what we call 2.5D and 3D are going to co-exist for a long time. Some things make sense with an interposer and some make sense to be 3D.
Reiter: I agree—2.5D is a parallel effort to 3D. Lots of things will not use 3D because it’s too expensive. In 2.5D we will see production this year. With 3D it will take until next year for the first ones. I would guess computing or networking would be the first.
Radojcic: I would think those guys will pursue 2.5D.
Subramaniam: Memory makers are already offering 3D solutions today. If you look at just the memory chip, to increase the size of the memory rather than the die they’re stacking it vertically. That kind of 3D is already in production. It’s the question of co-mingling logic and memory that will take time. The advantage of 2.5D is that it allows afterthought. It allows you to take an existing design and to create a new set of I/Os and put in a 3D type of application.
Radojcic: I see no value in doing that. You’re creating an expensive solution to something you can do more cheaply. If you add the 3D interposer you’re adding another wafer. That’s cost. We can solve that problem with a flip chip. It’s cheaper.
Subramaniam: I disagree. We’ve done the analysis. It allows us to take an existing design, like an ARM subsystem in 28nm, even though surrounding logic doesn’t have to be at that 28nm process node. It can be 40nm or 65nm. Rather than building a new chip at 28nm, I can take my existing design, use it as one component of my 3D IC, and build a second chip in a cheaper, older technology.
Radojcic: Yes, as long as you’ve architected your chip like that, such that you can partition it.
Subramaniam: You can’t take any design, no. There has to be some partitioning in the architecture and some forethought. It’s not 100% an afterthought, but there is still some afterthought there.
Radojcic: You have to architect for it. If you haven’t done that, taking an existing chip will just cost you more. If you have done that, of course there is an avenue to doing things better and more flexibly.
Subramaniam: There is enough flexibility in designs that allow you to partition it in some manner.
Radojcic: True, but before 3D came along most of us wouldn’t have partitioned. We wouldn’t have architected it that way. To be able to leverage that value proposition, you must have 3D in mind.
Gianfagna: That’s true. It’s a premeditated act. If you don’t think it through way up front it doesn’t work.
Subramaniam: Because the SoC has a well-defined architecture, it lends itself to this type of application.
Radojcic: But only if you plan for it ahead of time.

SLD: Is this true in all cases?
Reiter: That’s the view of a high-volume supplier. I see low-volume solutions where they use an existing die, put it face down on an interposer, and connect memory to it. So for low to medium volume, 2.5D works. You call it an afterthought. I call it a customized solution.
Radojcic: Why wouldn’t you do that in a traditional multichip package?
Subramaniam: Because you don’t get the interconnectivity. The advantage of a silicon interposer is that you get thousands of interconnects.
Radojcic: But you have to design it sufficiently so you can leverage the interconnects from die to die. If you had designed for a traditional design, though, you would say, ‘I can’t have thousands of interconnects so I’m going to make a serial interface with 100 pins.’ If you take that design for a 100-pin interconnect and stick in an interposer it’s an expensive way of doing things.
Subramaniam: You may be able to take some internal signals out, which you are not able to do with a traditional MCM (multi-chip module) approach.

SLD: Let’s do a reality check. How far along are we toward stacking?
Gianfagna: Last year we had a hot-wired 3D system that was 2D with a bunch of scripts and manual effort. The customer base had strange, contrived designs and they were trying to see what they could and couldn’t do, and the foundries didn’t know what they wanted to do. A year later we have native 3D planning capability, the customer base has specific designs for implementation this year and next, and the foundries have a laser-sharp focus on process learning, mostly around 2.5D initially. If that’s a metric, things are clearer this year than last year. From an EDA perspective, I still think the market is two years away. But we still think this is big.
Reiter: If you look at the Atom chip with the FPGA from Altera, that’s basically a 2.5D solution. The FPGA is for customizing things. The Atom chip was not designed for this application.
Radojcic: But why use an interposer? Why not use a substrate and a multichip package?
Reiter: You could do that.

SLD: What’s missing from the tools side to make all this work?
Reiter: The ability to demonstrate what this technology can do is the most important capability. If you look at big corporations, top management is still hesitant to invest in this technology. If we could demonstrate in a credible way what it can do, people will be more successful in getting money to start programs using this technology.
Gianfagna: The way that happens is the early adopters blaze the trail, everyone tries to follow and the market heats up. What’s needed are commercial drivers. The tools aren’t there, but they’re close enough.
Subramaniam: The tools are not the issue. The development needed to support 3D is incremental. It can be done with the existing infrastructure. It’s really the end application.
Radojcic: Other than path-finding, which is hard to do with traditional tools. And the analysis.
Gianfagna: The complexity is higher. We’ve discovered that, too. RTL prototyping for a single chip has a certain set of challenges. When you go to 3D the modeling requirements are much greater, the constraint generation is more complicated. And we need standards. We can generate all the constraints, but we don’t know where to put them and how to express them because there is no agreed upon way to do that.

SLD: Do the standards organizations know where to start with all of this?
Radojcic: Standards are on a good track. We’ve worked with Si2 and Sematech to propose initials blasts for standards so we can feed them into Si2 and the EDA community and accelerate the process. The bits and pieces are moving, and we are on track to have a set of design exchange format standards by early next year.
Reiter: And Wide I/O.
Radojcic: Yes. The standards are channeled and the engine is revving.
Reiter: We have a bunch of players in a 3D enablement center participating. There are 15 companies listed, including Intel, IBM, TSMC, GlobalFoundries, and so on.
Radojcic: The way this was set up was Sematech said we are going to start a 3D enablement center initiative driven by the SIA. All the members of Sematech were mapped into this. Then a number of companies like Qualcomm, LSI and ASE joined.

By Mark LaPedus
There may be a new hitch in moving to 2.5D stacked die—there aren’t enough suppliers of leading-edge, fine-pitch interposers.

That has put a crimp in supplies and raised prices significantly. A single interposer is reportedly selling for twice the price of a leading-edge 300mm wafer from a foundry today.

TSMC is one of the few vendors that can provide fine-pitch interposers for leading-edge designs. GlobalFoundries and UMC are readying their own offerings, but they have yet to to officially announce their technologies, according to E. Jan Vardaman, president and founder of TechSearch International, a research firm.

For some time, there has been a school of thought that the 3D chip market would evolve in two steps. First, vendors would develop 2.5D devices using silicon interposers, followed by the evolution of true 3D devices based on through-silicon vias (TSVs). But now, many experts believe that 2.5D chips using interposers will have a life of their own and will become a significant market.

Silicon interposers, at least in the initial iteration, are passive components that provide an intermediate layer between the substrate and the active device. The connections between the interposer and active device is handled through microbumps. And the connection between the interposer and packaged substrate is done via solder balls and TSVs.

“Silicon interposers are the new multi-chip modules,” said Subramanian Iyer, an IBM Fellow and chief technologist for the Microelectronics Division at IBM Corp. “They are potentially cheaper. So they are the first and very useful step in the 3D progression and will likely be adequate for a great many applications.”

At last count, there are 11 companies that supply silicon interposers, although most are not supplying fine-pitch components for leading-edge designs. Many offer larger-pitch interposers for MEMS, RF and other applications. Today’s interposer suppliers include Allvia, ASE, DNP, EPWorks, IBM, IMT, IPDiA, Silex, SPIL, STATS ChipPAC and TSMC, according to TechSearch. Others are in the planning or R&D stage, including Ibiden, Samsung Electro-Mechnical, Shinko and WLCSP, according to the firm.

The lack of supply for fine-pitch interposers is causing these components to be sold at a premium. Manish Ranjan, vice president of advanced packaging at Ultratech Inc., said the cost for a 300-mm, 28-nm wafer at a foundry is around $5,000 today. In comparison, there are reports that the interposer itself is about $10,000 alone, Ranjan said. “There are few people” that can make fine-pitch interposers, he said.

By Ed Sperling
Sonics filed suit against Arteris for infringing on network on chip patents, while Arteris rebuffed the claims. Things must be really heating up in the NoC space. http://chipdesignmag.com/sld/blog/2011/11/03/sonics-sues-arteris/

Tower Jazz’s qualified Cadence’s mixed-signal solution and PDK for its 180nm and 350nm reference flow 2.0 using bipolar CMOS-DMOS (BCD) process technologies.

ARM acquired Prolific, a startup hat develops tools for optimizing power, performance and area.

Also on the IP front, Methodics entered the Japanese market with its SoC design data and IP management platforms. Japan is one of the leading adopters of advanced EDA tools and IP.

GlobalFoundries named a new CEO, Ajit Manocha, which is rather anticlimactic. He had been serving on an interim basis since June.

And TSMC reported its Q3 numbers. Revenue decreased 4.5% sequentially from Q2, but it was up 4% from the same period in 2010. What’s particularly interesting is the breakdown. The company said 40nm and 28nm accounted for 27% of total revenues, while 65nm accounted for another 27%.

By Ed Sperling
A series of recent announcements by the Big Three EDA vendors and their well-known partners from across the disaggregated SoC ecosystem is lending new credence to the impact of collaboration.

While IDMs such as Apple, Intel, Samsung and IBM continue to blaze their own trail, developing in-house tools, methodologies, processes and chips, fabless companies working with foundries and tools developers are beginning to show some of the same benefits for a much lower cost.

One such effort involves Cadence, ARM and TSMC, which together unveiled a 20nm Cortex A-15 chip. Mike Inglis, executive vice president and general manager of ARM’s processor division, said teams from each company worked closely together to find out what was broken on the process side, then fed that information back into performance optimization and packaging and worked it into the design flow.

“This is how you more easily get to a more optimized solution more quickly,” Inglis said. “It also enables the leading edge and the trailing edge to get to market more quickly.”

This is what IDMs have always done, taking information back and forth between the design teams and the fab and adding tweaks all along the way. But what’s changing is that fabless companies appear to be catching up more quickly than most industry observers believed was possible.

“We’re seeing collaboration that is both horizontal and vertical,” said Lip-Bu Tan, president and CEO of Cadence. “Horizontal involves industry standards among peers and does not differentiate end products. With vertical collaboration, the goal is an end product that is differentiated, whether that involves IP, EDA, the foundry or software.”

Mentor Graphics, meanwhile, rolled out the next version of its Nucleus real-time operating environment that was developed with partners such as Texas Instruments, GCT and Stonestreet One. In a move aimed at conserving power, Mentor has moved some of the power management capabilities such as dynamic voltage and frequency scaling into the kernel of the RTOS, according to Jan Klube, director of the Nucleus product line.

“The software design was built into the application from the beginning versus folding complexity onto the application,” said Klube. “So developers get a simple power management API and a power-aware RTOS.”

One of those developers is TI, which has been working with Mentor as well as ARM for its Stellaris microcontrollers. Miguel Morales, worldwide marketing manager for the MCUs, said the microcontrollers are sold with pre-written software wrapped up in kits.

“Collaboration will have to accelerate,” said Wally Rhines, Mentor’s chairman and CEO, who noted that Mentor is also working with TSMC on “reliability” kits. He added that it will be critical to respond together to new and emerging problems, particularly with stacked die where stress, thermal and parasitic effects will create as-yet unknown issues.

Synopsys, meanwhile, has been working closely with TSMC and ARM to improve yield and deal with process variations.

“As we look ahead, there is the notion that an upstream tool can know what a downstream tool must do,” said Aart de Geus, chairman and CEO of Synopsys. “We need to be able to move forward to place and route before we finish synthesis, and we need to be able to question why we should do all the work if an issue is not resolvable.”

De Geus noted that collaboration is the answer to systemic complexity. “We must be committed, and we will need to collaborate with partners that have competence.” He added that there also is a need for quick compromise, balancing a “great enough” solution against a better one that will take longer to develop.

By Ed Sperling
The number of changes that will hit the IC market over the next few years is almost staggering by any standard—past or present. In addition to the relentless pressure of Moore’s Law, there will be new materials, new structures, and new models for developing and packaging chips.

System-Level Design asked executives from across the SoC ecosystem what will change, what’s driving those changes and what the ideal SoC will look like in the next few years. Here are some projections, broken down by category:

EDA
Wally Rhines, chairman and CEO of Mentor Graphics—“The SoC at the leading edge will not be a standalone device. It will be adjacent or under other things, whether it’s a stack or an interposer, or whether it’s an SoC with memory attached. One big challenge we had was with the package verification tools for 3D. Rather than create one mega merge of GDSII we’ve had to do a careful partitioning of individual SoCs and interfaces. In our opinion 2.5D will overwhelm the other approaches for a while. Logic with memory and through silicon vias is in the early stages. An interposer with memory stacked on processors that are tightly integrated is much further along.”

Aart de Geus, chairman and CEO of Synopsys—“We’re looking at smart everything. There will be more and more cores with little IQs. There’s an Internet of people, but there’s also an Internet of things, which will be a combination of all capabilities and probably require a price decline. From a technological perspective this will be really hard, of course. But what’s new? The continuation of technology is still there and we still have all the same problems with test and verification. But we also have 25 years of backward compatibility.”

Lip-Bu Tan, president and CEO of Cadence—“Application-driven design will be the big shift. The software will drive the hardware and the hardware will drive the software. It will be both. At the foundatation will be complex digital blocks with analog blocks and key IP that has been optimized for the system. The reason is that the system guy now expects silicon and the entire hardware-software stack. Some of the apps and the IP will be able to be re-used, which will make the time to market shorter. Some will not. Right now the bottleneck is in the IP, software and total solution.”

Mike Gianfagna, vice president of marketing, Atrenta—“There are two threads to this. One is that the software guys will be driving the agenda. Software dictates the silicon and the battery life. You will have a rich library of building blocks put together against software requirements, and the hardware architecture will be abstracted so that software runs against that model. The second thread is that the tools will have to change. Early floor planning and physical analysis will be required with stacked die because there are multiple ways to put a stack together and you have to get it right the first time. A 3D stack will have to be planned and analyzed. There may be 20 possible ways to build it, but only one or two that make sense.”

IP
Simon Segars, executive vice president and general manager of ARM’s Physical IP Division—“The biggest change will be power management, which will require a collection of different processing elements. You won’t see a big, monster CPU in the future because that isn’t power efficient. The future will be distributed computing. It won’t be easy, of course. With software, physically building software that can deal with the whole system will be very difficult. There also is a big challenge in putting chips together in a cost-effective way.”

Simon Butler, CEO of Methodics—”The big challenge will be bringing business intelligence into SoC design. You need to know what EDA tools to use and what the quality is of the blocks that you are putting together. And you need to define the versions of all the IP blocks and where they’re being used around the company. The goal is to see a map of the IP fabric in a design. This isn’t being done today.”

Manufacturing/Assembly
Prasad Subramaniam, vice president of design technology at eSilicon—“SoCs will have to evolve into major platforms where 10% of the platform changes and there is commonality of 90%. Otherwise it will be completely unwieldy. That 10% will still be 20 million gates. That also includes the software infrastructure, which will allow you to do performance analysis at the system level and make tradeoffs at the architectural level.”

Tom Quan, director at TSMC—“At the advanced nodes we’re looking at baseband and digital for 28/20/14nm. We’ll need 2.5D and 3D to bring the rest of the system together. So we’re getting ‘More of Moore’ coupled with ‘More than Moore.’ There will be fewer design starts, but there will be more derivatives. The base platform will be programmable with a lot of diversity, so you may see a company sell a platform and build applications on that.”

By Ed Sperling
Synopsys reported strong growth in its third fiscal quarter, with revenue increasing to $386.8 million compared with $336.9 million in the same period in 2010, and net income of $52.1 million compared with $39.3 million in 2010. Non-GAAP net income was $68.1 million vs. $58.2 million in 2010. CEO Aart de Geus attributed the growth to new designs of mobile devices, cloud infrastructure and more electronic content in just about everything.

eSilicon has agreed with TSMC to provide long-life process technology support for their customers. That’s particularly important at older process nodes, which are likely to be mixed with newer technology processes in stacked die configurations. Both companies continue to work together at advanced nodes, as well, including 28nm, reflecting their increasingly tight relationship. eSilicon is a member of TSMC’s value chain aggregator partnership program.

By Ed Sperling
Cadence won a deal with Taiwan-based Sunplus Technology, which has adopted Cadence’s TLM flow for its next-gen SoCs. Sunplus makes chips for TVs, set-top boxes and DVD players.

MIPS won a deal with Loongson Technology Corp.—a Beijing-based company formed through the Beijing Municipal Government, the Institute of Computing of the Chinese Academy of Sciences and the Loongson development team—to use its cores for everything from high-end computing, cloud servers to embedded applications in the industrial control, smart meter, automotive, GPS and mobile markets.

TSMC’s net sales were down slightly again in July—2.9% compared with June and 3.4% compared with July 2010. Of that amount, about 0.4% can be accounted for by Global Unichip, which is no longer included in TSMC’s numbers.

Processor sales appear to be booming. Intel declared a quarterly cash dividend of 21 cents per share. Given that Intel’s stock is trading at about $20 per share, that’s a hefty dividend.

By Ed Sperling
Mentor Graphics rolled out its Pyxis custom IC design platform, signaling that it has fully digested and integrated its acquisition last year of Pyxis, which made AMS routing tools. What’s particularly interesting is that Mentor says the new platform is tightly integrated with 2.5D interconnect parasitic extraction, taking yet another step alongside its role in test to position itself in the stacked die world.  Mentor also unveiled a new program for embedded software development that includes both professional services and a suite of tools for Linux, Android, open-source toochains and user interface product and design services.

Synopsys uncorked the next version of its LightTools for illumination analysis for the lighting industry. The focus will be on lighting and solar designs, which are both rapidly growing markets. Being able to apply advanced CAD tools to these sectors should produce some interesting results.

A standard for sharing memory between two chips, which was jointly developed by Arteris and Texas Instruments, has been licensed by 10 SoC vendors in the mobile and wireless markets. You might recognize some of these names: Intel, Samsung, LG, ST-Ericsson, HiSilicon and VIA Telecom.

Ansys’ proposed acquisition of Apache Design Solutions got a boost when the U.S. Justice Department and the Federal Trade Commission reduced the waiting period for the deal. The acquisition is expected to close next quarter.

TSMC issued its Q2 earnings report. Revenue was up 6.5% from Q1 and 16% year over year (in U.S. dollars). Net income was down 0.9% from last quarter. What’s most interesting in the earnings report, though, is the outlook. The company says the “global economic condition has weakened in the last few months,” adding volatility into the supply chain and impacting the demand for wafers next quarter. Consumer and computer sements are expected to decline while the industrial/standard segment will increase.

By Ed Sperling
Cadence acquired Azuro, which develops tools for clock concurrent optimization, aka coopt. Azuro claims it can reduce clock-tree power by up to 30% and overall system power by 10%. Given the increasing number of clocks in SoC designs, this can only be a good thing. Terms of the deal were not disclosed, meaning it wasn’t significant enough as a percentage of Cadence’s revenue to actually report.

For anyone who’s been contemplating the future of double patterning, strain engineering and eventually stacking of die, this stuff is no longer just theoretical. Samsung used Cadence’s Encounter-based flow to tape out a 20nm test chip. Samsung also used Synopsys’ IC Compiler and IC validator for in-design physical verification to get that test chip out.

Synopsys also is working with GlobalFoundries to deliver interoperable process design kits later this year at advanced nodes. 65nm G and enhanced low power (LPe) kits are available now.

Cavium licensed Arteris’ FleNoC interconnect IP for its processors. Given the complex interconnect tradeoffs in an SoC, this is a recognition by a mainstream processor company of how to deal with trouble spots in the future, namely plan for them.

Germany’s Dream Chip Technology inked a deal to become a Tensilica design center, supporting Tensilica’s processor core IP. Dream Chip makes SoC, FPGA and embedded software designs.

TSMC’s net sales shrank 0.9% between May and June, but they were up 1.5% year over year for that period.

By Ed Sperling
MIPS has positioned itself head-to-head with ARM in the Android world, adding yet another competitor. The other one is Intel’s Atom, of course. MIPS stake on this one involves a smartphone that passed the Android Compatibility Test Suite.

Moortec Semiconductor taped out its embedded temperature sensor IP using TSMC’s 40LP and 28HP processes and Synopsys’ custom design solution. Who says analog isn’t migrating down the process curve? Moortec is based in Plymouth, U.K. 8

TSMC’s net sales, which are a good indication of how the semiconductor industry is faring, were down 0.7% from April to May—basically flat—but they are still up 6.3% from last May, which was well into the recovery period. Revenue was up 12.2% in the same period compared with 2010.

GlobalFoundries, meanwhile, swapped out its top leadership team. Ajit Manocha will replace Doug Grose as acting CEO. James Norling will become executive chairman and Ibrahaim Ajami the vice chairman, while COO Chia Song Hwee—former CEO of Chartered Semiconductor, which was acquired by GlobalFoundries—will leave the company in August.