By Ed Sperling
UMC certified Synopsys’ StarRC extraction tools for its 28nm PolySiON and high-k/metal gate processes. Synopsys also uncorked a new release of its Synplify FPGA synthesis tool, which it claims reduces runtime by up to 30% through better algorithms.

Open-Silicon rolled out version 6 of its Interlaken IP core, a high-speed chip-to-chip interface protocol that supports speeds of up to 600Gbps. The company also announced that it had integrated 25 Analog Bits IP cores into complex SoC designs. Those cores are aimed at a variety of vertical markets ranging from networking and telecom to storage and computing.

By Mark LaPedus
There may be a new hitch in moving to 2.5D stacked die—there aren’t enough suppliers of leading-edge, fine-pitch interposers.

That has put a crimp in supplies and raised prices significantly. A single interposer is reportedly selling for twice the price of a leading-edge 300mm wafer from a foundry today.

TSMC is one of the few vendors that can provide fine-pitch interposers for leading-edge designs. GlobalFoundries and UMC are readying their own offerings, but they have yet to to officially announce their technologies, according to E. Jan Vardaman, president and founder of TechSearch International, a research firm.

For some time, there has been a school of thought that the 3D chip market would evolve in two steps. First, vendors would develop 2.5D devices using silicon interposers, followed by the evolution of true 3D devices based on through-silicon vias (TSVs). But now, many experts believe that 2.5D chips using interposers will have a life of their own and will become a significant market.

Silicon interposers, at least in the initial iteration, are passive components that provide an intermediate layer between the substrate and the active device. The connections between the interposer and active device is handled through microbumps. And the connection between the interposer and packaged substrate is done via solder balls and TSVs.

“Silicon interposers are the new multi-chip modules,” said Subramanian Iyer, an IBM Fellow and chief technologist for the Microelectronics Division at IBM Corp. “They are potentially cheaper. So they are the first and very useful step in the 3D progression and will likely be adequate for a great many applications.”

At last count, there are 11 companies that supply silicon interposers, although most are not supplying fine-pitch components for leading-edge designs. Many offer larger-pitch interposers for MEMS, RF and other applications. Today’s interposer suppliers include Allvia, ASE, DNP, EPWorks, IBM, IMT, IPDiA, Silex, SPIL, STATS ChipPAC and TSMC, according to TechSearch. Others are in the planning or R&D stage, including Ibiden, Samsung Electro-Mechnical, Shinko and WLCSP, according to the firm.

The lack of supply for fine-pitch interposers is causing these components to be sold at a premium. Manish Ranjan, vice president of advanced packaging at Ultratech Inc., said the cost for a 300-mm, 28-nm wafer at a foundry is around $5,000 today. In comparison, there are reports that the interposer itself is about $10,000 alone, Ranjan said. “There are few people” that can make fine-pitch interposers, he said.

By Ed Sperling
Altera is embedding Synopsys’ virtual prototyping technology in its ARM-based SoC FPGA products. Considering FPGA vendors have been giving away their tools for years, much to the chagrin of EDA vendors that have tried repeatedly to win a foothold in the FPGA tools market, this potentially is a big deal. And considering the existing market for virtual prototyping is still small and the FPGA opportunity is quite large…well, this gets very interesting.

On another front, Synopsys is collaborating with UMC to develop IP for the foundry’s 28nm HLP Poly SiON process.

Mentor Graphics is working with Freescale to accelerate automotive infotainment that relies on ARM A9-based processors. Mentor’s In-Vehicle Infotainment base platform is compliant with the requirements of the GENIVI Alliance, the association of automotive and consumer electronics companies.

Russia-based IntegrIT has ported its NatureDSP Math Library to Tensilica’s baseband DSPs. The traditional emphasis on science and math is still alive and well in Russia—and expanding into some new markets. IntegrIT develops signal-processing routines for DSP functions.

By Ed Sperling

As the semiconductor industry digs out from one of the worst downturns in decades, the business of semiconductor design and engineering is changing. While the architecture and features are still being developed by chip companies, the actual work of developing the chip increasingly is being done by third parties.

Outsourcing is hardly new concept in business. In the early part of the 20th century, most automobile makers recognized that it was far more efficient to design a car than produce the parts needed to run it. Outsourcing the design itself, however, has never proven successful because otherwise there would be no differentiation from one manufacturer to the next.

Even within this outsourcing there is specialization and stratification.

IDMs as foundries

Over the past decade, almost all the major integrated device manufacturers have offered foundry services to customers to help offset these costs, usually within the bounds of very restrictive designs. IBM, AMD, Toshiba and now Intel have all taken this approach, and so far none has been particularly successful. Others, such as Texas Instruments, have handed their manufacturing over to major foundries and given up trying to keep pace with rising costs for digital or advanced mixed signal chips.

The latest player to put a stake in this market is Globalfoundries, the AMD joint venture with Advanced Technology Investment Company (ATIC), the investment arm of the Abu Dhabi government that recently announced its intention to buy Chartered Semiconductor. Globalfoundries’ approach is to become a virtual IDM, creating design kits, IP, processes, and even transistor tuning and metal stacks. It does not do the place and route, however, which some of the other IDM foundries have done in the past.

“What we’re doing differently is providing feedback to customers,” said Subramani Kengeri, vice president of design solutions at Globalfoundries. “The disaggregated supply chain model was broken. We’re able to provide very early access, certification for IP—that’s product grade qualification—and we can emulate an SoC so the building blocks are verified at almost the SoC level. We also have a ‘gate first’ approach, while Intel has a ‘gate last’ approach. That gives us more than two times the gate density, and we offer SOI for super high performance.”

This is no ordinary foundry play, and Intel’s approach is to focus on a menu of possible services ranging from power and memory choices to the number of layers and transistor strategy. (See Figure 1) Paul Otellini, Intel president and CEO, said at the Intel Developer Forum last month that he expects SoCs to surpass processors as the company’s revenue stream over the next decade.

Figure 1: Intel's SoC offering.

IBM, meanwhile, has been offering what it calls end-to-end integration from design to manufacturing to characterization and test, and Toshiba has been providing complete design services for the past several years.

How successful these ventures are is unknown. None of these companies break out their revenues for these operations.

Foundries as design houses

While the IDMs seek to recoup their development costs with design and manufacturing services, pure-play foundries aren’t looking so pure-play anymore, either.

The problem with the pure-play model is that majority of designs are being manufactured at older process nodes, which is not where foundries can generate the highest profit. It’s also not where they gain the money to develop new processors or the experience on those new processes to mature them, thereby simplifying the move to the most advanced nodes and amortizing the whole investment.

This explains why TSMC took a 49% stake in Global Unichip Corp. six years ago (it has since reduced that investment), and why the big names on the GUC board of directors are the same ones on TSMC’s board. In fact, looking at the two boards it’s hard to differentiate the companies.

Rival UMC, meanwhile, struck a design services agreement with Bangalore-based Wipro Technologies for the entire design cycle for ASICs and SoCs.

Until recently, when ATIC made a bid for Chartered, it was Chartered that was claiming it was the last major pure-play foundry because of these outside relationships.

Design houses as advanced chip engineers

The last piece to change in the supply chain is the one that was predicted first—but differently. As designs become more complicated and time-to-market pressures mount for companies, many thought they would outsource some of their older designs to companies that could churn them out relatively cheaply while focusing design work on the bleeding edge of Moore’s Law.

What’s happened, however, is quite different from the predictions. Companies like eSilicon and OpenSilicon are now developing much more complex designs than anyone would have guessed. In fact, eSilicon now views 40nm as mainstream, according to Prasad Subramaniam, the company’s vice president of design technology.

Subramaniam notes that complexity is becoming so great that it’s difficult for many companies to turn out a chip or two every year. Engineers don’t have enough experience with some of the tools and difficult techniques such as multiple power islands and complex verification to work at these nodes.

Open-Silicon has reached the same conclusion after initially pitching its design services for older process nodes.

“The downturn convinced people to outsource,” said Naveed Sherwani, Open-Silicon’s president and CEO. “Three years ago our customers were startups. Now they’re large companies. We’re finding that our real competition now is the internal teams within these companies. The VP of engineering services now sees us as competition. We’re writing RTL for them.”

By Ed Sperling

Power is shifting across the design industry in multiple ways and sometimes across multiple continents, driven by complexity and cost pressures and entirely new forms of competition.

On one side of the equation, foundries are dictating more of what goes on up front in the design cycle. Design for manufacturing is a prerequisite at 45nm and below, and they’re the ones dictating the rules. Moreover, those rules are becoming far more stringent at 32/28nm because the lasers used to etch chips aren’t thin enough at 193nm—even with immersion technology—to etch all the polygons as irregularly as in the past.

On the other side, ESL modeling is removing much of the control for designs from individual design engineers used to working with RTL or various levels above that. Interfaces are entirely too complex to map out by hand, IP is bought by the block with the real challenge moving to the integration and testing of those blocks, and verification continues to become more unwieldy as tradeoffs between performance, area and power—and power in multiple states and islands—become orders of magnitude more complex.

The foundry shift

With new fabs costing $4 billion to $5 billion for the most advanced process nodes, it’s no wonder that most companies no longer can afford them. Even IBM has partners for developing new processes, and it continues to expand its ecosystem for new technologies to include companies like Sony, Infineon and AMD. And the mighty Intel, until recently the one holdout in the integrated-device manufacturing model, has shifted manufacturing for its Atom chip to TSMC.

But that shift also has concentrated an increasing amount of power in the hands of a few foundries, most notably TSMC, UMC and the Common Platform triumvirate of IBM, Samsung and Chartered Semiconductor. With cost pressures rising on them, they’re in a position to both dictate what gets built, how it gets built, and what gets used in a design.

Already, the foundries are dictating what IP gets validated. Tom Quan, TSMC deputy director, said the foundry has a portfolio of IP companies as a necessary part of getting designs into production.

“We’ve got to understand who’s doing what, who’s got the star IP,” said Quan. “We have to know all the pieces and pick the right players. We also have to look at the emerging players and choose which ones we think are the most promising. We’re betting on them.”

This becomes particularly important at future nodes. Currently, about two-thirds of TSMC’s revenue comes from the 65nm and 90nm process nodes. In the first half of 2010, the foundry estimates that half its revenue will come from 28nm chips.

That also means more restrictive design rules, because if the designs don’t head into production then the foundries don’t make money.

“Restrictive rules increase productivity,” said Quan. “At 40nm, we had some rules. At 28nm, there will be more. And at 22nm, there will be even more.”

Driving those rules are layout-dependent effects caused by everything from diffusion to stress engineering. Those effects can be theorized, but reality isn’t always the same. And that means the layout designer will have far less freedom than in the past.

That’s no surprise to some long-time industry investors. Startup Tela Innovations—notably funded by Cadence, Qualcomm and Intel, among others—is focused on developing more regular layouts to make them easier to print. Neil Carney, VP of marketing at Tela, said the company’s focus is on front-end rules, including ways to break designs into to parts using double patterning.

One source, who spoke on condition that he not be named, said the new design rules put designers back 20 years. “What you’re giving up is shape-based technology where you tune with wires and vias,” he said. “At 22nm, you’re back on the grid. Wrong-way wires will disappear.”

That opinion was echoed by Giuseppe Forniciari, senior design manager at ST Microelectronics: “At 40nm and below, wiring dominates gates and margins add too much power.” He said the need for concurrent multi-corner, multi-mode throughput on the flow is now essential.

Raising the abstraction level

While EDA executives jab at the growing control of the foundries whenever the opportunity arises, individual designers are taking shots at the growing control of the large EDA vendors. ESL modeling removes much of the control in a design from their hands and raises it to a level that makes them more reliant on tools than ever before.

This is, in part, why analog engineers have so strongly resisted using EDA tools. It’s also why modeling has experienced relatively slow growth in the digital world. But with complexity now beyond the comprehension of the human brain—particularly within the time constraints of most chipmakers—raising up the level of abstraction and keeping track of all these different levels, power states and voltage islands makes modeling a necessity.

Modeling plays neatly into the hands of the big EDA vendors, which are working on everything from simulation to validation and software prototyping. Tadahiko Yamamoto, chief specialist in Toshiba’s design methodology development group, said that with Synopsys’ IC Validation Design rule checker it was able to reduce the number of steps to three from what was previously six. In addition, total time spent was reduced to a few hours instead of more than a day.

Intel is even starting to measure progress in “time to model.” Daniel Pace, senior software engineer at Intel, said the goal is quick turnaround for adjusting the model and mixed levels of abstraction.

Conclusion

Complexity, technology limitations in areas such as lithography, time-to-market pressures and the rising cost of getting chips out the door will change fundamental power relationships within the semiconductor design industry. Systems on chip require different skill sets than simple IC designs, but SoCs built at 22nm will require different skills, tools, packaging and possibly even different substrates and materials than those built at 28nm. So far, no one is even sure what the half node beyond 22nm will be or what that will entail.

Chipmakers are coping with all of this by outsourcing designs altogether to companies like eSilicon or Open Silicon, skipping nodes, or hanging back a node or two on some products to save development time and cost because manufacturing processes are more mature there. It’s even too expensive to continue developing their own point tools at the leading edge of design, which used to be a differentiator for many IDMs—back when there were IDMs—and putting more resources into software development.

But if these kinds of changes in the industry’s power structure are happening over the course of a couple of process nodes, what will happen at the next couple of nodes beyond 22nm?

If you think things are bad, be glad you’re not in the Taiwanese foundry business—where the pain level is strangely uniform.

TSMC’s sales dropped 59.5% in February compared to the same month last year, and 7.5% compared to January. How many ways can you spell ouch? 

UMC’s numbers are down 56.9 percent in February 2009 vs. the same period in 2008. That’s pretty close. In fact, it’s remarkably close.

This kind of information is only available in Taiwan. SMIC, based in Shanghai, and Chartered, based in Singapore, don’t report monthly sales numbers.

Nevertheless, there was at least some encouraging news out of Chartered. It said that sales seem to be stabilizing and wafer starts appear to be increasing for Q2. 

There is evidence of this showing up in other parts of the market. U.S. retail sales, excluding big-ticket items like cars, show modest increases in areas like clothes and consumer electronics. Numbers were up in January and February. It certainly wasn’t a robust gain, but it wasn’t negative, either. That will translate into new design starts sometime in the next few months, which barring any more major drops will start this whole cycle rolling again.

Design activity has to begin at least six months prior to any turnaround, which means that if the overall economy is expected to show growth in 2010,  electronic designs have to begin by mid-year—perhaps even sooner.

None of this is perfect, however. Why, for example, did National Semiconductor just announce plans to cut 26% of its workforce? At least part of that can be explained by closing of an assembly and test plant in China and a fab in Texas. Too much capacity is expensive, and we wouldn’t be surprised if National ultimately begins outsourcing some of its work to foundries. Yes, it’s analog, but is it still more efficient to run fabs yourself, even if they’re fully depreciated, when TSMC and UMC are begging for business?

Meanwhile, in the FPGA realm, chip design is getting so complex that EDA vendors are finally beginning to find inroads. This is a market previously owned by tools from the FPGA vendors, which they readily gave away to customers at little or even no cost. That worked fine before the industry got to 90nm, and at 45nm it’s tough enough even with the best of tools.

Mentor introduced its Precision Synthesis Tool family for Altera’s Stratix and Arria families. Our guess is that you can expect to see a lot of activity in this market in the near future, and not just from Mentor. Synopsys’ purchase of Synplicity gives it a vested interest in the FPGA market, as well.

–Ed Sperling