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Blog Review – Monday, April 24, 2017

Monday, April 24th, 2017

This week’s blogs are concerned with AI and intelligent, connected vehicles, sometimes both. There are quests to find the facts behind myths and searches for answers for power management and software security too.

Is an effective tool for verification, the stuff of legends? Gabe Moretti, Chip Design Magazine, seeks the truth behind Pegasus – no, not the winged horse, the more earthly verification engine from Cadence.

A power strategy is one thing, but a free trial adds a new dimension to energy management. Don Dingee, Sonics, elaborates on the company’s plan to bring power to the masses, using hardware IP and ICE-Grain Power architecture.

If you are unsure about USB, Senad Lomigora, ON Semiconductor’s blog should help. It looks at what it’s for, why we can’t get enough of USB Type C, USB 3.1, connectors and re-drivers.

Every vehicle’s ADAS relies on good visuals, observes Jim Harrison, guest blogger, Maxim Integrated, and good connectivity. He looks at the securely connected autonomous car, and then homes in on explained how Maxim Integrated exploits GMSL, an alternative to Ethernet, in its MAX96707 and MAX96708 chips, to create an effective in-car communication network.

Still with the connected car, Pete Decher, Mentor Graphics, is fresh from the Autotech Council meeting in San Jose. The company’s DRS360 Autonomous Driving Platform launch was high on the list of discussion topics, along with the role of artificial intelligence (AI) in the future of driving.

Still with AI, Evens Pan, ARM provides an in-depth blog on Chinese start-up, Peceptin’s enabled embedded deep learning. The case study is fascinating and well reported in this comprehensive essay.

Making any software engineer feel insecure about software security is an everyday occurrence, helping them out is a little more out-of-the-ordinary, so if it refreshing to see a post from the editorial team, Synopsys, letting the put-upon software engineer know there is a webinar coming soon (May 2) to enlighten them on the Building Security In Maturity Model (BSIMM), with a link to register to attend.

Caroline Hayes, Senior Editor

Behold the Intrinsic Value of IP

Monday, March 13th, 2017

By Grant Pierce, CEO

Sonics, Inc.

Editor’s Note [this article was written in response to questions about IP licensing practices.  A follow-up article will be published in the next 24 hours with the title :” Determining a Fair Royalty Value for IP”].


Understanding the intrinsic value of Intellectual Property is like beauty, it is in the eye of the beholder.  The beholder of IP Value is ultimately the user/consumer of that IP – the buyers. Buyers tend to value IP based upon their ability to utilize that IP to create competitive advantage, and therefore higher value for their end product. The IP Value figure above was created to capture this concept.

To be clear, this view is NOT about relative bargaining power between buyer and the supplier of IP – the seller –  that is built on the basis of patents. Mounds of court cases and text books exist that explore the question of patent strength. What I am positing is that viewing IP value as a matter of a buyer’s perception is a useful way to think of the intrinsic value of IP.

Position A on the value chart is a classification of IP that allows little differentiation by the buyer, but is addressing a more elastic market opportunity. This would likely be a Standard IP type that would implement an open standard. IP in this category would likely have multiple sources and therefore competitive pricing.  Although compliance with the standard would be valued by the buyer, the price of the IP itself would be likely lower reflecting its commodity nature. Here, the value might be equated to the cost of internally creating equivalent IP. Since few, if any, buyers in this category would see advantage for making this IP themselves and because there are likely many sellers, the intrinsic value of this IP is determined on a “buy vs buy” basis.  Buyers are going to buy this IP regardless, so they’ll look for the seller with the proposition most favorable to the buyer – which often is just about price.

Position B on the value chart is a classification of IP that allows for differentiation by the buyer, but addresses a more elastic market. IP in this category might be less constrained by standards requirements. It is likely that buyers would implement unique instantiations of this IP type and as a result command some end competitive advantage. Buyers in this category could make this IP themselves, but because there are commercial alternatives, the intrinsic value is determined by applying a “make vs buy” analysis. The value proposition of the sellers of this type of IP often include some important, but soft value propositions (e.g., ease of re-use, time-to-market, esoteric features), the make vs buy determination is highly variable and often buyer-specific. This in part explains the variability of pricing for this type of IP.

Position C on the value chart is a classification of IP that serves a less elastic market and empowers buyers to differentiate through their unique implementations of that IP. This classification of IP supports license fees and larger, more consistent, royalty rates. IP in this category becomes the competitive differentiation that sways large market share to the winning products incorporating that IP. This category supports some of the larger IP companies in the marketplace today. Buyers in this category are not going to make the IP themselves because the cost of development of the product and its ecosystem is too prohibitive and risky. The intrinsic value really comes down to what the seller charges.

This is a “buy vs not make” decision – meaning one either buys the IP or it doesn’t bother to make the product. A unique hallmark of IP in this position is that so long as the seller applies pricing consistently, then all buyers know at the very least that they are not disadvantaged relative to the competition and will continue to buy. Sellers will often give some technology away to encourage long-term lock in. For these reasons, pricing of IP in this space tends to be quite stable. That pricing level must subjectively be below the level that customers begin to perform unnatural acts and explore unusual alternatives.  So long as it does, the price charged probably represents accurately the intrinsic value.

Position D on the value chart is a classification of IP that requires adherence to a standard. Like category A, adherence to the standard does not necessarily allow differentiation to the buyer. The buyer of this category of IP might be required to use this IP in order to gain access to the market itself. Though the lack of end-product differentiation available to the buyer might suggest a lower license fee and/or lower to zero royalty rate, we see a significantly less elastic market for this IP type.

This IP category tends to comprise products adhering to closed and/or proprietary standards. IP products built on such closed and/or proprietary standards have given rise to several significant IP business franchises in the marketplace today. The IP in position D is in part characterized by the need to spend significant time and money to develop, market and maintain (defend) their position, in addition to spending on IP development. For this reason, teasing out the intrinsic value of this IP is not as straightforward as “make vs buy.” Pricing is really viewed more as a tax. So the intrinsic value determination is based on a “Fair Tax” basis. If buyers think the tax is no longer “fair,” for any reason, they will make the move to a different technology.


Position A:  USB, PCI, memory interfaces (Synopsys)

Position B:  Configurable Processors, Analog IP cores (Synopsys, Cadence)

Position C:  General Purpose Processors, Graphics, DSP, NoC, EPU (ARM, Imagination, CEVA, Sonics)

Position D: CDMA, Noise Reduction, DDR (Qualcomm, Dolby, Rambus)

Why Customer Success is Paramount

Sonics is an IP supplier whose products tend to reside in the Type C category. Sonics sets its semiconductor IP pricing as a function of the value of the SoC design/chip that uses the IP. There is a spectrum of value functions for the Sonics IP depending upon the type of chip, complexity of design, target power/performance, expected volume, and other factors. Defining the upper and lower bounds of the value spectrum depends upon an approximation of these factors for each particular chip design and customer.

Royalties are one component of the price of IP and are a way of risk sharing to allow customers to bring their products to market without having to pay the full value of the incorporated IP up front. The benefit being that the creator and supplier of the IP is essentially investing in the overall success of the user’s product by accepting the deferred royalty payment. Sonics views the royalty component of its IP pricing as “customer success fees.”

With its recently introduced EPU technology, Sonics has adopted an IP business model based upon an annual technology access fee and a per power grain usage fee due at chip tapeout. Under this model, customers have unlimited use of the technology to explore power control for as many designs as they want, but only pay for their actual IP usage in a completed design. The tape out fee is calculated based on the number of power grains used in the design on a sliding scale. The more power grains customers use, the more energy saved, and the lower the cost per grain. Using more power grains drives lower energy consumption by the chip – buyers increase the market value of their chips using Sonics’ EPU technology. The bottom line is that Sonics’ IP business model depends on customers successfully completing their designs using Sonics IP.

Blog Review – Monday, February 13, 2017

Monday, February 13th, 2017

Among this week’s topics: two important announcements: the OpenFog Consortium and IEEE Standard for the Functional Verification Language e; a panel discusses the Internet and beyond; Mentor Graphics applies IoT to PCB design; FASTR accelerates the connected car and why USB is not as easy as 123

The importance of IP blocks is a given, but Rocke Acree, ON Semiconductor, explains how selection also has to consider technology and support tools. The company has collaborated with Hexius Semiconductor to qualify analog IP blocks to reduce design cycles and development time.

There are specific constraints, challenges and design requirements for PCBs designed for the burgeoning IoT market. John McMillan, Mentor Graphics has created a two-part blog focused on this topic.

Doing a quickstep around the topic of USB, Eric Huang, Synopsys, explores verification and FPGA prototyping for best results. He recommends some design rules, a test site, then curiously, throws in some political comment, a film review and dance-related jokes to end the blog.

It may not be an understatement by Rhonda Dirvin, ARM, to say that the day the OpenFog Consortium announced its reference architecture is the day we have all been waiting for. Hyperbole? Possibly not, as it defines how secure, interoperable products should be built – just what the connected world needs. She helpfully includes a link to the architecture, and a heads-up on a presentation at Mobile World Congress in Barcelona, Spain (Feb 27 to March 3).

If there is an award for Most Apt Acronym, the Future of Automotive Security Technology Research (FASTR) consortium, must be a contender. The uncredited Rambus blog reviews the brief history of the consortium, and discusses its recent manifesto, looking at why it is need for a secure, connected vehicle industry.

2017 begins with the publication of IEEE Std 1647 2016, the IEEE Standard for the Functional Verification Language e. of 2017. Efrat Shneydor, Cadence Design, looks at the enhancements which have been made and proficiently summarizes the highlights.

Generic connectivity is not enough – NASA has been designing, building and launching satellite systems with the goal of providing connectivity throughout the world. The concept and realities of the Internet of Space is the panel discussion topic, reported by John Blyler, Chip Design Magazine.

Caroline Hayes, Senior Editor

USB Lets Power Go to its Head

Monday, June 17th, 2013

While some USB capabilities haven’t taken off yet, the USB Power Delivery specification is generating plenty of excitement.

USB continues to up the ante, and these days, power management is the way to win the game. Our panel of experts explains the excitement around USB’s recent Power Delivery specification and shifts in the adoption of the USB Battery Charging Specification, which should ease the battle to keep all the devices in our lives charged. And they offer their thoughts on the adoption and issues around other USB initiatives from the Android Open Accessory Protocol to USB On-the-Go and more. Thanks to our roundtable participants for their insight: David Flowers, principal applications engineer, Microchip Technology Inc. and Jesse Lyles, director of applications and marketing, USB and Networking Group, Microchip Technology Inc.; Jack Roan, technical marketing manager, Connectivity Products, Exar; and Derek Fung, COO of Total Phase.

EECatalog: With Android showing up more often in embedded devices, how are developers taking advantage of Android’s Open Accessory protocol for USB peripherals? Are there challenges still to overcome?

David Flowers, Microchip Technology Inc.
Jesse Lyles, Microchip Technology Inc.

David Flowers and Jesse Lyles, Microchip Technology Inc.: Android provides two main ways in which developers can create USB accessories for Android devices. The first method makes the phone/tablet the USB host. The second method, the Android Open Accessory (AOA) protocol, enables phones and tablets without USB host capability to communicate to an accessory. In this mode, the accessory is the USB host and the phone/tablet is the USB peripheral. This mode has the benefit that the phone/tablet can charge from the accessory which is ideal for docking type applications, but not ideal for mobile accessories. One major drawback is that the data in this mode is custom and only the audio out and HID features provided in AOA v2 interact directly with the OS—all other applications need to work in conjunction with an app. Additionally, most phones and tablets tested do not support the USB battery-charging specification completely. They fail to detect the difference between a USB wall charger and a host capable of both communication and high charge rate. As a result, a phone/tablet attached to an AOA accessory may slowly charge or might slowly discharge based on the 500 mA charging current provided while still communicating. If the AOA accessory tries to enter the high charge-rate mode, the communication is not enabled in most cases.

Jack Roan, Exar
Derek Fung, Total Phase

Jack Roan, Exar: We have worked with customers on the Android platform, but haven’t seen a lot of interest or need for the Open Accessory protocol.

Derek Fung, Total Phase: We are not seeing a large uptake. In our brief research, it appears that only one of the top 15 current Android accessories is taking advantage of USB. In our tool business, we’re not seeing a large call for support of decoding of the Android Open Accessory protocol. To the best of our knowledge, no major protocol analyzer manufacturer currently decodes this protocol out-of-the-box.

EECatalog: How are embedded developers taking advantage of USB’s power management capabilities for new designs?

Flowers and Lyles, Microchip: There has been a recent shift in adoption of the USB Battery Charging specification. More USB devices, both host and peripheral, are starting to adopt this specification to enable their system charging needs. This specification allows portable devices to charge at much higher charge rates (up to 1.5A at 5V). USB wall adaptors have become very common and inexpensive. There are also several inexpensive silicon products that designers can use to enable USB charging support for their applications, such as the USB3750 or UCS1001.

Roan, Exar: In my opinion, this is one of the most exciting recent trends with USB. The USB port/plug has already become ubiquitous for 5V DC power delivery: every new smart phone or tablet shipping today includes a USB-based DC charger. You can even get small consumer appliances that are powered via USB, like fans, lights, even humidifiers or a vacuum! Most are novelties, but with the Power Delivery spec (USB PD) expanding USB to include other DC voltages (5V to 20V, up to 100W) we will soon see many more devices using the USB connector just for power.

You can already buy USB wall plates for your home or office that supply 5V DC. Most of the airports that I visit frequently have integrated USB outlets in each seat for charging phones and tablets. The USB PD spec takes this idea even further and defines an intelligent power supply able to reconfigure itself as needed to deliver 5V, 12V, 20V, etc. making USB the de facto standard for any DC voltage, worldwide. Imagine not needing to take a voltage converter when you travel internationally! Imagine charging your laptop from a USB outlet, or plugging your electric razor into a USB outlet in your bathroom; smart DC outlets in our homes, offices and cars.

In my garage I have a large box of AC/DC wall warts from defunct or discarded electronic devices. A flexible DC power supply such as that defined by the USB PD spec renders these all unnecessary. No more wall warts. The worldwide impact of this technology will be huge.

Fung, Total Phase: Overall, this past year we’ve seen an increase in the number of devices aggressively managing power. Whether it is the LTSSM power management for USB 3.0 or link power management for USB 2.0, more device vendors are aggressively placing devices in lower power states. While these technologies specify how a device should enter lower power-consuming modes as a function of bus activity, we see a need in the market for tools that can help developers correlate packet level activity with voltage and current measurements, effectively helping developers transition to a more practical phase in the measurement of power. We are releasing our first tool to help in this space later this summer.

EECatalog: Where is Wireless USB taking hold, and how does it compare with other wireless protocols?

Flowers and Lyles, Microchip: The Wireless USB specification has yet to gain much traction in the market. It was developed after Bluetooth and Wi-Fi had already started to gain traction and has not been able to displace them thus far. Bluetooth is entrenched in the lower bandwidth space (mice, keyboards, audio devices, etc.). Many high bandwidth applications have adopted Wi-Fi (network drives, network printers, etc.). Wireless USB can still fit a need where a user does not want to expose the device to the entire network.

Wireless USB bandwidth is comparable to Wi-Fi and several orders of magnitude faster than Bluetooth in terms of data rate. Wi-Fi and Bluetooth have a comparable maximum distance range of around 100 meters. Wireless USB, however, has a much more limited range of 10 meters.

Roan, Exar: We haven’t seen wireless USB in any applications at this point.

Fung, Total Phase: We still see a dominance of Bluetooth and Wi-Fi, and our sample set is too small for Wireless USB to have a valid comparison.

EECatalog: What’s happening with USB On-The-Go (OTG) and Embedded Host capabilities? Are you seeing greater uptake of these in embedded applications?

Flowers and Lyles, Microchip: The most recent round of phones and tablets are starting to implement host and device capabilities. While these are not OTG compliant, they do use some of the features and intent of the OTG specification. Beyond the phone/tablet market, OTG has limited usage potential for most applications.

Embedded host support is growing in many embedded applications. Devices have started to add a USB host port for boot loading, diagnostics, data logging and user interface. An example application is a treadmill that uses a thumb drive to load workout programs downloaded from the Internet and then log workout data. Embedded host support appears to be limited mostly to the higher end models of the product lines they are used in.

The use of embedded USB has also led to the high-speed inter-chip (HSIC) standard being adopted by many mobile embedded applications for internal communications between chips. HSIC connectivity allows for a lower power and pin-count interface while maintaining the same USB software protocol.

Fung, Total Phase: Over the past year the number of inquiries for our USB tools supporting OTG has held steady, but at a fairly low rate. There does not appear to be an increase or decrease in uptake of OTG for embedded applications.

EECatalog: What does the future hold for USB? Are there any competing technologies that can challenge it?

Flowers and Lyles, Microchip: One of the more interesting recent developments in the USB technology world is the USB Power Delivery specification. USB powering attached peripherals has always been one of the positive points of USB. This specification builds upon this benefit by extending the power limit to up to 100W delivered. It also adds the ability to power the bus at 12V and 20V instead of just 5V, opening a new world of devices that can be powered directly from the USB cable. More information can be found on the USB power delivery website:

Roan, Exar: We’re seeing an increase in usage of USB for chip-to-chip connections—connecting processors and ICs on the same board without going outside the enclosure. USB continues to increase in bandwidth and with only two serial data lines it is very easy to route around a board. We are seeing designers migrating to USB from lower speed chip-to-chip protocols like I2C and SPI, as well as using it to replace proprietary serial or parallel buses.

Fung, Total Phase: For higher data volumes, we’re seeing Thunderbolt as a competitor for USB. USB’s ubiquity is its competitive edge. For lower-speed applications, we’re seeing an increase in wireless protocols to replace USB. For example, for printers, mice and keyboards there is a transition to wireless protocols like Wi-Fi and Bluetooth. USB is facing stiff competition: Thunderbolt from the high-performance side and wireless for the less data-intensive applications.

coupe_cherylCheryl Berglund Coupé is managing editor of Her articles have appeared in EE Times, Electronic Business, Microsoft Embedded Review and Windows Developer’s Journal and she has developed presentations for the Embedded Systems Conference and ICSPAT. She has held a variety of production, technical marketing and writing positions within technology companies and agencies in the Northwest.

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