By John Blyler & Ed Sperling
Is the Electronic Design Automation (EDA) tools market shrinking or growing? That depends greatly upon how you define EDA.

A recent report by the Global Industry Analysts, based on information from EDA Consortium (EDAC), predicts that the global EDA tool market eventually will re-emerge to drive growth to $9.8 Billion by 2015. The report suggests that this growth will be fueled in part by the traditional efforts to improve efficiency and performance throughout the chip development process.

EDA Chip-Level Tools
Aart de Geus, chairman and CEO of Synopsys, expanded upon this finding in a recent interview. “As a percentage of our business, classic EDA is shrinking, but this is not a case of ‘classic EDA doesn’t grow.’” For example, in the past, EDA companies added front-end RTL synthesis and design tools with timing and power closure to improve the productivity of chip designers. Next, efficiencies were found in the back-end of the process by adding physical design with extraction and Design for Manufacturing (DFM) and Yield (DFY) tools. Today, EDA vendors are improving the value of system-level design with architectural tools.

Synopsys is indeed attempting to improve their architecture tool flow with the recent double acquisitions of two electronic-system level (ESL) design companies – VaST and CoWare. The emphasis on architectural integrated circuit (IC) design productivity has pushed traditional EDA chip companies to expand into the next level of product development, namely, package and board design and – on the software side – even application development.

But this time around, productivity and efficiency within the chip development process will not be enough to save EDA. In addition to continuing improvements in both front and back-end tool design, chip-level EDA companies must be successful in reaching outward to embrace new customers and industries.

Perhaps no one understands this shift in thinking better than Mentor Graphics, who has products in the chip, package, board and even embedded real-time operating system (RTOS) markets. “We (EDA chip tools) as an industry are stubbornly targeting a limited number of customers,” said Serge Leef, vice president of new ventures and General Manager of the System-Level Engineering Division at Mentor Graphics. “We really need to figure out where to go beyond that.”

There are four choices, according to Leef. One is to sell products to existing customers, which EDA companies will continue to do. The second is to sell new products to existing customers, which they are attempting in areas such as submicron design, DFM and yield enhancement. A third option is to sell existing products to new customers in places like China and India, but most of those companies are either part of multinational companies that already buy EDA tools or they’re underfunded startups that cannot afford tools. A fourth option is to sell new products to new customers.

On paper, the last option seems the most promising. The problem is getting the new customers to look at what EDA has to offer, which means that EDA companies must understand the needs of the new customers – i.e., different industries.

IP Drives Profit
A universal need shared by most new customers in today’s economically challenged markets is that of cost reduction. This has two effects. One is to increase the use of intellectual property (IP) blocks in chip-level design while the other is to move from ASIC to FPGA-based designs.

Increasing the use of IP was a primary theme in Virage Logic’s keynote address at the recent DesignCon show. That was expected, but the arguments that were used to support the growth of IP are worth noting. Brani Buric, executive vice president for marketing and sales at Virage, explained it this way: “As we move into consumer markets with low profit margins we must think beyond the technical challenges to the business issues. The question is not just how to do the design more efficiently in terms of cost, but whether to do the design at all.”

The business focus of this approach is reflected in its name, i.e., Design for Profitability (DFP). Companies focusing on profit might just write the spec for a new chip, then hand off the rest of the design and implementation to design companies such as eSilicon or Open-Silicon. Owning the spec would typically be a lot less expensive than owning any part of the implementation process. This approach relies heavily on IP blocks to build the chip to spec.

Interestingly, the growth of IP is one of the key drivers cited by in the Global Industry Analysts report for overall EDA growth. The reason that EDA tool revenues are expected to climb in 2015 is because EDA owns IP. By including Broadcom, Qualcomm and ARM as some of the largest IP licensing companies, EDA will indeed be one of the fastest growing sectors—at least on paper. The reasoning for this inclusion, according to EDAC, is that EDA tools are an integral part of licensing the IP, so IP licensing revenues should be counted in the EDA business calculations.

EDA in the Board-Level Market
The growing reliance on FPGA-based electronics is the second trend driven by profit-focused designs. But this is another area where companies like Actel, Xilinx and Altium are trying to engage a broader customer base, e.g., medical, industrial and automotive markets.

Actel’s purchase of Pigeon Point moves that company squarely into the Advanced TCA and MicroTCA world, which has been heavily utilized by communications companies and defense. Xilinx, meanwhile, is positioning its next-generation 28nm FPGA platform to help win business in non-traditional markets. And Altium has been focusing on a single database implementation of FPGA-based, board-level products that include embedded software development.

While all of these expansions reflect broader changes in the overall semiconductor industry, real growth in the EDA sector can only come from expansion beyond traditional markets. But there will always be a nagging question facing EDA companies moving into these new markets: Is this really EDA, or are we venturing into a new sector that reaches well beyond the confines of EDA to include a true system-level approach?

By Ed Sperling
Throughout system-level design there are gaps. High-level modeling doesn’t connect directly to RTL code. Synthesis and high-level synthesis remain worlds apart. There are even gaps in the expertise, from the people who handcraft RTL to those who take it for granted.

Some of these gaps will get closed over time. Others will never be closed. In same cases it doesn’t matter. In other, it adds inefficiency into the flow. Gaps can result in errors, they can delay designs, and they can cost money.

“There is always a gap between those two stages,” said Serge Leef, vice president of new ventures and general manager of Mentor Graphics’ System-Level Engineering Division. “There is no implementation path from ESL onward. In fact, the two worlds are barely connected. People who do system-level modeling are basically done because the benefits of that system model are not connected to implementation. Test benches become the ‘bridges’ between the two worlds.”

Leef said that what is missing is true system synthesis. Right now engineers work with synthesized blocks or even pieces of blocks, but it takes far too long and too many cycles to synthesize an entire SoC.

“There are too many dimensions to optimization,” he said. “Add software and the number of optimization knobs is vast. Also, there’s no really good language for synthesis that addresses concurrency, timing and pre-emption. SystemC, which is the best we’ve got, is really a hardware modeling language. On the software side there are C and C++, and lately there’s been a push toward UML and SysML. But there is no single language that does everything.”

System prototyping
Industry consultant Gary Smith said the one critical piece that has been missing in ESL-based design is virtual prototyping.

“That’s the only way we’re going to be able to fix the flow and get the cost of the design down and get simulation,” said Smith. “We need RTL handoff.”

One of the key pieces in this puzzle is software prototyping. Both Intel and Synopsys have been on an acquisition spree in this part of the market lately, grabbing most of the startups. Smith said the prototyping has to be radically faster, though, for it to have a real impact on design—something in the neighborhood of 100MHz.

The second missing piece is virtual prototyping for hardware. Both Atrenta and Cadence are known to be working on this problem, and sources say all the major players are exploring this market.

But Aart de Geus, Synopsys chairman and CEO, said all the pieces may never come together. “There will always be different levels of abstraction,” de Geus said. “The benefit of one level is not the same as another level, and you need success on all levels of abstraction. There will always be a tradeoff between efficiency and quality of design.”

He noted that there is a big difference between systemic complexity and the scale complexity inherent in Moore’s Law. “The opportunity is to keep scale complexity going while dealing with systemic complexity.”

Alex Shubat, president and CEO of Virage Logic, said the future may be in integrating the supply chain rather than the individual pieces of technology.

“Everyone has a center of excellence,” Shubat said. “The key is to make sure you can integrate up and down. No one company spans the whole world. The bigger the vertical stacks, the greater the efficiency. If it all works smoothly, you should be able to get to tapeout in half the time.”

Unexpected winners
That has paid off for IP vendors, who provide some of the pieces. It has created new opportunities in other areas. For example, the disconnect between the high-level modeling tools and the engineers who like to see exactly what is going into synthesis has opened the market for tools that can dig down into the code and analyze it. Mike Gianfagna, Atrenta’s vice president of marketing, said his company discovered that somewhat accidentally when chip developers began using Atrenta’s SpyGlass exactly for that purpose. It was an unexpected win for the company, considering SpyGlass was created to analyze RTL.

“There are a completely different set of things that each of these groups care about,” said Gianfagna. “With high-level synthesis you get machine-generated RTL, but you generally don’t know what the machine generated. Then you’ve got the other side of the engineering world where they handcraft RTL. They want to know what’s in the RTL, but the machine-generated RTL from high-level synthesis is not all that well documented.”

The result is that not everything can be optimized effectively without that level of granularity. But at the same time that higher level of abstraction is essential just to get the analysis done. Every time a team of engineers wants to do synthesis place and route it can take the better part of a week. Both speed and automation are essential, but it has to be linked back to the RTL side.

By Ed Sperling

The acquisitions continue. Mentor Graphics acquired Freescale’s Virtual Garage optimization and analysis technology, expanding its reach into automotive electronic design. Consider this an interesting way for Mentor to leverage its design expertise in adjacent markets.

Synopsys reported revenue of $330.2 million in fiscal Q1, down about $9.6 million from the same quarter in 2009. Profit was $132.8 million, but that included an extraordinary one-time gain of $91.6 million from a tax settlement with the IRS. Still, the company surpassed analyst expectations, and numbers are expected to be as good or better in the current fiscal Q2.

Mentor announced it was making its embedded Inflexion user interface available for the Android mobile platform using TI’s OMAP environment. Mentor made the announcement at Mobile World Congress in Barcelona, Spain.

Virage Logic teamed up with Open-Silicon to create an ultra low-power design that combines Virage’s low-power memories with Open-Silicon’s back-biasing technology.

Arasan signed onto Atrenta’s clean IP program, aka SpyLinks, which is yet another link in the chain of providing IP that actually works. This has become critical ever since the major foundries, TSMC and the Common Platform group began rating IP to make sure it works and can be manufactured.

By Ed Sperling

Money is flowing again. Sometimes into companies, sometimes out of companies. But at least it’s moving.

Synopsys bought VaST Systems for an unknown price, but it doesn’t appear it was a vast amount of money. Synopsys said it didn’t materially affect its numbers, which means it fell well below the radar screen. Apparently it’s tough to break into the software prototyping market without serious integration with other tools in a flow. This builds on Synopsys’ acquisition of Virtio in 2006.

Virage Logic’s revenue for Q1 of its fiscal 2010 was $21.7 million, up from $11.3 million in the same quarter in 2009 and $13.1 million in Q4. The company reported a loss for the quarter of $2.2 million, but that loss reflects the costs of recent acquisitions. Minus those charges, profit would have been $900,000. More significant for Virage, royalty income for Q1 was $4.7 million vs. $2.8 million in the same period in 2009, a sign that companies are building chips again and licensing IP to get to market more quickly.

Actel posted a profit in Q4 2009 vs. the same period in 2008, despite a drop in overall revenue. Net income was $1 million in the quarter, vs. a loss of $12.5 million during the same period in 2008. Revenue was $49.7 million in Q4 2009, down 5.8% from 2008, but up 5.2% from Q3 2009. For the full fiscal year revenue was $190.6 million, down 12.7% from fiscal 2008. The company expects revenues in the current quarter to rise 2% to 6% compared to Q4.

Actel also announced that its president and CEO, John East, would step down once a replacement is found. East, who is 65 years old, will continue serve as a consultant through August 2011, after which he will retire. He has led the company for the past two decades.

Things were modestly upbeat at Cadence for the first time in months. The company reported financial results for Q4 and fiscal year 2009. In Q4 revenues slipped to $220 million vs. $227 million in 2008, but net income was $2 million vs. a loss of $1.63 billion (!) in the same period in 2008. It must be nice to write in black ink again. The Q4 2008 loss included a $1.36 billion “impairment charge.” For the 12 months, revenue was $853 in 2009 vs. $1.04 billion in 2008. Net loss for 2009 was $150 million vs. $1.86 billion including that one-time charge (or $500 million without that charge).

The bottom line—the worst is over. Traffic on Silicon Valley roads is up, and attendance at DesignCon this week was strong. Next comes the jobs.

By Ed Sperling

Every now and then a new trend comes along in the semiconductor design world, often because an old tool doesn’t work well anymore or because a new one is achieving critical mass. Lithography moved to immersion when the wavelength couldn’t be refracted far enough anymore. Designers at the advanced end of Moore’s Law began using tools like high-level synthesis and Transaction-Level Modeling 2.0 to help sort out the complexities of multicore, multi-voltage, multi-power island designs.

What’s changing at 32nm and beyond is the number of different directions the industry is heading. In the past, each new node brought new changes. At 130nm, the changes were considered extremely difficult because manufacturing moved from 200mm to 300mm wafers, added copper interconnects and low-k dielectrics for insulation. Most developers and chipmakers heaved a sigh of relief when that transition was over. But in retrospect, that was relatively tame.

Interviews with dozens of engineers, vendors, scientists, researchers and business managers over the past six months show that what’s ahead cannot be bounded into just one or two shifts. The change under way now is geographically global. It’s moving to a higher and higher level of abstraction, from semiconductor to system to device. And it is as much driven by business as technology. Moreover, taken in total these changes will completely alter the basic fabric of the design community in ways that have never been seen before.

Business
Behind many of the changes afoot in the market there is always a business case. In the past, technology trumped business. Those with steely nerve and enough backing could often carve out a space for themselves in markets, and even if they weren’t entirely successful they could minimize their losses.

Three things changed over the past decade to alter this approach. Business now trumps technology in almost all cases. First, the venture community has grown more cautious about the rate of return in hardware and EDA tools ever since the dot-com bubble burst in 2001. It’s not possible to return to the tap anymore without a real product and a real business model.

Second, the cost of failure has gone up. It now costs $4 billion to $5 billion to build a state-of-the-art fab. Consortiums of very large companies and governments are now involved in this business. And it can cost upwards of $100 million to build a very complex SoC at the latest process node. Stalwart adherents to Moore’s Law such as Freescale, which made the leap to the next process node without hesitation until 90nm, have begun skipping nodes on certain products.

Third, chips are now so complicated that it takes too long to build everything from scratch. That means chipmakers must buy IP from third parties. Even Intel doesn’t make everything itself anymore. And all but a very few companies now use a fabless or fab-lite model for at least the digital portion of their chips, which forces them to adhere to design rules and process technology developed by the foundries.

Put these together and the result is that business issues are forcing a handoff of some of the most basic parts of semiconductor engineering—defining a unique architecture, tinkering with the layout, refining the process, and balancing all of these pieces together at tape-out. Fast yield, time to market and standardized interconnects and IP are no longer just goals. They are requirements. Some companies have handed off the building of chips entirely to a new class of value-chain producers like eSilicon, Global Unichip and Open-Silicon.

Globalization
For the first 50 years of its existence, the semiconductor industry defined global as North America, Europe and Japan. Taiwan was a latecomer to the part, and TSMC’s vision of a foundry model was considered revolutionary well into the 1990s. Companies like Texas Instruments and AMD said they had no intention of letting go of their own fabs.

Fast forward through two downturns and 10 process nodes and the situation now looks much different. Software is increasingly a part of the design process, heavily automated foundries can be located anywhere in the world where tax breaks and the cost of power are lowest, and massive education programs are under way in multiple countries that see semiconductor and computer engineering as a fast way to economic health.

While many lament that the semiconductor industry is declining or not showing growth, the opposite is happening. It’s expanding significantly. In 1977, the Semiconductor Industry Association reported total semiconductor sales of $2.88 billion, with about $1.92 billion of that in the Americas and only $182 million in Asia/Pacific (not including Japan). In the first 11 months of 2009, sales were $196 billion worldwide, with $102 billion in Asia/Pacific and $33 billion in the Americas.

By any standard this represents an enormous increase in sales, but the profits are now far more dispersed around the globe. Moreover, IP for chips is being developed in places like Eastern Europe and former Soviet republics, and in the future that kind of work will accelerate in other parts of the world because the barrier to entry into this market is one of the lowest—you don’t need to build full systems—while the return on investment is one of the highest. Virage Logic, ARM and Synopsys have been snapping up these kinds of operations around the globe over the past couple years.

Technology
Most of these changes are being driven by the technology itself. There are fewer design starts for ASICs these days, but the problems being solved are far more numerous on each chip than in the past. The tradeoffs of area, power and performance have been relatively balanced over decades of development. When lithography became an issue, there was enough slack in power and performance to tide chip designers over until the next node.

At 90nm that began to change. Classical scaling ended, lithography stalled at 193nm, defect density increased as irregularities in silicon and process technology became evident. Power forced even companies like Intel to begin adding more cores onto a chip rather than continuing to turn up the clock speed, creating problems about what to do with more and more cores.

At 22/20 nm—the next node for companies that live on the edge of Moore’s Law—things get even more interesting. Both Synopsys and Mentor Graphics predict that FinFETS will start showing up on chips—3D transistor structures that will wreak havoc on parasitic extraction because of the amount of data that will now need to be analyzed and synthesized. IBM has talked about potentially reducing the functionality on chips at future nodes to be able to get chips out the door that fit into the power budget.

All major chip companies are now looking at heterogeneous cores instead of homogeneous cores and matching software and core size for a specific function. IBM and Mentor are experimenting with computational scaling to compensate for the limits of 193nm lithography. And power techniques that used to be considered exotic and extraneous are suddenly becoming necessary.

Even substrates are changing. Intel, which examined and then rejected partially depleted silicon on insulator (SOI) is looking seriously at fully depleted SOI for future nodes. And work is under way to sidestep much of this entirely with 3D stacking of chips, which have many problems such as heat dissipation and parasitic issues still not fully understood.

Abstraction
Perhaps even more daunting in this whole process is a complete shift in control within the design flow. The number of computations necessary at advanced nodes, coupled with business pressures and time to market issues are forcing engineers to rely on models. For many, this is like black-box technology. You put requirements in one side and the software adds a lot of the things in between.

For engineers who learned to solve problems the hard way–that is, without software models–this is perhaps the toughest change of all. RTL engineers who work at big chipmakers say there is enough work at the moment to stick with their core competencies. The problem is the amount of data they are dealing with is going up, and over the next few years it will skyrocket into the stratosphere.

Japan has been particularly accepting of tools like TLM 2.0, high-level synthesis from companies like Mentor, Forte Design Systems and Synopsys, and network-on-chip technology from companies like Arteris and Sonics. The acceptance level in Europe is lower, and it has been lower still in North America. But that is likely to change at future process nodes as business pressures take root, something that is already becoming evident with the rapid proliferation of DFM tools and automated test suites.

Tools vendors characterize these changes as a shift from design engineer to systems engineer. But there’s far more to it than that. In the future, a systems architect will have to understand how the software will behave in the system they’re designing and how all pieces of the verification can be matched to the progress in the design. The next phase of systems engineering will be concurrency in multiple pieces of the design, with real-time feedback across the flow to make a series of modifications and more modifications until tape-out.

This is already evident in the number of tools players around the fringes that are trying to solve unusual problems–companies like Atrenta, Jasper, Oasys, CoWare, and a slew of others that have made inroads and will continue to make inroads.

Conclusion
Taken as a whole, the confluence of a variety of factors ranging from technology to tools to business is coming to a head. Each node from here gets tougher not because one problem has to be solved, but because more and more problems have to be solved simultaneously at each successive node.

Moore’s Law will continue, but not in the form in which it was originally conceived. A FinFET is not a classic transistor, and 3D stacking moves things into a different plane. Moreover, the tools to create these new devices will continue to change, the way they are manufactured will change, and the skills necessary to create these structures will change.

Perhaps even more important, all of these changes will begin showing up over the next couple of process nodes. We are all living and working in interesting times, but whether it’s a blessing or a curse may depend on each engineer’s role, their training, their ability to accept change and possibly even where they’re located

It must be time to solve those pesky I/O issues no one got around to fixing last year. Mentor Graphics introduced a hardware-assisted solution for USB 2.0 verification called iSolve, which works with a variety of emulators. Cut the wait time wherever you can.

And Synopsys uncorked a couple new products for USB 3.0. One is a DesignWare protocol analyzer for verifying USB 3.0-based designs. It also introduced USB 3.0 models for TLM 2.0.

Virage Logic set up an R&D center of excellence in the Netherlands. This builds on the rather complex deal Virage inked with NXP last year. Note the analog business unit, which plays heavily into Virage’s ARC acquisition.

GlobalFoundries completed its acquisition of Chartered Semiconductor. It now owns two 300mm fabs and is building a third in New York State. The bottom line: It’s now down to the Common Platform (GlobalFoundries included) vs. TSMC at advanced nodes in the merchant foundry business. Watch out for falling shrapnel.

Speaking of TSMC, the foundry is developing its 28nm process technology with Qualcomm. Most process folks think 28nm is an evolution, but 20nm starts getting really tricky. This may be a good time to start reading up on FinFETs, air gap insulation, self-assembling components and new substrate materials like graphene. They’ll be filed in the science fiction section.

Intel seems to be doing okay these days. Its fourth-quarter income jumped 875%. No, that is not a typo. Revenue was up 28% year over year. And while the computer market pull-through isn’t what it used to be for electronics companies, it certainly can’t hurt.

By Ed Sperling

The new year is off to a gallop, which either means the economy is recovering or everyone took the holidays off and now they’re playing catch-up.

There were a barrage of press releases over the past week. While individually they look like the usual marketing, collectively they tell a different story—and probably the first really positive one since the downturn hit. Business is up, design activity is up, and executives are back to pitching financial success to Wall Street.

Virage Logic signed a partnership deal with eSilicon to become an IP partner in eSilicon’s value chain. Virage also inked a deal to provide its Sonic Focus software on IDT’s codecs for PCs. and another deal to license its ARC processor cores to Phison, which makes USB drives and memory controllers.

Canon is migrating its India Design Centre to OVM and is using Mentor’s Questa verification platform. Business is healthy in Asia.

Top execs are back on the road again doing more than just sales calls, too. CEOs from Synopsys (Aart de Geus) and Actel (John East) will be presenting at the Needham conference in New York next week.

And electronics companies began talking up the products that are running their latest technology at CES. ARM is showcasing its Cortex-A9 processor in an NXP set-top box  while MIPS is showcasing its cores in set-top boxes running Android.

Even jobs are beginning to return to the market, according to job boards. Some of this work is still on a consulting basis, but it’s at least a first step toward a broader recovery. Welcome to 2010.

By Ed Sperling

Virage Logic wasted no time in putting its ARC acquisition to work. As soon as the ink dried for the deal, Virage opened fire on ARM. Virage’s new 32-bit processor core, aka the ARC 601, is aimed squarely at ARM’s Cortex M0 microcontroller. With the lines already blurred between microprocessors and microcontrollers this should prove to be an interesting slugfest. What’s especially interesting about this new ARC core is that it’s the same size as an 8-bit microcontroller.

At least ARM is getting a reprieve from Intel’s laser-like focus. With the Federal Trade Commission hammering Intel, this time for including graphics on its processors, the company is facing battles on all fronts—Europe, Korea, Japan and now the United States, it has to be a major distraction. How many other big markets are there? Intel did take the unusual step of responding to the FTC with a statement. It said the FTC jumped the gun and filed before it knew the facts.

Meanwhile, the other half of the dynamic duo, Microsoft, settled its dispute with the EU. Microsoft will now offer multiple browsers to customers. Does anyone still care about which browser gets used? A more pertinent question is whether they can take advantage of more than one core for searches and video playback.

Mentor Graphics achieved IPv6 phase II compliance for its Nucleus operating system. IPv4 is predicted to run out of address space in 2010, which happily was never mentioned in the Mayan calendar. Still, this is a good move for Mentor. We’re taking odds on whether there will be some hiccups in the transition of the Internet, though.

X-Fab, a major analog/mixed signal foundry in Germany, is backing Synopsys’ Galaxy custom installation solution. Analog and mixed signal continues to be a slow and tedious process, in part because analog engineers don’t put a lot of trust in automated tools. Anyone trying to push tools into this market needs a lot of patience and staying power.

TSMC introduced process technology for LED driver devices. This stuff goes all the way back to .6 micron, which is 600nm and as far forward as 180nm. Guess they found a good use for all that fully depreciated equipment.

Chartered Semi, meanwhile, won two investor relations awards in Asia. This is interesting because Chartered has been dead silent since early September, when Abu Dhabi’s ATIC offered to buy the company.

By Ed Sperling

It was the best of times and it was the worst of times, but for EDA it was primarily the latter. And just how bad depended on whether you looked at the world from a GAAP (generally accepted accounting principles) perspective or a non-GAAP approach.

Mentor Graphics reported $189 million in revenue for fiscal Q3, ended Oct. 31, compared with $185 million in the same period in 2008. Non-GAAP earnings were 5 cents a share vs. a GAAP loss of 28 cents. Mentor said sales were up for test, place and route and DFM, and that the outlook for fiscal Q4, which ends Jan. 31, is about $220 million in revenue with non-GAAP earnings of 44 cents per share and GAAP earnings of 33 cents per share. For fiscal 2010 the company expects revenue to increase 1% from fiscal 2009 to $795 million.

Synopsys, meanwhile, posted revenue of $338 million for its fiscal Q4, also ended Oct. 31, compared with $353 million in the same period last year. On a GAAP basis, it showed a profit of 13 cents a share, while on a non-GAAP basis it was $1.75 per share—up slightly from 2008. Revenue targets for the quarter ending Jan. 31 are between $325 million and $333 million.

Cadence, whose Q3 ended on Sept. 30, reported revenue of $216 million compared with $232 million in 2008. On a non-GAAP basis, earnings were 3 cents a share, while on a GAAP basis the company lost 5 cents per share. And Magma, which seems to have overcome its near-death experience (at least as far as its auditors predicted), posted revenue of $30 million for its fiscal Q2, ended Nov. 1, with GAAP earnings of 9 cents a share compared with a loss last year of 60 cents a share. Non-GAAP earnings were 3 cents a share.

The picture presented by all the large EDA players is relatively flat, which is far better than in many other sectors. The companies that have done best—and the product areas within these companies that have fared best—are in areas where there is the most pain in the SoC development process. Private companies with tools that help reduce some of the complexity say they have been seeing solid growth throughout the past couple quarters.

On the non-financial side, Virage Logic shifted gears somewhat with its acquisition of ARC, moving into adaptive volume software, which keeps a consistent volume on computers and handsets. The feature is similar to what is offered by some television makers to keep the volume of commercials at the same level as regular programming. But while there are standards on television, there are none for other devices.

Atrenta won a deal with the Semiconductor Technology Academic Research Center (STARC) to integrate its constraints SDC equivalence verification into STARC’s production flow. Early design closure becomes more important at each new process node.

Intel stepped up its pressure on ARM, rolling out a developer kit for future netbook applications based upon its Atom processor. For the past couple months Intel has been making vague mention of an applications store to go along with the Atom, beginning next year, starting first with netbooks and then extending beyond netbooks to mobile devices such as smart phones and mobile Internet devices. Vendors will have their own storefronts in this mega department store, but how that works and whether it will be successful remains to be seen. Nevertheless, it wouldn’t be the first time a company stole a good idea from Apple and made a bundle off it.

TSMC is jumping into the automotive-grade semi world with a fab in Shanghai. While that may seem rather odd for TSMC—Taiwan Semiconductor Manufacturing Corp.—it’s a tacit recognition of where the majority of cars will be built and sold over the next decade.

Actel extended its popular 8051 core into the world of high-reliability aerospace applications, where cosmic radiation can wreak all sorts of havoc on chips. The big advantage of the strategy is that it leverages a much broader ecosystem than is normally available for military applications.

By Ed Sperling

Test has emerged as a hotly contested market in the mainstream of SoC design rather than living somewhere out on the fringe between verification and tapeout.

What’s unusual is just how quickly this seems to have happened. While it is being driven by a confluence of growing time-to-market pressures, increasing complexity and the link between test and yield, these are not new factors. But they are growing worse at 32nm and beyond, so anything that can be done to reduce time at the back end of the design—the proverbial 50% to 70% of the non-recurring engineering costs—is considered a welcome change for chip companies.

Both Virage Logic and Mentor Graphics are poised for a slugfest in this sector. Virage this week rolled out a Silicon Browser for its self-test and repair (STAR) memory system, for post-silicon bring-up, system debug and embedded memory characterization. That comes on the heels of Mentor’s introduction earlier this month of its Tessent platform, which combines both test and yield with greater compression.

Both Virage and Mentor say they can pinpoint bugs much better with the new test approaches, which take advantage of advancements in compression and processing power that years ago would have been relegated to the world of a supercomputer. What gets really interesting about both of these approaches, though, is just how integrated test has become in the design process. Both companies have built it deep into their product lines.

“At 0.18 and 0.13 (microns), discovering manufacturing errors was shorts and opens, which are relatively benign,” said Brani Buric, vice president of marketing and strategic foundry relationships at Virage. “At 65nm, 40nm and beyond, these manufacturing problems are not trivial. To test, you need to significantly increase the number of test algorithms.”

Along those same lines, Joseph Sawicki, vice president and general manager of Mentor’s Design to Silicon Division, said compression will need to increase 1,200 times. “Just to do a defect test, you have to increase the number of test vectors. We need to accelerate the number of test vectors.”

In simple terms, both companies see an explosion of data, pain for chip developers, and profit in reducing that pain. But they also see it further up in the system-level design process than in the past and integrated with other pieces of the flow, which marks a significant shift.