Mentor Graphics teamed up with National Instruments to create a test-oriented feedback process for designers. NI has been working around the edges of SoC design for some time with its LabVIEW software. The combination of LabVIEW and Mentor’s SystemVision SVX client means that NI is now firmly in the EDA business with a test-as-you-proceed approach.

Synopsys will deliver high-performance audio IP for 40nm and 55nm process nodes. This gets particularly interesting given the company’s announced purchase of Virage Logic, which now owns the ARC processor and all the associated codecs. ARC specializes in the high-end audio market, as well.

Synopsys also joined forces with GlobalFoundries to develop PHY IP for 28nm SoCs. The two companies had a similar agreement for DesignWare Interface PHY IP from 32nm all the way back to 180nm.

Cadence realigned its workforce around its EDA360 vision, focusing the company’s R&D around system, SoC and silicon realization. The system and SoC realization R&D will be led by Nimish Modi, while the silicon realization will fall under Chi-Ping Hsu. John Bruggeman’s marketing organization also will be tightly integrated with the new R&D groups. Given the company’s push into this new software- and IP-driven strategy, this should come as no surprise.

Cadence also adjusted its Q2 results, showing GAAP net income of $49 million, compared with a net loss of $74 million in Q2 2009. Revenue was $227 million for the quarter compared with $210 million in 2009.

Apache Design Solutions reported record bookings and revenue for Q2. The company said growth came from multiple new customers across broad market segments, while achieving 100% renewal from existing customers.

In the IP world, ARM’s revenue shot up 42% to $150.3 million, compared with $105.5 million in Q2 2009. Net cash generated was $30.4 million vs. $11.9 million in 2009. Profit before tax rose 167%.

MIPS likewise reported a stellar quarter. Revenue for the fourth fiscal quarter, ended June 30, was $23.3 million, up 33% over the prior quarter and up 85% from the same period in 2009. Net income was $5.7 million vs. $3.1 million in Q3 and $2.7 million in Q4 2009.

Actel signed up design services provider Axelsys as a partner. Axelsys, based in Fremont and Shanghai, is focused on a broad array of markets ranging from consumer electronics to defense and scientific applications.

And finally, on a sad note, Virage Logic executive VP Brani Buric passed away following a short illness. Buric helped build Virage into the IP powerhouse it has become, betting heavily on IP’s future before it was recognized by the rest of the industry. He will be remembered by the many lucky enough to work with him.

By Ed Sperling
Mentor Graphics filed an import suspension application against Eve in Japan, one of the biggest markets for emulation, on the basis of patent infringement. Eve is one of Mentor’s biggest competitors in that market, too.

The Synopsys acquisition of Virage Logic moved one step closer to reality this week when the 30-day waiting period expired. Under the terms of the deal, Synopsys will pay $12 a share for Virage common stock. Considering that Virage’s stock was hovering around $5.50 at the beginning of the year, that’s a big bump. The stock has been on a steady rise up to agreed upon share price since then.

The deal will be particularly interesting for Synopsys in light of Virage Logic’s agreement with SMIC to extend its partnership to the 40nm low leakage process technology. For anyone who thought the Chinese foundries were trailing well behind Taiwan and the GlobalFoundries, think again.

ARM struck up a bunch of deals with EDA companies and foundries this week. The deal with Cadence calls for an ARM-optimized system-realization solution that includes an end-to-end flow, interoperable tools, and ARMs’ processor, physical IP, services and methodology from embedded Linux to GDSII. ARM also struck a long-term agreement with TSMC to provide its processors and physical IP down to 20nm.

Cadence also struck several deals with Fujitsu, one for a standardized die model that provides a comprehensive chip-package-board co-design solution, , one for chip planning technology, and one for the Cadence Encounter Conformal ECO designer.

By Ed Sperling
As usual, the semiconductor industry slowed to a crawl following DAC. This year, it was especially slow because it abutted the July 4 holiday, which is celebrated with outdoor barbecues and fireworks in the United States and completely ignored by the British, who apparently don’t appreciate barbecues nearly as much as they do in the U.S.

Mentor Graphics adopted a shareholders’ rights plan, ostensibly in reaction to corporate raider Carl Icahn’s move to buy up Mentor stock. Commonly known as a “poison pill,” the plan makes it much tougher for anyone or any company to buy Mentor without the board’s approval. The plan calls for one incentive stock purchase right to be distributed for each shareholder of record at the close of business on July 6. Icahn now owns 10.84% of the company, according to the SEC.

Virage Logic rolled out its first IP product offering based upon its acquisition of NXP’s IP unit, this one focused on processor peripherals. Virage expects to continue rolling out products based on that acquisition throughout the year.

Cadence inked a deal with Silicon Integrated Systems, which adopted Encounter for its design-to-signoff exploration of power-saving strategies.

By Ed Sperling
The EDA and IP blogosphere seems to be in recovery mode after DAC, trying to digest a barrage of ideas that was interesting and compelling despite a falloff in attendance. The good news is that DAC is in San Francisco for the next four years, which means attendance likely will rise again, but that doesn’t mean the number of post-DAC blogs will increase.

Despite all the talk about the functional verification world moving to UVM from OVM and VMM, there apparently is another side to this story. For one thing, Synopsys is not abandoning VMM. The new wrinkle is that Mentor and Cadence are not abandoning OVM. Check out the blog from Mentor’s Mark Glasser. It’s a good one.

Cadence’s Tom Anderson, the other half of the OVM team, had a similar perspective. So why is the OVM side suddenly trumpeting OVM rather than UVM?

Synopsys’ Navraj Nandra talks about one vendor’s impact on Serial ATA interface standards. Needless to say, it’s a pretty big impact.

eSilicon’s Jack Harding looks at what the combination of Synopsys and Virage Logic means and what’s next. He asks an interesting question, too, for which there may not be a single answer.

Cadence’s Richard Goering looks at which language is best for high-level synthesis from a panel on the last day of DAC. It’s an interesting discussion.

What’s it like to be an embedded software expert in an EDA company? Until recently you’d have to wonder why you were hired, but Mentor’s Colin Walls says that’s changing rapidly.

Cadence’s Rahul Deokar calls DAC a “coming out” party for 3D IC design. He may be right, but the technology still has a long way to go before it hits the mainstream. The bulk of the work has been done behind closed doors and is considered a competitive advantage by the leading semi companies.

After DAC, it’s back to work. Paradigm Works’ Ambar Sarkar, writing in Synopsys’ VMM Central, talks about setting options for VMM 1.2.

And finally, but certainly not least, Mentor’s Jon McDonald says the tide is turning on ESL. The proof? The questions are changing.

By Ed Sperling
The rapid consolidation of the IP business is raising big questions about who will be left, whether new companies will join, and what it means for chipmakers looking to buy IP.

In a period of one month Synopsys bought Virage Logic, which had just finished a buying spree of its own with the acquisitions of ARC and the IP business of NXP, and Cadence bought Denali. So what exactly does this mean for chipmakers? There are fundamental questions that need to be answered to fully understand this market.

Why do companies choose one vendor’s IP over another? The answer to this question is more driven by performance, power, cost and ecosystems than it is by who develops the IP. Processor IP cores from ARM, for example, are dominant in the broad smart phone world because of the ecosystem of embedded and other software surrounding it. MIPS is more associated with the burgeoning Android market and specific industrial and commercial applications. And ARC has developed strong ties in the audio world.

“If you pick a problem to solve and develop a complete solution you can solve a customer’s problem,” said Mark Throndson, director of marketing at MIPS. “Virage/ARC has focused very vertically on problems and been successful with that. When it comes to ARM and MIPS you have to go into the nuts and bolts of RTL and our coherent multicore vs. the ARM Cortex A9. It’s architecture vs. architecture, the whole software stack and the marketing side.”

The decisions reach deeper into the ecosystem than just the IP vendor, though. Foundries certify based upon manufacturability, and both the Common Platform and TSMC have their own programs. Within each category there are at least two vendors whose IP has been certified, said Dan Kochpatcharin, deputy director of IP portfolio marketing at TSMC. “We have about 40 companies in our IP alliance,” he said. “We don’t pick and choose the IP. That’s up to our customers. But we do have a service that qualifies it.”

It also adds another check point for IP. In addition to price, performance, power, interoperability, ecosystem partners and licensing arrangements, you have to be sure it can be manufactured.

“We recently sponsored a perception audit to evaluate what customers consider important from both a business and a technical perspective when choosing standards-based IP,” said John Koeter, vice president of marketing for Synopsys’ Solutions Group. “From a technical perspective the most important criteria by far is that the IP has passed compliance and is certified. For standards-based IP cores such as USB and PCI Express, this gives designers confidence that the IP is functioning precisely to the specification and interoperable with other products in the market. An IP vendor’s engineering knowledge and having IP in volume production are the second and third most important aspects, respectively. Having engineering expertise gives customers assurance that there will be someone who has the technical know-how to address their issues whenever needed. IP that is in volume production means that the IP has been widely used and deployed, which lowers their integration risk.”

He noted that from a business perspective the top three factors are responsiveness of the IP vendor, a broad portfolio and cost.

Is consolidation good or bad for IP customers? The answer to this question is multifaceted and complex. The most accurate answer is, it depends. While the big IP vendors get acquired by big EDA vendors, new ones are forming in India and China. They are expected to begin showing up over the next 12 to 24 months en masse. And it’s not just India and China, where the bulk of IP is being created by startups.

The large IDMs in Japan are planning to make some of their IP commercially available in the Japanese market over the next year, with global ambitions for selling that IP after that.

Kochpatcharin, for one, believes that consolidation is a healthy trend because it creates an opening for new startups, which can’t always rise above the din of dozens of midsize IP vendors to effectively market their IP. But the transition isn’t always smooth. “When it goes to fewer vendors the business bundling gets easier, but in a customer tapeout that’s usually not the deciding factor. With smaller IP vendors it’s easier to get IP that’s customized to their needs.”

But not all IP is outsourced, either. Synopsys estimates that only about 65% to 70% of standards-based IP is outsourced. The rest is developed by companies themselves, which is still an option.

And despite all of this, there appears to be no slowdown in IP growth. The whole market is growing. Ron Moore, director of PIPD strategic accounts marketing at ARM, said that growth is likely to continue for several reasons. “First of all, the explosion of mobility devices that support multiple radios, multi-processing, and apps ecosystem will rely more on commercial IP for the system. Second, many semiconductor companies are focusing their flat (or shrinking) hardware design resources on SoC integration of high-value parts rather than building reusable IP. And third, the continued growth of the fabless or fab-lite business model means that the deep knowledge of the process technology required to co-optimize the IP will be concentrated in the leading IP companies.”

Is integration easier when large EDA companies or IP vendors control more of the pieces? Answer: Sometimes no, sometimes yes.

“Integration is not the main driver of this consolidation,” said Yankin Tanurhan, vice president and general manager of Virage’s processor, SoC infrastructure and NVM solutions. “But the advantage of consolidation is that everything is under one roof so you can make sure it’s compatible. On the other hand, monopolies don’t work. You need a combination of open standards so you can mix and match as much as possible. Integration will be easier, but there is still strong demand by companies not to rely on a single vendor.”

Not everyone believes integration is easier if it all comes from a single vendor, however. Kochpatcharin said that in some cases it’s better—particularly when it involves a controller and PHY from the same company—but two different types of IP do not necessarily work better together.

Moreover, those IP blocks may have been developed by different teams, in different locations and at different times. In fact, they may have been developed by different countries that were brought together for economic reasons. But as Tanurhan noted, it’s still easier to address interoperability issue in a big development organization than in 100 different companies.

The most effective way to ensure interoperability isn’t unifying development under a single corporate umbrella. It’s establishing standards such as IP-XACT, which has emerged as the most prominent standard in the IP industry. “With hard IP it will be different, but with soft IP standards will drive the ability to integrate,” said Tanurhan.

Will the role of EDA companies change when it comes to IP? Answer: Yes.

John Bruggeman, chief marketing officer at Cadence, has been quite consistent in saying that the challenge of the EDA industry is integrating IP and software as a way of getting the cost down in chip development.

“The role for EDA is where we enable OEMs to define and specify a system that optimizes system verification, design and modeling,” Bruggeman said. “Once you specify the system model you should be able to pump it into the supply chain and have it deliver against the spec.”

IP is a big part of that strategy, which is why Cadence bought Denali. The company builds memory models, which provide that spec. “What will change for EDA is that we will have three customers in the future vs. one today, which is the semiconductor company. In the future the OEM will become a customer because they will buy the platform, and the foundry will become a customer because the system model will be handled from OEM to foundry.”

Mentor and Synopsys are both taking similar routes, even though they are less vocal about the changes. Synopsys is working on software prototyping and standard IP, while Mentor is providing the tools for creating larger models and ensuring the manufacturability. And while there is divergence in the approaches among all three of the big EDA vendors, there is also cohesiveness in their recognition that big changes are afoot and various different approaches will be necessary.

How will IP change in the future? The biggest change for IP at future nodes may be around liability and flexibility rather than the IP itself. In a 3D chip, for example, IP that may be perfectly good on a single die may not work. In fact, an entire chip may not work, which likely will result in some nasty finger-pointing comparable to when the IP industry first got going.

“This is one of the ugly sides of 3D,” said Tanurhan. “The level of qualification might have to change.”

By Ann Steffora Mutschler
With the amount of IP blocks being integrated in SoCs today – in some cases as many as 100 blocks in a single chip – SoC design methodologies are shifting to address the new challenges this complexity brings. The good news is that these integration challenges has put the spotlight on the issues—along with the skyrocketing development costs for the creation, qualification, acquisition and integration of IP, which can account for as much as 25% of the total hardware design budget.

“There is an increasing amount of external IP being used and things are moving toward a printed circuit board-type methodology where we have large customers that are making several IPs and buying the rest, but we also have some smaller customers that only make one IP (the differentiator of their chip) and everything else is bought,” noted Charlie Janac, chairman, president and CEO of Arteris.

Design project managers are struggling to know how quickly that SoC can be assembled, what the cost is of the assembly, and how quickly the verification can be complete.

“The challenge is to quickly integrate IP that has multiple protocols. IP can be wrapped to chase a protocol, but that introduces unwelcome latency and risk. So you really want to use the native IP protocol that the IP comes in because that’s what is proven,” Janac said.

Further quantifying the situation today, Neil Hand, director of product marketing at Cadence Design Systems pointed out that “at 65 nm about a quarter of a $45 million design spend was spent on qualification of IP, which seems a little big but other customers tell us that for every dollar they spend on acquisition of IP they are spending $2 to $3 to make it work.”

The problem is “there is still a complete lack of consistency between the IP providers. There is no consistent set of standards for deliverables or consistent standards for quality or even what it means to be IP. Some vendors will say it has to be silicon proven when all they’ve actually done is put it in a test environment,” he said.

“Designers spend a lot of time creating the extra views, the extra models, and the extra things to integrate into their design before they can even get it to work. Even if you’ve got “silicon-proven IP” it doesn’t mean it works it all works well together,” Hand pointed out.

Mike Gianfagna, Atrenta’s vice president of marketing, believes this trend spells opportunity for EDA. “The shift from authoring to integration demands a new set of design tools to support reuse and integration. IP-XACT is one standard that is helping to drive this. There are others. At the center of the shift is the need for a rapid assembly, prototyping and validation tool set that works at a high level of abstraction on designs that are not yet complete. The need to interface to the software developer is also present here. These new tools will be in high demand, and should command a good average selling price. EDA hasn’t seen new budget dollars for quite a while – this new trend will break that streak.”

Cadence’s answer to this is its Open Integration Platform, whose stated goal is to reduce SoC development costs, improve quality and accelerate production schedules by concentrating on an application-driven development process and encouraging open, standards-based, collaboration within an ecosystem of production-proven semiconductor design companies, IP providers, foundries, service providers, EDA vendors and assembly houses. It is part of the company’s EDA360 view of next-gen, application-driven development. Cadence’s recent acquisition of Denali Software fits into this, as well.

The platform includes integration-optimized IP from the company and its ecosystem partners, an Integration Design Environment along with integration services. Cadence mixed-signal (analog and digital) design, verification and implementation products and solutions are the underpinning of the Open Integration Platform, the company said.

At the same time, while it has not been stated directly, Synopsys, with its acquisition of Virage Logic, is also expected to come out with IP subsystem products of its own at some point, possibly arranged around a sophisticated interconnect. ARM and Posedge also provide IP subsystems.

What does complexity mean for the interconnect?
While design teams have been using third-party and internally-developed IP in SoC designs for at least 10 years, what’s changed is that over time they have put more and more IP blocks onto the SoC. Today for high-end parts there could be upwards of 100 blocks on the SoC, according to Rich Wawrzyniak, senior market analyst for ASIC and SoC at Semico Research.

“The connectivity between the IP blocks is absolutely critical because the advantage of the SoC may be that you can put all of these blocks on the same chip to get the performance, but if the interconnect is incorrect, improper or not efficient enough you lose all of the advantages that you just gained. The biggest issues on these things are the type of bus architecture you’re going to be using,” said Patrick Soheili, vice president of marketing and business development at eSilicon.

Technical issues surrounding the interconnect abound, including IP re-use; efficient transport (how quickly the data can be moved around the chip); memory bandwidth issues; the number of gates needed, and routing congestion.

There is also the issue of SoC services. Here, Janac believes the industry has been confused about where those services go – whether they belong in the IP, the memory controller or in the interconnect. “The network-on-chip (NoC)-type interconnect handles the data transactions (signal packetization), which gets the SoC data onto the network and the wiring and transport services which move the data all over the chip,” he said, noting that Arteris’ NoC supports SoC services—higher level functions that control the operation and performance of the SoC. SoC services include quality of service, security, power domain management, frequency domain management and software debug.

“These higher-level functions have an impact on SoC performance, power consumption, security and software quality and belong in the SoC interconnect because they represent SoC system-wide functions that need to go to many parts of the chip. In a multicore SoC, the interconnect is the only part of the chip that sees all of the data traffic and thus is the best place to consolidate these higher level service functions,” Janac explained.

“The NoC-type interconnect is ideal for implementing these services it implements predictable networking techniques with relatively modest number of interconnect wires and communications control logic. Individual IPs such as memory controllers and processors no longer see all of the data operations that occur in an SoC and so they not the best place to try to implement these types of SoC wide functions,” he added.

Particularly on the road to 28nm, interconnect issues are a key roadblock along with IP readiness. “What’s challenging about 28nm is obviously the complexity, the readiness, the availability of the IP; the readiness of that IP becomes a major Achilles heel of getting to 28nm,” Soheili said.
In order to reduce the risks, costs and time to market for its customers headed for 28nm, eSilicon is planning to take a platform-based approach in which it would pre-design SoCs.

“This works in particular vertical markets where a customer can look to this platform that could be a certain percentage of the design already completed. Then, the customer’s value-add is in selecting and providing the software stack, the applications, the drivers all the way up to the system-level, along with marketing and channels and getting the customers. This could be done in very large volume markets or could be in smaller volume/higher margin markets or anywhere in between. The smarts go in finding a superset and going after vertical markets so you do the job once, you get through the silicon validation process and the design process and then harden it as much as you can before the customer comes in. Now the NRE is down, the engineering time and the risk are down, the time to revenue is down.

To be sure, this is an interesting time in the industry as design complexity and vendor consolidation bring up new challenges to address.

By Ann Steffora Mutschler

The EDA industry has seen a number of large acquisitions as of late, most notably of Denali by Cadence, as well as CoWare, VaST and Virage Logic which were acquired by Synopsys, but just what impact does this realignment have on the biggest EDA customers? Commenting on these changes is Jean-Marc Chateau, director of system platforms and tools at STMicroelectronics, the world’s fifth largest semiconductor manufacturer, in this exclusive System-Level Design interview.

SLD: As one of the industry’s largest EDA tool customers, how do you view the recent acquisitions?
Chateau: It is very interesting what is happening. It looks like all of the big players – Cadence, Mentor and Synopsys – are waking up to say, ‘We should change speed on ESL and try to create a market,’ which has always been so far in the $200 million range. Synopsys has been very aggressive, first with Virtio [in 2006], then with CoWare and VaST. It’s quite interesting because it can bring consolidation around pieces that were not fully interoperable. There are positive aspects of SystemC but there are things lacking in the standard – there are still missing pieces. So every company including semiconductor companies – not only tool and IP vendors – they have been obliged to build their own extensions. The fact is that companies like CoWare and Synopsys have to solve the interoperability between models and tools of what they have acquired because it’s not enough to be SystemC compatible. It will be positive because they will have to solve the problem for us.

But on the negative side, the risk is that they will build a closed solution and try to milk the user community—especially the software community—with a proprietary solution to which, when you enter you can not get out, and you have to follow all the flow with their tools. So we are looking at what will happen. I believe it will take Synopsys two years to really consolidate a single modeling solution out of what they are buying today. Cadence is more on the IP because Synopsys was very strong on IP; Cadence was stronger maybe on tools and they are trying to complete their solution. Mentor has a lot of pieces as well but still not very coherent and consistent all together.

SLD: Given that ST had a development relationship with CoWare, will the acquisition by Synopsys change ST’s relationship with the companies in terms of ESL development?
Chateau: In terms of ESL, ST has a long history of internal development. We have quite a large team developing solutions for all the divisions of ST and ST-Ericsson and this started more than 10 years ago. We have been pioneering ESL, especially pushing for open standards such as OSCI TLM. We have been chairman of the board at the beginning and also involved with SPIRIT IP-XACT for assembly of different IPs into SoC and subsystems. Therefore, we have an internal solution that is widely used for complex SoCs in TV, set-top boxes and mobile phones. The usage we have of CoWare is marginal – focused on the processor. We use technology to manage the coprocessor and to generate ISS and also to configure the coprocessor attached to a flexible processor. We have our own internal processor called XP70 – Tensilica-like, let’s say – and CoWare is our supplier in terms of technology to configure this processor. It is widely used in many applications such as set-top boxes and mobile phones. But this is very marginal.

There is another usage of CoWare in ST-Ericsson, which comes from the legacy of the acquisition of NXP Mobile and Ericsson. They were using CoWare especially in NXP so there are some platforms or subsystems that are using CoWare models, but fortunately they followed the TLM standard and we have been able easily to build a completely interoperable platform from the various pieces in ST-Ericsson. So for us, CoWare is relatively marginal and the fact that it was acquired by Synopsys is not impacting us much.

SLD: Do you sense from what you hearing that the top EDA vendors understand users’ biggest challenges in ESL?
Chateau: It is much better than it was, I would say, because we have been talking with them for years on that and there is really a change today in those three companies. I see, for example, Cadence has launched EDA 360; Synopsys of course will have to merge Virtio and CoWare into one platform, but it may leave it aside for the moment and maybe merge it later. And Mentor, they try to put together what they have in a consistent way. The verification part was a bit forgotten before but it is more part of it.

What they have not understood in the past is that the cost of modeling is very high and we cannot afford, by any means, to duplicate the platform for several flavors. We have system-level platforms that require a higher level of abstraction above RTL. You have the architects that need performance from this platform with certain flavors. There are verification people, mostly the sub-verification people, who require some testbenches at a high level. You also need to have a virtual platform for software development. The three cases would require in theory different approaches of modeling, but we cannot afford this so what we did 10 years ago was to make a decision and say, ‘We are going to define one way to do models and we have to apply it all of the categories,’ because it is always difficult to populate fully in TLM a complete system platform with models. To do that three times – no way. I think if you look at all of those companies – VaST, CoWare, etc. – they are focused on either verification or software virtual platforms or architecture investigation, but not the three of them together. Now, it seems to me, it is my perception that they need to tackle all, having in mind that the biggest population is software development. But if you look at the software budget we put on the shoulder of the software designer, it is very light in terms of CAD. We buy very few tools; we mostly rely on point tools so to introduce the same business approach as in hardware design with CAD seats that cost several $10Ks will not work in the software world. I still think they dream a bit.

SLD: With Synopsys acquiring Virage and Cadence acquiring Denali, how do you view this consolidation?
Chateau: To me it was very obvious Synopsys was missing the embedded memory part in their portfolio. With Virage they don’t target anything but that part. I don’t think they are very interested in the other part. They will have to make a choice between the differentiation on parts I’m sure. For Denali and Cadence, it is a little bit different because Cadence is still very weak overall in its IP portfolio, so I have no comment on this. Denali is strong in models so that can be a good asset for the company to position because they have acquired also a lot of companies for VIP and transactors and this is key to build an offering in ESL. So I think they have a good strategy, which is a lower cost strategy than what Synopsys did. So, we’ll see.

SLD: Does ST mind that the IP it purchases come from the tool provider?
Chateau: We preach for interoperability and we are very active in standards for that purpose, so we would like to deploy the IPs with the tools as much as possible. This is why in OSCI we are very much attached to the fact that there is an open source simulator that you can run with any models from any IP vendor to see if it is really following the standard. Of course the companies would like to kill this and do only paper for the standard because they would like to make money out of simulators in Mentor, Cadence and Synopsys, and CoWare before the acquisition. I understand, but we are fighting to keep that preference because TLM OSCI SystemC cannot be as strict and non-ambiguous and RTL-like as Verilog and VHDL. You really need to have an open source to check interoperability. The higher level you go, the more reference you will need like this, and therefore, our wish is to be able to buy IPs wherever we want independently of the tools. Today, if you look at what we buy … our biggest supplier is Synopsys, but it’s not because of the tools.

By Ed Sperling
Cadence completed its acquisition of Denali, moving the company squarely into the IP business for what amounts to an all-out IP arms race. Several sources have confirmed Cadence bid for Virage Logic first, but was outbid by Synopsys. Cadence subsequently made the $315 million offer for Denali. The selling price has lots of companies hanging out a “for sale” sign. The big question is who’s next?

ARM, the Common Platform companies (IBM, Samsung and GlobalFoundries) and Synopsys introduced a 32/28nm high k/metal gate that is “vertically optimized.” Exactly what “vertically optimized” means is something of a mystery, however. You won’t find any additional information about this in the release or in any of the links.

Mentor Graphics and Synopsys both updated some of their top tool suites at DAC, not to mention their relationships with foundries. Mentor is collaborating with GlobalFoundries on an advanced design and manufacturing flow using Calibre.  It also added verification, extraction and DFM support for TSMC’s AMS 1.0 flow, as well as ESL, integrated design, and manufacturing closure for TSMC’s Reference Flow 11.  In addition, Mentor’s Olympus SoC place and route is now supported by X-FAB.

Synopsys improved its PrimeTime performance for static timing analysis, migrated its Ly-nx pre-validated design environment for the Common Platform’s 32/28nm nodes. It also introduced a Galaxy characterization solution for standard cells, complex macros and memories, and it added StarRC custom 3D extraction for sub-45nm designs.

Cadence also provided its contribution to the Universal Verification Methodology, aka UVM—an open-source reference flow for SoC verification.

Atrenta introduced SpyGlass-Physical for physical implementation modeling. There was a lot of talk about tradeoff analysis and what-if approaches at DAC this year.

http://www.atrenta.com/atrenta-news/96.news

AMD inked a deal for Apache Design Systems’ power supply noise and reliability sign-off tools. Considering the close relationship between AMD and GlobalFoundries, this becomes particularly interesting.

By Ed Sperling
You would have to be hiding in a cave without WiFi to miss the Synopsys acquisition of Virage Logic, which is due to go through in Synopsys’ fiscal Q4. This should turn Synopsys into an IP powerhouse and push it further into adjacent markets. And Synopsys still has a pile of cash remaining, so don’t think this is the end of the acquisition spree.

Case in point: At least some of the money leftover went to purchasing Synfora’s high-level synthesis technology. Considering Synopsys didn’t really have a play in the HLS market until last year, it has gained expertise in this area rather quickly. Synopsys’ push into software prototyping followed a similar pattern. There are three other big players in HLS, Mentor, Cadence and Forte. Synopsys doesn’t have enough cash to buy Mentor or Cadence, but there are plenty of rumors floating around about what company it can buy.

Mentor, meanwhile, is working on drumming up interest in HLS, which has been slow on the uptake for the better part of a decade. It introduced a high-level synthesis reference book, known as the HLS Blue Book. It’s everything you wanted to know about HLS–and it’s free.

Cadence is raising some big bucks on the side in a note-swapping deal that will provide millions to the company’s general fund. So far it hasn’t said what it’s going to do with that money, but given EDA stock prices these days Cadence may be gearing up to do some acquisitions of its own.

Mentor rolled out yet another addition to its Calibre DFM suite, this one aimed at fast and accurate extraction using 3D field solver technology. Translation: Calibre is a cash cow for Mentor and the company is making sure it stays that way.

All the big EDA companies seem to have some sort of announcement with TSMC this week. It might have something to do with the new flows that TSMC has introduced, including its analog/mixed signal reference flow 1.0. Synopsys validated its custom design solution with that flow and is working to validate Galaxy at 28nm for TSMC’s interoperable process design kit. Cadence likewise threw its support behind TSMC’s AMS 1.0 for 28nm. TSMC also included Apache Design Solutions’ power and noise solutions in two of its flows, including the AMS 1.0. And Mentor is working with TSMC on waivers for its design rule checks so previously waived IP doesn’t slow verification.

On the processor front, ARM introduced a virtual debug interface called VSTREAM that allows developers to stop the processor, view and change the value of registers and system memory. The tool works with both Mentor’s and Cadence’s emulation platforms, as well.

Actel is offering a free IP cores bundle and RTL package options with its standard software bundle. Until now most of the FPGA vendor giveaways were basic tools. This ups the ante by quite a bit.

By Ed Sperling
System-Level Design sat down with Ravi Varadarajan, an Atrenta fellow; Geert Rosseel, vice president of technology at Arteris; Yankin Tanurhan, vice president and general manager of Virage Logic’s processor and NVM business units, and Mike Smayling, senior vice president of product technology at Tela Innovations. What follows are excerpts of that conversation.

SLD: Why is it so important to move to 3D?
Tanurhan: The whole idea why you go to 3D is to reach volume faster. It will allow massive re-use. The only thing missing is modeling and the standards. Once you have that, you can make intelligent decisions about what to model and where to place it.
Varadarajan: A lot of that is happening today. When you look at place and route and synthesis tools today, every cell has multiple footprints—low speed, high speed, different power. There may be 25 variants of a standard-cell library. It’s the duty of the synthesis and the place and route tool to pick the right one to meet all these multi-domain objective functions. I look at 3D the same way. If I have an IP block, it might exist in two different technologies—one at 65nm and one at 90nm, and maybe one at 28nm. Each IP has different fixed footprints, timing characteristics, area characteristics and power characteristics. This prototyping tool is helping you determine whether it’s better to keep the IP at 90nm or is it better to bring it down to 28nm. What we’re doing at the transistor level has to be done at the IP level and the memory level to make this more scalable.

SLD: What happens to signal integrity if you get hot spots?
Rosseel: It’s no different than what’s happening on chips today. The only question is whether you can model the hot spots and get the heat out. There is a big temperature issue even today. With 3D, you’re going to put more power in a smaller footprint. So how do you model that? How do you know you’ve got the heat out? That is the main challenge there.

SLD: What happens to the IP and how do you test for all of this?
Tanurhan: The amount of characterization you need to do will be larger and you will need more parameters. But once you’ve added those parameters and the right modeling tools that would not be as big a challenge.

SLD: So what you’re talking about is guard-banding your IP?
Tanurhan: Yes. You need all the temperature information, and the designer or even the tool putting that information together has to make the right choices.
Smayling: I spend most of my time thinking about 1D problems. But as we scale technology to 28nm, 22nm and 16nm, the patterns are going to become very regular 1D patterns. From my viewpoint, being able to partition IP between the leading edge, which will require these kinds of design styles, while still allowing older devices with 2D design styles, is going to be a benefit for the industry. It will let us continue scaling logic functions, which are not constrained by electric fields as much as analog or some of the memories. It becomes a patterning problem, which we can deal with.

SLD: Can you find the bugs the same way in a 3D structure as in a 2D structure?
Varadarajan: You have to be able to leverage everything we do today in 2D and to build new models. New factors come into play such as mechanical and thermal stress—not just the heat—when you stack these dies on top of each other. But a lot of people who should be worrying about these problems are actually worrying about them. For this to be a viable alternative, we need to figure out how to do the testing and how to reliably manufacture it. I think it will be an evolving process over the next one or two years.

SLD: What happens to power requirements in a 3D chip? Does it go up or down?
Smayling: It will go down. You’re driving shorter loads and less loaded devices.
Tanurhan: If you are using older mature technologies your power cannot go down. It should be staying where it was. One of the tricks to re-using an older node is to get the power down. The only thing we can do is control the power more efficiently. If you do it on a single die you have to introduce a lot of trenches and you need a complex process to manage multiple voltage domains. Now you don’t have to do that. You can have die by die with different voltage domains and you can introduce a much more intelligent power structure. But it will not happen on its own. By definition the power should be going up.
Smayling: The reason it will go down is that the interconnect is dominating the power now, not the active devices. Unfortunately, we’re spending a lot of time moving capacitors.
Tanurhan: But with 3D you’ll have even more interconnects.
Smayling: But those will be shorter interconnects.
Varadarajan: You won’t have as many buffers and repeaters as on a 2D chip.
Tanurhan: But you still have to drive power from chip to chip. It’s not free.
Smayling: But it’s less than driving bonding pads and bond wires on a circuit board.
Tanurhan: Absolutely, but not always less than the wire. The whole power calculation has to be made.
Rosseel: It all depends on where you’re coming from. If you’re taking an existing design and putting it on multiple die, power will go up because you’re at capacity. If you’re taking a stacked die and putting it in a more normal 3D structure then power will go down because you won’t have to drive that much I/O capacitance.

SLD: How about multiple voltage domains?
Smayling: We’re able to separate voltage domains, which is good. That drives people crazy today. But let’s suppose I have a 3.3-volt analog chip that I’m going to attach to my 1-volt chip. I need to get that 3.3 volts out to a pad somewhere, and the PDK for my 1-volt chip doesn’t even understand 3.3 volts. It gets back to this multiple-node and multiple-domain PDK problem. That’s something we’re going to have to work out. The devices won’t even support some of these voltage requirements.
Tanurhan: Or you have to bond from the other die, which we have seen in past situations.

SLD: Let’s look at drivers for 3D. Is it cost or is it technology?
Tanurhan: Sometimes it’s IP availability. How do you get access to it? Sometimes it’s easier to get access because someone is already using it internally. It also may be the only way that architects are looking at the problem today while everyone is waiting for EDA to show up.
Rosseel: We have extended the network-on-chip protocol for a chip-to-chip interconnect, which would serve 3D because it’s very lightweight and configurable, with low latency and relatively high bandwidth. People are already using that for stacked die solutions. We haven’t seen any real 3D yet, though. Stacked die is what people are using today.
Varadarajan: Some of our big customers are seeing both. The mainstream world is not starting to think about 3D yet, but the large companies have either done it or are actively thinking about it.
Smayling: A lot of the motivation is cost, but completely new functionality is a technology driver. We think in terms of integrating multiple silicon chips. But if we can start putting optical components into the mix, now we’ve got communication bandwidth available that we didn’t have with a pure silicon solution. There’s a lot of opportunity out there that is limited by our imagination. When we start mixing these materials and properties of some of these compounds and the integration we get with analog-digital silicon, we’ll get to things we haven’t even contemplated.