By Ed Sperling
System-Level Design sat down with Ravi Varadarajan, an Atrenta fellow; Geert Rosseel, vice president of technology at Arteris; Yankin Tanurhan, vice president and general manager of Virage Logic’s processor and NVM business units, and Mike Smayling, senior vice president of product technology at Tela Innovations. What follows are excerpts of that conversation.

SLD: What’s the advantage of going to 3D? Is it speed, re-use of IP or timing closure?
Rosseel: It’s heterogeneous integration. You’re not going to be able to move all your analog IP to each new process node. It’s too expensive and it’s increasingly difficult. Splitting application processors from modems, memory from the processor—that has to be the main driver. Otherwise chips will be too complicated and you won’t be able to test them.
Varadarajan: Analog makes a perfect business case, but speed is the second factor. When you look at 28nm, to get from IP No. 1 to IP No. 2 with a clock speed is 500MHz, 600 microns of wire takes up more than 1 nanosecond of delay. In two dimensions you cannot get every IP close enough to every other IP. You’ll hit a brick wall going to the newest process node because of the wire.
Tanurhan: It depends on what kind of chip you are talking about where you have to go up. The main driver is still cost—and all the derivatives of the cost. The second driver is connectivity. You cannot reach everything on the chip in a reasonable manner. We are running into more and more insularity problems. You want to have access to an IP block but you may have to wire too much. So you introduce many layers or directly connect, which keeps the cost down.

SLD: What’s the biggest impediment? Is it putting the chips together? Is it testing them?
Tanurhan: 3D has always been seen as a way to minimize time to volume. You have existing IP that is working and already has high yield. The only thing you have to do is move it to another die. But once you put those two dies together you have to test it. Was that IP made to be tested in this integrated mode? Maybe not. Now you are running into testability issues. Once you manage that, you have to sit down and make a cost calculation about whether you are saving anything. You are testing two dies, putting them together and testing them again. This isn’t free. We are seeing people having problems with this where they put two dies together and have lower yield. It’s not that easy. With memory we have a good handle on it. But if you have multiple chips with PHY’s on them, it may get very ugly very fast.
Varadarajan: If going to 3D requires you to re-tool your entire EDA flow, it’s not going to happen. There also need to be standards. Does a TSV go into a LEF file in technology node one or two or a new standard? How are the parasitics of the TSV going to be represented? What are the timing characteristics? But at the same time the most efficient way to get there is to keep the existing 2D tools working and build something on top of it so each die becomes a well-contained 2D problem.

SLD: For connectivity?
Varadarajan: Not just that. It’s even for prototyping of a 2D chip before actual implementation. If I’m putting a complex SoC together I have to take it through place and route to make every critical division as to how big a memory I need and where it’s going to be placed. That’s a very time-consuming flow. People work through it today by putting on more designers, but you can’t do that in 3D. You need to be able to make critical decisions up front. The prototyping technology needs to develop more than today. You need to be able to make what-if tradeoffs, and it needs to be correlated with what’s on the back end. If you can do that up front, you can extend the existing EDA tools. The challenges are standards on one side, and the other it’s the methodologies and the flows.
Rosseel: The next step is going to be a more manufacturable, denser solution for a stacked die. You don’t need a lot of new tools for that. You just need to partition it correctly. You can do it already, except from the manufacturing side.
Tanurhan: The problem you are talking about is similar to a PCB problem, and we are solving that already. The first 3D solutions were 2D. The dies were sitting next to each other—MCMs (multi-chip modules). Besides tooling, though, we will need standardization of the manufacturing, as well. Everyone has their own ideas about how to manufacture. For the tools people to make money, they need some standardization on manufacturing, as well.
Smayling: The EDA people should really embrace 3D because it’s like opening up a whole new can of worms. They can definitely add value to solutions here. One of my pet peeves for many years is that SPICE is isothermal. You have one parameter for telling you the temperature of the room, but the transistors are not all running at the same temperature. If you’ve got a chip with hot spots and you put another chip on top of it that, even if  you’ve simulated and designed and it all works fine, when you put them together SPICE doesn’t know that. It wouldn’t even know when I designed the first chip that I had that problem. You need to be able to add a layer of insight in the IP to be able to understand what other IP is doing. There’s a tremendous opportunity. It’s a very big problem if you get out of constraint situations. You can put processors on memory. One company put DMDs (digital micromirror devices) on top of an SRAM. You can do that in a very constrained environment. But when you have an ASIC flow where it’s the Wild West, it’s going to take a lot of work.

SLD: The mapping of the thermal characteristics becomes extremely difficult if you don’t have a standard layout and way of putting these together, right?
Tanurhan: Yes, and that goes back to the manufacturing standards. You have to deal with temperature in placement. Today we are mainly driven by power, so we can indirectly influence it. Most of the power during place and route gives us an idea of where it will hit on the temperature. It’s could be a second-order effect, but you can use that to get the problem controlled. It depends on how many hot spots you can withstand on your chip. When you put two chips together and you get effects from that—that’s what we still cannot model very well. We are working on cooling between the two dies now.
Rosseel: Yes, they are developing heat sinks for that.
Varadarajan: If I have two dies and I’ve already done the partitioning and determined these IPs are going to be on die one and these memories are going to be on die two, obviously there is some communication between them. The simple approach is to floor-plan die one and figure out where these connection points are. That’s not the best way to do it, though. You need to look at these two floor plans simultaneously and figure out where the interconnects go. That’s where some of these problems can be dealt with like how do you reduce the thermal profile. If you can model it you can optimize it. You know which IPs can be on top of which IPs. Those are the new problems that can be solved in a layer up front. After that, each die is a 2D problem.
Rosseel: But you can only do that if you have full control of the whole design. You won’t have that because some of your chip is going to come from somewhere else or you’ll want to re-use the old one. It makes no sense to do everything from scratch. You will need some standards. The analog chip isn’t going to change for a number of years and the digital chip is going to spin every year.

By Ed Sperling
One size no longer fits all, and that’s causing consternation across the supply chain from established EDA vendors to point tool developers all the way up to the largest chipmakers.

While the overall number of design starts for SoCs really hasn’t changed much, despite a drop in the number of companies working at the most advanced process nodes, what has changed significantly is how companies are getting chips out the door, what process node they’re using and how they view the future of design. And for EDA companies, which get the biggest return on investment when they can build tools that automate processes and tasks for the multitude of engineers rather than just a few, this puts them into a quandary. Do they develop tools for the few that are willing to pay for automating some of the complexity at advanced designs, or do they look at alternative approaches.

The answer for the Big Three—Mentor Graphics, Synopsys and Cadence—has been to cater to the most advanced customers while also spreading into adjacent markets for incremental growth. The question for them is whether the adjacent markets will provide enough growth to warrant the investment.

For point-tool makers, the question is what kinds of problems need to be solved and who’s willing to pay for a solution. And at the most advanced process nodes, the question among chipmakers is whether they’ll be forced to develop their own tools at greatly added cost, whether the tools will be available from commercial vendors as regularly as in the past, or whether they can get buy with existing tools from older nodes.

Cause and effect
At the most fundamental level, there is a schism in the design community between those looking to reach the most advanced node—those who make memory chips, smart phone SoCs, GPUs and CPUs—and those who can live with improvements at older nodes ranging from 130nm to 180nm where tweaks can improve performance and/or lower power consumption.

One of the best real-world measurements of this trend is in the standard IP sold by companies like Synopsys and Virage Logic. John Koeter, vice president of marketing for Synopsys’ IP and Systems, said the number of SoCs with one or more processors is staying constant at about 3,500 design starts and expected to increase to 3,700 in the next few years.

“From a raw number standpoint, the TAM (total available market) is the same or growing,” said Koeter. “But what’s also going on is people are staying longer at any process node. We track 1,000 to 1,500 IP requests, and of those about 43% of the demand is at 65nm and 35% is at 45nm.”

So what about the other 22%? “As an IP provider, we’re being asked to re-optimize IP at older nodes,” he said. “In some cases it’s how you enable a lower-cost system. We’re seeing a lot of demand at 110nm and 130nm in Asia/Pacific for devices fitted with the latest standards like USB 3.0 for low-cost applications.”

Hedging bets
Evidence of this change is everywhere in EDA these days. All of the Big Three are pushing into adjacent markets. Mentor’s push into DFM with Calibre is paying off big for the company, despite the fact that when the company began going down that path it was greeted with widespread skepticism. Mentor also has pushed into other areas such as mechanical analysis and more recently PCB design.

Synopsys, meanwhile, has focused on IP and software prototyping, so that software can be developed in conjunction with the hardware. The moves are more in line with Synopsys’ overall flow, but its push into power analysis with Eclypse and more recently into high-level synthesis and FPGA tools are a step outside the company’s traditional borders.

Cadence, in contrast, has pushed heavily into a software-first approach with its EDA 360, an idea that has been circulated around EDA for years but which is being taken seriously now in part because of the complexity and cost of developing chips at advanced nodes. The company also just announced plans to buy Denali, which makes modeling IP.

“About 70% of a chip is re-use,” said Vishal Kapoor, vice president of product management at Cadence. “The challenge is integration. So far we’ve made sure it is compliant, but what we need to develop are tools that are built with a focus that ranges from creation to integration. And then we have to make it so it can be integrated into an SoC.”

Kapoor said IP is what’s expected from EDA vendors. But he said the rest of the world is software-driven, with the application being the most important. “If the hardware guys do not present differentiated pieces of hardware we will see commoditization of the hardware. The consumerization trend is forcing us to think about getting the most out of hardware.”

But even IP vendors aren’t just IP vendors anymore. Virage Logic, which started out making logic and memory IP, is now extending into other areas of the design such as built-in test.

“It’s not architecture first and then the system,” said Yervant Zorian, Virage’s chief scientist. “It’s building blocks coming together. In the past it was build everything together and then think about testing. It’s not an add-on. It’s now an integrated part of the smallest units that you’re building.” He noted this approach first began with memory more than a decade ago, but it is now being implemented into almost everything.

Thinking in 3D and other technologies
Perhaps the biggest changes will come by way of packaging and three-dimensional design. That will allow chipmakers to keep some of the old design, particularly the analog blocks, while leveraging the digital components that do benefit from Moore’s Law. Analog has never fit into that equation.

“What we’re seeing is the impact of system in package,” said Gary Smith, president of Gary Smith EDA. “You lag on analog and try to keep up in digital. What’s interesting is we probably have all the technology you need to switch already. In 3D, we’ve got most of the problems already solved. The next step is to get the cost out with volume.”

One of the interesting things about 3D technology is it allows companies to focus on a smaller piece of the overall development and to utilize the most advanced process nodes in addition to less advanced ones. That drives down the cost of development significantly and brings companies that have abandoned Moore’s Law because of cost back into the two-year digital process cycle. Processors and certain types of memory can still progress to the next node while analog and I/O may persist at older nodes for years and still gain performance and power consumption benefits through shorter wires and through-silicon vias.

Smith says 10% to 20% of the chip still needs to be created each time a new chip is introduced to remain competitive, but even if that number remains constant some of that development may be on the analog rather than the digital side. It also may be the software, or it could be the hardware optimized for the software or the software optimized for the hardware. Or it could be a faster I/O channel and a virtualized chip environment.

Smith, for one, believes the big innovations will be in packaging and stacking. He also believes that CMOS as we know it will run out of steam over the next few process nodes, and that what will make other substrate materials more cost-effective will be the same volume production that has kept Moore’s Law viable since it was first introduced in 1965.

FPGAs have taken an early lead in this arena. Actel’s SmartFusion platform includes programmable analog with an FPGA. Xilinx reportedly is working on its own version of programmable analog blocks.

Conclusion
While it’s too early to tell which approach is the right one or exactly what path will prove most profitable for developing chips, IP and ultimately software, it is clear that a transition is under way. And while transitions are always interesting to watch, they also produce fallout in the way of winners and losers—and potentially new competitors.

By Ed Sperling
System-Level Design sat down with Ravi Varadarajan, an Atrenta fellow; Geert Rosseel, vice president of technology at Arteris; Yankin Tanurhan, vice president and general manager of Virage Logic’s processor and NVM business units, and Mike Smayling, senior vice president of product technology at Tela Innovations. What follows are excerpts of that conversation.

SLD: How real is 3D?
Smayling: 3D is clearly happening. People are building chips with 3D. As with any pioneers, they’re the ones with the arrows in their back. There are a lack of tools and a lack of infrastructure, but that will change. Applied Materials announced it is supporting the dielectric coatings for through-silicon vias. It’s important to have those tools available if you’re going to build the structures. Having the big manufacturers get involved means they see the importance of the business and the demand for multiple tools.
Varadarajan: The business need and the technical need for 3D is real. Moving to 28nm and below, there are two factors at play. One is the complexity of the interconnects. When you are dealing with 2D, the wires are incredibly long. The performance you’ll get by going to smaller geometries will be nullified by the long wires and the complexity of doing the layout. The second aspect is heterogeneous integration. There’s really no need to migrate everything you want to put onto an SoC into the new technology. That’s an impediment today. If you have an analog block and some memories that don’t need to move to the next node, you still have to do it if you’re building a chip in 2D. When you look at the complexity on one side and the parasitics on the other, both of those say you need to have some sort of 3D technology moving forward. The process enhancement has been happening and 3D technology is coming to the point where it can become mainstream. This is a wonderful opportunity where the technology is maturing and the need is prevalent. Leti, Imec and SEMATECH are all coming together. If you don’t have some sort of 3D strategy in 2012 you’re going to be left behind, at least for memory on core architectures.
Rosseel: Somebody has to take a contrary view. I think we have to define first what 3D is. You can start with a package on package, which is some version of 3D, and then you have stacked die and go all the way down to having four or five chips fully designed as an integrated circuit. I think the last one is a long way from reality, and I’m not sure if that’s even desirable. Stacked die is already happening. But implementing stacked die as multiple chips on top of each other may not be worth it. You get an extra process complexity and extra cost for doing that. There are too many problems to implement that.
Tanurhan: The real driver of 3D is that no one can pay all the costs for a certain process node. Being able to use multiple process nodes on the same application is opening that corner, and that’s how the whole mechanical 3D solution came in. For a while it was called system in package. The first time I heard the ‘3D’ word in conjunction with semiconductors design was the early 2000s, and in 2007 it started to become a marketing name. I still don’t know what it is. The IBM concept is different than an SiP. A single-die 3D is a big change, because you will get higher density, you will minimize the wiring, and you will need a lot of IP. But we are not seeing that pull yet. One of the reasons is the tools are not available and another is the yield is not there. But 3D is extremely interesting for us. With non-volatile memory the sweet spot is still 90nm and above, even though we have 65nm and 40nm available. It doesn’t make sense to take this technology to 28nm because the price tag will be enormous. The analog circuit doesn’t shrink. You have to pay more for the wafer. So stacked dies are becoming very interesting. But it’s not easy to do. The world is going to multiple processors, heavy on-chip communication and heavy processing. Now you have to cross domains from one chip to another and you cannot use the communication protocol you’ve been using. It behaves more like a PCB, but it really isn’t one. And, by the way, it’s your problem to solve the timing issues because we don’t have tools, either. For a memory block, it’s a done deal. But having multiple processors communicating on the same bus and sharing the same memory will be a heavy thing to lift for all designers.

SLD: Let’s dig into some of the problem points.
Varadarajan: You’re talking about people conceptualizing where you have 90nm, 65nm and 45nm. Just splitting the gates across the different technology nodes and figuring out the best possible layout and the routing is an interesting technology problem to solve. I don’t think we’re going to get there anytime soon. But memory is happening today. You can even extend that one step further to when you have a two-die structure and you just put in memory. You have a lot of white space on the memory die. If you look at systems on chip today, they are complex IPs put together with a bus fabric connecting them. These IPs exist in multiple technologies. You can start to question whether this IP belongs at a lower technology node or whether it can go into older technology nodes because there is empty real estate. By doing that, how do to the timing and high-speed IP look? That is a practical application. It’s memory and then also migrating entire IPs into different tiers and dies. Then you have to look at timing and your thermal profile and whether you need to do something special to dissipate the extra heat. But if you can solve all of these problems you have a viable approach.
Rosseel: We’re looking at this more from an architecture point of view. People are not going to share transistors and gates, but they are going to share IP between different die. Then the only question is how these IP blocks are going to talk to each other. We see network on chip as a communication mechanism. You need some kind of communication because they’re all developed separately and designed separately. To create that coupling you’re going to have to create some standard interfaces. They will have to be asynchronous and configurable. With standard interfaces you can test them separately and design them separately.
Tanurhan: Network on chip is on-chip. This one is off-die. There is a lot of development that needs to be done. The white space issue is real and has to be addressed, but it’s a system architect’s nightmare. It is not straightforward to have all that timing budget and model it right. The reason why it works with memory is it is very nicely encapsulated. Sharing IP blocks will require two elements. One is local management capability, so you will some type of system supervisor to make sure all that local intelligence is managed right. That is not a passive element. On the really high-speed 3D, you also will have all the cooling problems. Today you can create a really high-speed processor. If you have two of those, one sitting on top of the other, how do you keep them alive? So one challenge we have is connectivity. A second is yield. The cost function still has to make sense, too. Yield is a multiplier of cost.
Smayling: 3D has been around in ICs since 1985. At that time we were building DRAMs with planar capacitors and we couldn’t build the chips big enough because of reticular limitations so we began building in 3D structures, either trench capacitors or cup capacitors. Integrated devices like DRAMs had to start long ago, because of cost reasons, to go 3D. Cost has always driven our industry. People will do 3D or hybrids if they’re cost-effective, but they won’t be if the tools aren’t there for the masses to use them. You can always have very big engineering teams figure out ways to grind through these problems, but unless you have EDA support, ecosystem support and standards it won’t happen. How can you design a 3D chip with the tools you have? The data structures aren’t even there to understand what you’re trying to do. At TI we built these merged process devices and they were successful if you knew what you were going to merge at the beginning and then used as much of the additional process complexity across the chip as possible. If you added 5% to the wafer price but only used it on 2% of the area you had a losing proposition.

Mentor introduced its InRoute extension to its Calibre DFM platform, allowing it to be used inside the company’s Olympus place and route system. According to Mentor, InRoute fixes DRC violations and tunes a design for DFM while addressing area, timing, power and signal integrity.

Synopsys updated its IC Compiler release, which boosts speed by up to 2.5 times with support for 32/28nm processes. The product is aimed at reducing surprises late in the design cycle, when most engineers seem to rather suddenly lose their sense of humor, by enabling signoff-accurate static timing analysis, rail analysis and physical verification during the design cycle.

Cadence uncorked its Open Integration Platform, which it says will significantly chop SoC development costs and time to market. At the heart of the technology is integration-ready IP from Cadence and its partners. The technology is part of Cadence’s push into more standardized hardware platforms that are defined by the application software.

Virage Logic reported its fiscal Q2 results for the quarter ended March 31. Revenue was $25.2 million compared with $11 million in the same period in 2009 and $21.7 million for fiscal Q1. What a difference a year makes. The GAAP loss was $1.1 million vs. a loss of $21.7 million for the previous quarter. While that’s much improved, it’s even better than it looks. The loss was largely acquisition-related. The company acquired ARC and NXP’s IP business in 2009.

Mobileye, which makes vision-based SoCs for driver assistance–the kind you wish you had on your car–licensed MIPS’ Coherent Processing System, a multithreaded multiprocessor IP core.

Synopsys also unveiled Ethernet controller IP with audio bridging for streaming audio and MIPI DigRF v4 IP for development of LTE and WiMax SoCs.

When the market window is closing, it’s time to break out the big iron. Mentor’s Veloce emulation has been tracked at 400 times acceleration for OVM-driven verification. They clocked it with a stopwatch.

And finally, TSMC amended a statement made by its CFO during the previous day’s earnings call regarding market segment changes. The release says that TSMC’s wafers are constrained by current capacity and that is no indication of customer demand. That statement may raise far more questions than it answers.

By Ed Sperling
Low-power manufacturing processes may start out looking like the better option for saving battery power and energy, but at 40nm and beyond there is less ability to really turn down the voltage than with the standard process geared toward performance.

Combining the benefits of two processes into one has a major benefit for fabs. Developing dual processes is enormously expensive at advanced nodes, and if a single process can be tweaked to provide either more performance or lower power—or some middle ground between them—then it makes economic sense to invest in a single process and perfect it more quickly.

TSMC currently has three 40nm processes—low-power, general purpose, or G, and low-power triple gate oxide (LPG). Of the three, the G process is getting far more attention both inside and outside the company.

“The (TSMC) G process at 40nm is .72 volts,” said Lisa Minwell, technical marketing director at Virage Logic. “The LP process has a higher starting voltage and it can’t swing as far.”

The design rules are the same for both the G and LP process, Minwell noted.

At 28nm, TSMC’s G process uses high k/metal gate technology while the low-power process does not. Engineers at several companies said the implication is that TSMC’s expectation is that at 28nm everyone will need to move to high k/metal gate. The Common Platform, meanwhile, is working on a high k/metal gate version of the LP process as well as its high-performance process.

By Ann Steffora Mutschler
As the semiconductor industry moves from older manufacturing nodes to newer ones what users want from IP providers is changing. So is the way IP providers are answering those needs.

Mirroring the broader semiconductor industry’s recognition that it’s simply too expensive, too difficult and too time consuming to do everything alone—the very basis of the IP sector’s existence—the race is now on to glue together large ecosystems that can fill in the cracks. What an IP vendor cannot provide, their partners usually can.

This is a huge shift for the IP industry. A decade ago, cores were delivered in a hardened fashion. But at current process nodes, as performance levels combined with design complexity and requirements for power management go up, design teams expect more.

The chip industry also has moved away from hard IP cores to synthesized cores, and for the last three or four semiconductor manufacturing nodes IP cores from the top providers in this space—ARM, MIPS, Synopsys and Virage Logic—have been offered primarily in a synthesized fashion, thereby putting the burden back on the designer to implement the core.

These issues make it increasingly challenging for a semiconductor company or OEM to remain competitive, so anything the IP vendor can do to make it easier to deliver a good result is highly valued. As Dr. John Heinlein, VP of marketing for the physical IP division at ARM put it, “We offer a complete solution to customers so they don’t have to stumble around in the dark trying to get an optimized implementation.”

Every major IP vendor has a similar approach. Economic conditions, time-to-market constraints caused by frequent product revs and shrinking product windows have made integration a key factor in the success of an IP implementation.

Kevin Kitagawa, director of strategic marketing for MIPS Technologies, affirmed that customers do indeed need solutions and, depending on the market segment, they ask for different things. “In a lot of cases, it is a time to market thing,” he said. “What they are trying to do is get from licensed IP to tape out as quickly as possible. It used to be that they would take the time and evaluate things and the value-add that the SoC designer did was really in that ‘secret sauce’ in tying all that IP together. That’s how they differentiated themselves from their competitors. They are still doing that, but it’s mainly by choice of IP.”

Yankin Tanurhan, vice president and general manager of the processor and non-volatile memory solutions division of Virage Logic, said the first step of extended IP demand started with customers asking for drivers for the IP they were integrating. But it didn’t stop there.

He said Virage has been “quite adamant” about the draw of a full IP solution, pointing to its Sound-to-Silicon solution as one example: “[This approach] shortens the time to delivery of the complete product because today’s world is expecting much more than just a drop of an RTL or attaching a driver to that RTL – they are expecting to get the full stacks, potentially even the codecs.”

The bigger picture
But providing every stack and codec isn’t possible for every vendor. As a result, IP providers have created their own ecosystems of third-party partners to deliver what they don’t, and have built up engineering teams to keep quality levels high across the ecosystem.

For instance, Virage has a 50+ member engineering team in St. Petersburg that focuses on codecs, as well as embedded software development activities in Eindhoven, Netherlands, and Fremont, Calif.

Likewise, ARM counts more than 700 partners in its ARM Connected Community including software partners writing development tools, middleware and drivers; customers creating IP building blocks such as interface IP; design services partners; and foundries.

Through its MIPS Alliance Program, Kitagawa explained that MIPS works with key partners to put together ‘best practices’ solutions that encompass recommended design techniques, interfaces and targeted reference designs in key market segments of security, graphics and video.

In the case of a graphics application, one such reference design would include recommendations for bus structures and how to connect those two pieces of IP together. In a set-top box application, where video performance is of the utmost importance, MIPS includes bus structures and latency-interrupt types of mechanisms.

Kitagawa stressed that MIPS has worked very, very closely with partners to develop optimal recommendations for each and every one of these application cases.

Differentiation by micromarket
While partnerships are a key way that IP vendors look to stand out from the crowd, each vendor also focuses on providing different aspects of IP.

ARM spans the widest range, from cores (generally offered in a synthesizable fashion) to other key blocks that are becoming performance-critical like graphics and video. It also provides fabric (interconnect infrastructure and bus interface that is the backbone of the system); and physical IP (from the acquisition of Artisan — targeted at addressing implementation complexities).

“Back in the day, the Artisan model was primarily geared around mature technologies,” Heinlein said. “Artisan pioneered the free library program – which was incredibly successful and still is – to gather a lot of customers in by having no upfront licensing fee.”

ARM still maintains that model today, but in the past several years the company has invested heavily in advanced technologies – 65nm to 28nm – realizing that customers have implementation challenges and really need a complete solution.

“Not only are we developing IP in general for those advanced technologies, but we’re also specifically focusing on the key performance critical subsystems of the ARM core. One of the things we are doing is developing what we call application-optimized/processor-optimized physical IP. Customers come to us and they say, ‘I need to implement a Cortex A9 core and I need to get the high megahertz. How can you help me?’ So we are developing the standard cell libraries and memory compilers they use but we’re also developing specifically-optimized standard cells that make the processor go faster, and specifically optimized memory instances that make it easier to get to high performance and low power,” Heinlein said.

“We are really focusing our efforts on all of the performance-critical subsystems of the SoC, which means the ARM core – the heart of the SoC, into the graphics subsystem which is performance-critical, into the interconnect within the chip, all the way out to the DDR. That path dominates the performance of the SoC. It’s also important to have USB, PCI Express and those interfaces, but there are a lot of providers that make that kind of IP, in fact, we are really deemphasizing those areas for our own development. We’re focusing on the core physical IP: standard cells, logic, memory compilers, I/O products, DDR – all of that is crucial for the performance of the SoC,” he added.

For Virage Logic, the company views its biggest differentiator from the competition as its processor offering that surrounds the host processor, Tanurhan said. “Today’s and tomorrow’s SoCs have multiple processors. One of our customers is using nearly 60 of our cores on a single chip. We co-exist very nicely because even on a cell phone, for the touchpad you need a processor, for the roller ball you need a processor, for the USB you need a processor, for the Bluetooth you need a processor, and there will be a host – that fight has to be decided between the two big guys.”

When it comes to MIPS, Kitagawa said the company differentiates itself in terms of what it offers to customers in major market segments, and in developing “true” partnerships with third party IP providers through its Alliance Program, whereby roadmaps are shared and work is done at the system level to solve engineering issues.

MIPS believes it brings the benefits of a one-stop-shop by working with its partners very closely to make sure everything is optimized. “We give the benefits of coming from a single company but offering choice to customers,” Kitagawa concluded.

Conclusion
As the implementation challenges growing ever more complex, so too will be the market strategies of vendors looking to meet the needs of customers. But what appears to be increasingly clear is that IP vendors can only get so far with their own differentiation and market brand. It now requires a much broader approach.

It’s no longer enough to just stake out a market and integrate all the pieces of IP together. Increasingly, the key to success appears to be a much deeper integration that extends beyond an IP company’s own product line to include the products of their ecosystem partners. That marks a fundamental change in the IP market, at once making it much more useful while ultimately blurring the lines between one IP company’s offerings and those of its partners.

By Ed Sperling
Moore’s Law marches on. Virage Logic rolled out its memory compilers and logic libraries for TSMC’s 28nm high-k/metal gate process. This follows Virage’s first 28nm test chip tapeouts late last year. Word on the street—from those willing to talk about it—is that 28nm is relatively straightforward from a feature-shrink standpoint, although power will still be an issue. But 22nm is giving everyone the chills.

Mentor Graphics rolled out a DO-254 platform with enhanced HDL coding. DO-254 is an FAA standard for complex hardware in airborne systems.

NTT Electronics created a graphics chip using Arteris’ network on chip technology. This is an interesting application for NoCs because of the high volume of traffic on a graphics chip. Graphics is one of those areas that is embarrassingly parallel, so adding order to the chaos of on-chip communications is vital.

RT-RK created a big-endian version of Android for the MIPS platform. There was already a little-endian version. Big endian and little endian were terms created years ago by Unix vendors, depending on whether you read zeros and ones from left-to-right or right-to-left. It was an analogy to the big end of the egg or the little end. It’s a good thing eggs aren’t round.

Sales are up everywhere. STMicroelectronics also adopted Mentor’s Veloce emulation platform for next-generation set-top box chips. It should be noted, however, that even though we insist on calling these set-top boxes, nothing can ever rest on a flat-panel TV. Perhaps we need a new name.

Also on the sales front, Cadence inked a deal with TSMC for integrated signoff at 65nm with synthesis, place and route and RC extraction. Cadence also won new business from HSilicon for mixed-signal and low-power tools,  and from LSI for mixed-signal technology.

And in the same vein, Aptina adopted Apache Design System’s analysis, optimization and signoff technology for its image sensors. Apache also started the year with record bookings and revenue for Q1. We like hearing that kind of news.

eSilicon and Brite Semiconductor joined Synopsys’ IP OEM partner program. This puts eSilicon into the same group as Open-Silicon and Global Unichip. Apparently this is a club you need to join if you build chips for other companies.

Global Unichip, meanwhile, also licensed ARM’s IP portfolio. This is an interesting company to watch because of TSMC’s hedged investment in a company that rivals eSilicon and Open-Silicon, both of which are TSMC customers. It’s like riding a bicycle on a narrow trail next to a precipice. You don’t want to make any sudden movements. http://www.arm.com/about/newsroom/global-unichip-licenses-comprehensive-arm-ip-portfolio.php

By Ed Sperling
eSilicon will acquire Silicon Design Solutions, which makes memory IP cores. SDS is headquartered in Silicon Valley, but it has design centers in Vietnam and Texas.

Apparently things were better than expected at Virage Logic. The company updated its guidance for the quarter, pushing its numbers upward by as much as $1 million. Executive chairman Daniel McCranie attributed the change to rapid integration of acquisitions, controlling spending and a “significant increase” in royalties. We all like that kind of news.

Synopsys rolled out DesignWare DDR multiPHY IP, fusing support for six different DDR standards in a single PHY. This is the IP version of a package deal. http://synopsys.mediaroom.com/index.php?s=43&item=789

Cadence won a deal with STMicroelectronics to use its OrCAD PSpice technology for evaluating analog and power ICs.

As strong as the FPGA market is in the United States and Europe, it’s exploding in places like China and India. Proof point: Actel’s 24 x 5 technical support. It’s not that chip engineers work the same kind of hours as software developers—the Mountain Dew swigging night owls. But they do work in a lot of different time zones these days.

By Ed Sperling

It was a busy week for Mentor Graphics. The company scored another DFM win, this time from SMIC, the Shanghai-based foundry. SMIC will use Calibre for signoff for 65nm and below. It also set up a shared emulation resource with Platform Computing.  And perhaps even more important, one of its development engineering managers, Vladimir Szekely won an award from the Hungarian Parliament for advanced transient temperature equipment.

Actel extended its SmartFusion FPGAs up into carrier-grade equipment with programmable ATCA systems, which is an interesting move for this market. In the past, most of the ATCA solutions involved swap-in modules in a standard chassis. This adds analog programmability for the first time through Actel’s Pigeon Point subsidiary.

Synopsys rolled out Design Compiler 2010 for its Galaxy flow. The company says the new tool will double the productivity of RTL synthesis and place and route.

Virage Logic teamed up with MIPS to offer optimized embedded memory IP for their joint customers. So who are the joint customers? Think set-top boxes and broadband.

Cadence added a couple dozen new companies to its ChipEstimate planning and IP portal. Virage and Xilinx ramped up their support.

eSilicon CEO Jack Harding was re-elected to the GSA board for the first time as a value chain producer, a new category created by the GSA to include eSilicon. It’s a good thing he got elected.

By Ed Sperling

Mentor’s Thomas Bollaert takes a look at what he calls modern Luddites and some of the change-averse comments he received on some customer visits. The Luddites, by the way, were a group of disgruntled English weavers who opposed mechanized looms in the early 1800s. (We looked it up.)

Along the same lines, Cadence’s Jack Erickson talks about the relationship between Madonna and chip design. Actually, Madonna has nothing to do with chip design. But think of how it might change if she did.

Andrew Piziali and Texas Instruments’ Jim Bondi, writing in Synopsys’ VMM Central, talk about getting the chip architect involved in the verification process. Sounds like a great way to make sure the chip can be verified relatively quickly. This is sort of like standing in someone else’s shoes when they’re two sizes too small.

Tets Maniwa, writing for Gabe on EDA, looks well beyond the presentation of next-generation tools for next-generation processes. It’s a great analysis of a lot of issues in SoC presented in very readable and digestible bites. Nice job.

Virage Logic’s Hezi Saar examines the rising risk of failure in the communications market, which is where the majority of leading-edge SoCs are going because those are the only markets that can justify the development cost with large enough volumes.

Cadence’s Samta Bansal takes a hard look at why 3D stacking has become such a hot topic and what it needs to move into the mainstream—lots of work.

Mentor’s John Day takes a stand on banning cell phones in cars. He’s against the ban because it will limit the safety advances that are in development. Interesting argument.

Cadence’s Tom Anderson, in the same vein, questions whether it’s good for participants to use social networking while they’re attending an Accellera meeting. In our view, no, but anyone over 35, not to mention people who occasionally use multi-syllabic words like disintermediation, will miss the importance of this social networking revolution.

Daniel Nenni takes a look at Mentor’s acquisition of Pextra for 3D field solver technology and why you should care. He even predicted the acquisition, so kudos to Mr. Nenni for that one (unless, of course, Mentor got the idea from reading his blog). Field solver technology is becoming increasingly important technology below 40nm for effective circuit simulation.

Cadence’s Jason Andrews digs down into accessing physical memory and registers from virtual platforms. There’s some good, solid technical insight here.

And last but not least, Mentor’s Jon McDonald compares ESL to an insurance policy and asks how lucky you feel. It sounds a lot like a line out of Dirty Harry movie: “You’ve got to ask yourself one question: ‘Do I feel lucky? Well, do ya punk?’”