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Blog Review – Monday, June 26, 2017

Monday, June 26th, 2017

This week, hot on the heels of DAC, a review of the Austin event; Intel administers a dose of precision medicine; Challenges for drivers; How to choose between a GPU or FPGA and a blockchain reaction for the IoT

DAC 2017 took place in Austin, Texas, and Paul MeLellan, Cadence Design Systems, was there and has collated a wide-ranging report, with day-by-day news, including bats and bagpipes from the 54 th incarnation of the event.

Writing from a very personal viewpoint, Bryce Olson, Intel, advocates precision medicine, and looks at Intel’s scalable reference architecture to speed up the research and answers in medical care.

Vehicle safety is critical, and Stephen Pateras, Mentor Graphics, looks at self-test and monitoring in autonomous cars, using the Tessent MissionMode architecture. He explains in a clear, detailed manner, the IC test capabilities and simulation for self-driving cars.

Still with vehicle design, Robert Vamosi, Synopsys, flags up the security hazards around the connected car as sensors proliferate and hackers ramp up their assaults. He advocates software security and the communication protection afforded by the IEEE 802.11p protocol.

A handy white paper is brought to our attention by Steve Leibson, Xilinx, for those deciding whether a GPU is better than an FPGA in cloud computing, machine leaning, video and image processing applications.

I learned a couple of things from Christine Young, Maxim Integrated this week. One is that there is a job title of ‘chief IoTologist’, the other was to put the term ‘blockchain’ into context for the IoT. She reports from the IoT World Conference about how blockchain, using advanced cryptography, provides a “tamper-proof distributed record of transactions” and how the IoT Alliance is occupied in developing a shared blockchain protocol as a common identifier to secure IoT products.

Starstruck John Blyler, looks at the reality behind the stardust and conducts an interview with Dr Clifford Johnson, physicist at University of Southern California and script adviser for the National Geographic Channel’s TV program, Genius, about Albert Einstein.

Blog Review – Monday, April 10, 2017

Monday, April 10th, 2017

This week, there are traps and lures in the IoT, as discussed by ARM and Maxim Integrated; Xilinx believes a video tutorial is a good use of time; Get cosy with SNUG for some insight; and ON Semiconductor is keeping an eye on you

Beware of delivery men bearing IoT gifts, warns, Donnie Garcia, ARM, who also looks at trap doors and NXP’s Kinetis KBOOT bootloader to foil a new attack vector and advertise a related webinar on April 25.

Nagging parents had the right idea, decides Russ Klein, Mentor Graphics, remembering entreaties to turn off lights, and whose energy saving advice he now applies to SoCs and embedded systems, with the help of the Veloce emulator.

Gabe Moretti, Chip Design, gets a bit saucy, trying to figure just what is Portable Stimulus. He gets down to the nitty gritty with how the Accellera System Initiative can help, but still believes some areas need to attended to. Let’s hope the industry pays heed.

More warnings from Kris Ardis, Maxim Integrated, and connected devices. While a Jacquard print may not be to everyone’s taste, the idea of protecting the IoT and its data has universal appeal.

The appeal of Agile design is not lost on Randy Smith, Sonics, who writes about the concept and Agile software development. He deftly dives into advances in Agile hardware design and IC methodology for Agile techniques – keeping every design engineer on their toes.

A visit to ISC West, the security expo, has made Jason Liu, ON Semiconductor, think about surveillance systems, as he throws a spotlight on one of the company’s introductions.

14 minutes does not sound like a long time to pack in all you need to know about Zynq UltraScale+ MPSoCs and Vivado Design Suite, but Steve Leibson, Xilinx points readers towards an interesting, informative video, which he describes as a fast and painless way to see the development tools used in a fully operation system.

It sounds like a self-satisfied neck-warmer, but SNUG (Synopsys User Group) events can be informative. Tom De Schutter attended the one in Silicon Valley and relates what he learned from the technical track with experts from ARM, NVIDIA, Intel and Synopsys about prototyping latch-based designs, ARM CPU and GPU increasing densities and more besides.

Striving to improve the lot of IoT designers, John Blyler, Embedded Systems, talks to Jim Bruister, SOC Solutions, about markets, licensing, open source and five elements that will drive improvement.

Compiled by Caroline Hayes, Senior Editor

Cadence Launches New Verification Solutions

Tuesday, March 14th, 2017

Gabe Moretti, Senior Editor

During this year’s DVCon U.S. Cadence introduced two new verification solutions: the Xcelium Parallel Simulator and the Protium S1 FPGA-Based Prototyping Platform, which incorporates innovative implementation algorithms to boost engineering productivity.

Xcelium Parallel Simulator

.The new simulation engine is based on innovative multi-core parallel computing technology, enabling systems-on-chip (SoCs) to get to market faster. On average, customers can achieve 2X improved single-core performance and more than 5X improved multi-core performance versus previous generation Cadence simulators. The Xcelium simulator is production proven, having been deployed to early adopters across mobile, graphics, server, consumer, internet of things (IoT) and automotive projects.

The Xcelium simulator offers the following benefits aimed at accelerating system development:

  • Multi-core simulation improves runtime while also reducing project schedules: The third generation Xcelium simulator is built on the technology acquired from Rocketick. It speeds runtime by an average of 3X for register-transfer level (RTL) design simulation, 5X for gate-level simulation and 10X for parallel design for test (DFT) simulation, potentially saving weeks to months on project schedules.
  • Broad applicability: The simulator supports modern design styles and IEEE standards, enabling engineers to realize performance gains without recoding.
  • Easy to use: The simulator’s compilation and elaboration flow assigns the design and verification testbench code to the ideal engines and automatically selects the optimal number of cores for fast execution speed.
  • Incorporates several new patent-pending technologies to improve productivity: New features that speed overall SoC verification time include SystemVerilog testbench coverage for faster verification closure and parallel multi-core build.

“Verification is often the primary cost and schedule challenge associated with getting new, high-quality products to market,” said Dr. Anirudh Devgan, senior vice president and general manager of the Digital & Signoff Group and the System & Verification Group at Cadence. “The Xcelium simulator combined with JasperGold Apps, the Palladium Z1 Enterprise Emulation Platform and the Protium S1 FPGA-Based Prototyping Platform offer customers the strongest verification suite on the market”

The new Xcelium simulator further extends the innovation within the Cadence Verification Suite and supports the company’s System Design Enablement (SDE) strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently. The Verification Suite is comprised of best-in-class core engines, verification fabric technologies and solutions that increase design quality and throughput, fulfilling verification requirements for a wide variety of applications and vertical segments.

Protium S1

The Protium S1 platform provides front-end congruency with the Cadence Palladium Z1 Enterprise Emulation Platform. BY using Xilinx Virtex UltraScale FPGA technology, the new Cadence platform features 6X higher design capacity and an average 2X performance improvement over the previous generation platform. The Protium S1 platform has already been deployed by early adopters in the networking, consumer and storage markets.

Protium S1 is fully compatible with the Palladium Z1 emulator

To increase designer productivity, the Protium S1 platform offers the following benefits:

  • Ultra-fast prototype bring-up: The platform’s advanced memory modeling and implementation capabilities allow designers to reduce prototype bring-up from months to days, thus enabling them to start firmware development much earlier.
  • Ease of use and adoption: The platform shares a common compile flow with the Palladium Z1 platform, which enables up to 80 percent re-use of the existing verification environment and provides front-end congruency between the two platforms.
  • Innovative software debug capabilities: The platform offers firmware and software productivity-enhancing features including memory backdoor access, waveforms across partitions, force and release, and runtime clock control.

“The rising need for early software development with reduced overall project schedules has been the key driver for the delivery of more advanced emulation and FPGA-based prototyping platforms,” said Dr. Anirudh Devgan, senior vice president and general manager of the Digital & Signoff Group and the System & Verification Group at Cadence. “The Protium S1 platform offers software development teams the required hardware and software components, a fully integrated implementation flow with fast bring-up and advanced debug capabilities so they can deliver the most compelling end products, months earlier.”

The Protium S1 platform further extends the innovation within the Cadence Verification Suite and supports the company’s System Design Enablement (SDE) strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently. The Verification Suite is comprised of best-in-class core engines, verification fabric technologies and solutions that increase design quality and throughput, fulfilling verification requirements for a wide variety of applications and vertical segments.

Blog Review – Monday, January 23, 2017

Monday, January 23rd, 2017

This week’s blogs show the human face of automated driving; and why energy should be taken seriously. There is lift-off for SpaceX to bring more satellite comms and a poetic turn, in the style of Rudyar Kipling’s classic poem.

There is a human element to automated driving, namely Human Machine Interface (HMI) and Jack Weast, Intel, uses his second blog post to examine how and why it can be used. He promises more in part three into the company’s research.

Energy is a serious business, says Grant Pierce, Sonics, and the electronics industry must shoulder some responsibility for power savings. The company, with Semico Research is conducting a survey and wants your help into understanding today’s and tomorrow’s power requirements.

Boosting the satellites to provide point-to-point communications, the SpaceX Falcon 9 rocket put the first 10 Iridium NEXT satellites into Low Earth Orbit (LEO), equipped with Xilinx space-grade Virtex-5QV FPGAs to implement the satellites’ On Board Processor (OBP) hardware. Steve Liebson, Xilinx, includes a link to a video describing the constellation and the launch.

Celebrating the relationship with Ericsson, Dassault Systèmes’ Olivier Ribet, looks at how the latter’s Networked Society will transform the way we interact with the world around us and meet technology challenges, such as 5G, IoT and the cloud.

Moving to 10nm and lower process geometries pushes the boundaries of FinFET and the custom layout flow and this means trouble ahead, warns Graham Etchells.

A touch of culture, with a poem “wot I wrote” by Keith Hanna, Mentor Graphics. He deftly tackles Computational Fluid Dynamics (CFD) as Rudyard Kipling might.

Image data and the mysteries of how to create, access and use a Qimage to greatest effect is detailed by Laszlo Agocs, Qt, with three case studies to illustrate what can be done.

A sharp video addressing the interconnect verification challenges is hosted by Nimrod Reiss. Cadence’s Corrie Callenbach has found and highlighted the video.

Caroline Hayes, senior editor

Blog Review – Monday 07 November 2016

Monday, November 7th, 2016

Browsing the MIT Library; AI and HPC for cancer breakthroughs; FPGAs on Mars; Romancing ISO 26262; It’s IoT conference season; Who’s going to pay?

For smart and connected IoT devices, Intel has introduced the Intel Atom processor E3900 and Ken Caviasca, Intel explains how the series brings computing power nearer to the role of the sensor.

Crash scenes from Mars, as taken by the Mars Reconnaissance Orbiter’s High Resolution Imaging Science Experiment (HiRISE) reveal features previously unseen on the planet. Steve Leibson, Xilinx, explains how we have FPGAs to thank. (For the images, not the crash!)

Ahead of GE’s Minds & Machines Conference (November 15-16, San Francisco) Lane Lewis, Ansys, celebrates the marriage of the Simulation Platform and Predix Platform to create a profitable asset health monitoring and the industrial IoT.

As mobile payment matures, Martin Cox, Rambus Bell ID, identifies that tokenization is becoming a hot topic. His blog explains the role of the company’s Token Gateway as a means to integrate multiple mobile payment schemes. No excuse not to get a round of drinks in now.

Moving automotive and safety into the realm of Dungeons and Dragons, Paul McLellan, Cadence, reviews the recent DVCon Europe and how ISO 26262 – the critical safety standard – became a theme, but not necessarily one to dread and fear or avoid. Like St George, you just have to grit your teeth and tackle it head-on, to find the pot of gold that is critical safety design success.

Fresh from IoT Planet in Grenoble, France, Andrew Patterson, Mentor Graphics, is occupied by two topics – connectivity and security. He shares some interesting thoughts and statistics around these gleaned from the event.

Fascinating insights into the world of bio-medicine and computational bio-medicine are provided by Dr Michael J McManus, Intel. He explains how Artificial Intelligence (AI) and High Performance Computing (HPC) are used by researchers to analyze data and predicts an era of revolutionary cancer breakthroughs, of both drug development structures and genome analytics running on a single Intel cluster using Intel Xeon, Intel Xeon Phi processors and Intel Omni-Path architecture.

There is a fascinating collection of rare books at MIT, exhibited to mark Ada Lovelace Day. For those can’t walk the aisles of the MIT Libraries, Stephen Skuce, MIT Libraries, shows us through some of the collection relating to women who have contributed to science, math and engineering with its annual celebration of the history of women in the STEM (Science Technology, Engineering and Mathematics) subjects.

Caroline Hayes, Senior Editor

Blog Review –Monday, October 24 2016

Monday, October 24th, 2016

The how, what and why of time-of-flight sensors; Conference season: ARM TechCon 2016 and IoT Solutions Congress; Save time on big data analysis; In praise of FPGAs; Is it time for augmented and virtual reality?

Drastically reducing big data analysis is music to a data scientist’s ears. Larry Hardesty reports on researchers at MIT (Massachusetts Institute of Technology) have presented an automated system that can reduce preparation and analysis from months to just hours.

Keeping an eye on the nation’s bank vaults, Robert Vamosi, Synopsys, looks at the what bank regulators are doing to ramp up cybersecurity.

If you can’t head to Barcelona, Spain this week for IoT Solutions World Congress (October 25-27), Jonathan Ballon, Intel, reveals what the company will unveil, including a keynote: IoT: From Hype to Reality, what 5G means, smart cities and a hackathon.

Tired of the buzz, and seeking enlightenment, Jeff Bier, Berkeley Design, delves into just what is augmented reality and virtual reality. He examines hardware and software, markets and what is needed for widespread adoption.

Closer to home, 2016 ARM TechCon, in Santa Clara, California (October 25 – 27), Phil Brumby, Mentor Graphics, offers a heads-up on its industrial robot demo, using Nucleus RTOS separated by ARM TrustZone, and the ECU (Engine Control Unit) demo in a Linux-hosted In-Vehicle Infotainment (IVI) system. There is also a technical session: Making Sure your UI makes the most of the ARM-based SoC (Thurs, 10.30am, Ballroom E)

The role of memory is reviewed by Paul McLellan, Cadence Design System, as he discusses MemCon keynotes by Hugh Durdan, VP of the IP Group and Steve Pwalowski, VP of Advanced Computing Solutions at Micron. There is comprehensive pricing strategy and a look at industry trends.

A teardown of the Apple iPhone 7, by Dick James, Chipworks, links STMicroelectronics’ time-of-flight sensors with the Starship Enterprise. The blog has a comprehensive answer to questions such as what are these sensors and why are they in phones.

If the IoT is flexible, Zibi Zalewski, Aldec, argues, then FPGAs can tailor solutions without major investments in an ASIC. He takes Xilinx’s Zynq-7000 All-Programmable SoC as a starting point and illustrates how it can boost performance for IoT gateways.

Elegantly illustrating how multiple Eclipse projects can be run on a single microcontroller with MicroEJ, Charlottem, ARM, runs through a connected washing machine that can communicate via Bluetooth, MQTT, Z-Wave and LWM2M.

Caroline Hayes, Senior Editor

Blog Review – Monday, October 10, 2016

Monday, October 10th, 2016

This week, bloggers look at the newly released ARM Cortex-R52 and its support, NVIDIA floats the idea of AI in automotives, Dassault Systèmes looks at underwater construction, Intrinsic-ID’s CEO shares about security, and there is a glimpse into the loneliness of the long distance debugger

There is a peek into the Xilinx Embedded Software Community Conference as Steve Leibson, Xilinx, shares the OKI IDS real-time, object-detection system using a Zynq SoC.

The lure of the ocean, and the glamor of Porsche and Volvo SUVs, meant that NVIDIA appealed to all-comers at its inaugural GPU Technology Conference Europe. It parked a Porsche Macan and a Volvo XC90 on top of the Ocean Diva, docked at Amsterdam. Making waves, the Xavier SoC, the Quadro demonstration and a discussion about AI in the automotive industry.

Worried about IoT security, Robert Vamosi, Synopsys, looks at the source code that targets firmware on IoT devices, and fears where else it may be used.

Following the launch of the ARM Cortex-R52 processor, which raises the bar in terms of functional safety, Jason Andrews looks at the development tools available for the new ARMv8-R architecture, alongside a review of what’s new in the processor offering.

If you are new to portable stimulus, Tom A, Cadence, has put together a comprehensive blog about the standard designed to help developers with verification reuse, test automation and coverage. Of course, he also mentions the role of the company’s Perspec System Verifier, but this is an informative blog, not a marketing pitch.

Undersea hotels sounds like the holiday of the future, and Deepak Datye, Dassault Systèmes, shows how structures for wonderful pieces of architecture can be realized with the company’s , the 3DExperience Platform.

Capturing the frustration of an engineer mid-debug, Rich Edelman, Mentor Graphics, contributes a long, blow-by-blow account of that elusive, thankless task, that he names UVM Misery, where a customer’s bug, is your bug now.

Giving Pim Tuyls, CEO of Intrinsic-ID, a grilling about security, Gabe Moretti, Chip Design magazine, teases out the difference between security and integrity and how to increase security in ways that will be adopted across the industry.

Blog Review – Monday, June 13, 2016

Monday, June 13th, 2016

DAC 2016 highlights; Medical technology and IoT; Autonomous car market races ahead; Remote controlled beer; Secure connectivity

Distinguishing between Big Data and Business Intelligence, ScientistBob, Intel, identifies a ‘watershed’ moment for Big Data and Intel’s steps with Intel Xeon processors to deliver the next step in data analytics.

In response to FCC regulations, the prpl Foundation addresses next-generation security for connected devices. Alexandru Voica, Imagination Techologies, has collected some useful information (demo, white paper, devices, kits and links) to show the progress made.

A fascinating medical application is detailed in Steve Leibso, Xilinx, as he describes how the Xynq-7000 SoC in an eye-tracking computer interface. The video is a little ‘salesy’ and could have benefitted from some more examples of use rather than talking heads but has some practical engineering information about how the processing moves to the SoC.

Continuing the medical theme, Thierry Marchal, ANSYS, tantalizes readers ahead of a medical IoT webinar (June 22) by Cambridge Consultants. He has some interesting statistics to put the topic into context, some graphics and an exploration of the communications protocols involved.

The 53 rd DAC saw ARM launch ARM Artisan physical IP, including POP IP, targeting mainstream mobile designs. Brian Fuller, ARM, adds some meat to the bones with comment from Will Abbey, general manager, ARM’s Physical Design Group.

Automotive design at DAC captured the interest of Christine Young, Cadence, who reports on the keynote by Lars Reger, CTO Automotive Business Unit, NXP Semiconductors. She looks at the security issues for vehicles from the family car to trucks.

Beer that comes to you takes the slog out of summer al fresco dining, doesn’t it? The Atmel team details the use of an ATmefa8 MCU for a remote controlled beer crate, with a link to the build recipe list.

Here in the UK, we are knee-deep in discussions about how to get on with our neighbours as an EU membership referendum looms. A model for happy international relations is here in the blog by Devi Keller, Semiconductor Industry Association, which records the 20 years of the World Semiconductor Council (WSC).

A trip to Detroit for Robert Bates, Mentor Graphics, for its IESF conference, was a source of great material for all things related to autonomous cars. Keynotes and networking led him to consider safety and neural network questions around the technology.

Putting it all into practise, the first Self Racing Cars track event is gleefully reported by Danny Shapiro, Nvidia. There are some great images capturing the spirit of a ground-breaking event. Last weekend a momentous event in the motorsports and automotive world took place. Of course, the company’s technology is used and there is a handy list of what was used and where.

Caroline Hayes, Senior Editor

Blog Review – Tuesday, May 31 2016

Tuesday, May 31st, 2016

Security issues around IoT and maritime vessels; CCIX Consortium accelerates data centers; Cheers for metering; Noise integrity in ADAS; Virtual Reality in practice

Protecting IoT devices is clearly and elegantly outlined by Jim Wallace, ARM, he includes illustrations, a lot of information and guidelines on advice on how security can produce new business models.

Accelerating data centers always raises interest and when names like AMD, ARM, Huawei, IBM, Mellanox, Qualcomm, and Xilinx come together. Steve Liebson, Xilinx, describes how the companies, via the CCIX (Cache Coherent Interconnect for Accelerators) Consortium are developing a single interconnect technology specification whereby processors using different instruction set architectures can share data with accelerators and enable efficient heterogeneous computing to improve efficiency.

Advocating an alternative to the plan to drink beer when the fresh water runs out, David Andeen, Maxim explains the importance of an ultrasonic water meter which can accelerate design cycles and reduce the cost of meters.

All in the name of research, Alexandru Voica, Imagination, tries his hand at Daydream, the Virtual Reality (VR) platform built on Android N and outlines the rules of VR.

Another cyber threat is identified by Robert Vamosi, Synopsys. His blog looks at research from Plymouth University and how vulnerable marine vessels can be at risk.

The undeniable increase in Advanced Driver Assistance Systems (ADAS) needs careful design consideration, and Ravi Ravikumar, ANSYS, discusses how the ANSYS CPS simulation helps power noise integrity to be met. His blog is informative, with some clear graphics to illustrate ADAS design.

For a quick catch-up on USB 3.1 and the Type-C connector, turn to Chris A Ciufo, eecatalog, for a quick reference guide. He includes some handy links for extra reading.

A review of the Bangalore, India, Design&Reuse event is provided by Steve Brown, Cadence Design Systems. A rundown of keynotes ends with a head-up for the next event.

Blog Review Monday April 11 2016

Monday, April 11th, 2016

Mbed development board seeks therapy; in praise of HPC; IoT security – can it be improved?; EDAC name change; acquisition fever runs high

Checking and testing safety critical systems can be performed using the Zynq-7000 All Programmable SoC (AP SoC) with dual ARM Cortex-A9 processors, and dual Neon FPUs. Austin, Xilinx, explains the routine.

Therapy from an mbed development board may not threat therapists just yet, but ELIZA, the computer program that simulates a psychotherapist, is now available for the mbed platform. The obvious question to ask Wilfred Nilsen, ARM, is “How do you feel about that?”

Who needs High Performance Computing (HPC), asks Wim Slagter, Ansys. He addresses computing as a strategic asset, scalability benefits and what to do with a server cluster.

The Internet of Things (IoT) security market will be worth $28.90 billion by 2020, yet it is flawed, argues an unattributed blog from Rambus. Interviews with Simon Blake-Wilson and Ted Harrington, Rambus, assess how much ground needs to be made up.

Still with security, Robert Vamosi, Synopsys reports on the Synopsys and Underwriter’s Laboratory (UL) collaboration to create the UL Cybersecurity Assurance Program (UL CAP). The aim is to increase transparency and confidence in the security of network-connectable devices using expertise from both camps.

Looking ahead to the connected car, Andrew Macleod, Mentor Graphics, considers what will be coming together for a centralized processing system, handling communications and autonomous driving functions. The vehicle’s systems will be consolidated, but how best to achieve that is up for debate.

It may take some people a while to adjust, but the EDA Consortium has changed its name to the Electronic System Design Alliance. Gabe Moretti, Chip Design Magazine, looks at the whys and wherefores behind the change and the expertly analyses the Alliance’s expanded charter.

Intel has bought Yogitech, the functional safety company and Ken Caviasca, Intel, looks at what this means for the company and, in particular, its IoT offering.

Still with acquisitions, it is all getting a bit too much for Chris Ciufo, eecatalog, who traces some recent ‘musical chairs’ before focusing on what the Mercury Computer purchase of three Microsemi businesses will meet for the military market.

Caroline Hayes, Senior Editor

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