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Blog Review – Monday, November 6, 2017

Monday, November 6th, 2017

This week, we find that ANSYS gets hyper about Hyperloop development, Xilinx puts its mind to networks, Maxim supports factory automation and NXP, Mentor and ON Semiconductor explain why and how a product can be used.

A positively upbeat tone is set by Maxim Integrated’s Jeff DeAngelis, as he looks at how Industry 4.0 and automation is bringing back jobs. He looks at how being competitive through automation is leading to reshoring activity.

The now infamous ‘Jeep hack’ is the starting point for Timo van Roermund, the security architect at NXP considers what safeguards are needed and how the car domain needs to be re-thought for security on the roads. As well as citing several NXP products, there are also some useful links.

There’s a new look to the Mentor Graphics blogs and Michael Nopp uses it to good effect to take us through the company’s PADS Professional. His use of clear, colourful graphics adds to a simply told design guide.

Who isn’t super-excited about Hyperloop technology at the moment? Adora Anound Tadros, HyperXite guests on the ANSYS site to tell us how the team from University of California, Irvine, used simulation tools for its entry in the SpaceX Hyperloop Pod competition. The team is gaining momentum and was in the top six of this year’ competition and is planning to compete again in 2018 – with a self-propulsion pod design.

Smile, you’re on camera, says an image-conscious Jason Liu, ON Semiconductor. He looks at the changing roles of cameras in our lives and introduces the company’s digital image sensor.

Another current favourite topic is neural networks. Steve Leibson proudly relates how a team at the University of Birmingham in the UK has implemented a deep recurrent neural network on a Xilinx Zynq Z-7020 SoC using the Python programming language.

Caroline Hayes, Senior Editor

Blog Review – Monday, October 23, 2017

Monday, October 23rd, 2017

This week blogs are focused on health and AI, from remote care for the elderly to asthma inhalers using machine learning; plus sewer cleaning and multimedia SoCs

The autonomous car can reduce hospital visits by visiting patients – but won’t that put more cars on the road? David P Ryan, Intel advocates a delivery service for the next generation of healthcare.

Taking an engineer’s view on every object, Peter Ferguson, Arm, looks at the asthma inhaler and takes a deep breath at the Amiko ‘smart’ inhaler which uses an Arm Cortex-M processor.

Former Cadence employee, Vishal Kapoor, presented Preparing for the Cognitive Era, at San Jose State University. Paul McLellan, Cadence reports on why Kapoor is worried about the amount of data companies are collecting.

The importance of video content, used in augmented reality devices and 4K UHD TV, relies on efficient multimedia SoCs. Richard Pugh, Mentor, looks at some of the ways and means to verify the data and cites an interesting example of a customer developing a drone.

No wonder it’s called Solo – who would want to join RedZone Robotics’ autonomous sewer-inspection robot (called Solo)? Steve Leibson, Xilinx, uncovers the clean workings of the robot that crawls and records where others refuse to go, and explains how it uses Spartan FPGA for image processing and for AI. (There’s a video too – but it’s not a mucky one!)

Enough about the IoT, says Jim Harrison, Lincoln Technology Communications, guest blogging for Maxim Integrated. What about how to connect millions of sensors and actuators? He lays out a comprehensive ‘shopping list’ of long range wireless comms and connection options to help speed up the IoT conversation.

Coming full circle, Marc Horner, ANSYS, relates the case study of computational modeling for insulin delivery systems.

Caroline Hayes, Senior Editor

Blog Review – Monday, August 14, 2017

Monday, August 14th, 2017

This week, the blogsphere reveals how FPGAs adopt a MeerKAT stance; OML brings life to Industry 4.0; Wearable pairing boosts charging and rigid-flex PCB design tips

A keen advocate of rigid-flex PCB design, Alexsander Tamari, Altium, offers sound design advice for the routing challenges that it may present. There is a link to an informative white paper too.

We love wearables but charging devices wirelessly can present problems, but luckily Susan Coleman, ANYS, is able to describe the company’s recent collaboration with RF2ANTENNA. She describes with tips for efficiency improvements using its tools.

Another classic challenge is taken on by Arthur Schaldenbrand, Cadence. He continues his analog design series and looks at process variation, and countering die costs, power dissipation, with reference to the use of Monte Carlo analysis.

Chip Design’s John Blyler talks to Mentor’s Director of Product Management, Warren Kurisu, about a biometrics game and increased productivity using the Cloud.

Discovering new galaxies is exciting but is demanding on processing power and memory speeds. Steve Leibson, Xilinx, reflects on what the MeerKAR radio telescope has achieved and how FPGAs have played a part.

Ruminating on this year’s SMT Hybrid Packaging event, Danit Atar, Mentor Graphics, reviews what she claims is the world’s first IoT live public demonstration of a manufacturing line, and how Open Manufacturing Language (OML) bring Industry 4.0 to life.

Software integrity is never far from an engineer’s mind, and David Benas, Synopsys, presents a compelling argument for implementing security measures into the software development life cycle (SDLC) from start to finish.

By Caroline Hayes, Senior Editor

Blog Review – Monday, July 24, 2017

Monday, July 24th, 2017

Let’s hear it for High Fidelity Gaming and it’s all about the IoT, with PCB schematic tips from Mentor and security from Maxim; Inside NI’s 5G test lab and hope for Parkinson’s Disease research

Serious gamers are intriguing Freddi Jeffries, ARM. She looks at High Fidelity Mobile Gaming (HFMG) and who’s adopting it and where. Can mobile devices, based on Mali graphics processing units (GPUs) take on the console market?

A personal and heart-felt post by Altium Designer, Altium, looks at medical advances in treating Parkinson’s Disease. An overview of research by assorted technology companies manages to combine various uses for spoons, concludes with a gentle plug for PCB design software.

Stil with PCBs, John McMillan, Mentor Graphics Design presents part four of an IoT PCB design-themed series. The topic is schematic and layout design, from creating the schematic to component placement and constraint management for effective manufacture.

IoT security is keeping Christine Young, Maxim Integrated occupied – she is keeping busy finding out the scale of cybercrime, and the worrying lack of action companies to take steps for security. She flags up a free webinar on how to safeguard connected devices.

Taking a practical approach is applauded by Michael DeLuca, ON Semiconductor. He likes the attitude of the Institute of Space Systems (IRS) at the University of Stuttgart, whose students are preparing to launch its Flying Laptop satellite.

Taking a sneaky peek at the National Instruments’ 5G Innovation Lab, Steve Leibson, Xilinx, celebrates the company’s Virtex-7 and Kintex-7 FGPAs use in Verizon’s 5GTF (Verizon 5G Technology Forum) test equipment. The Forum is developing a 28/39GHz wireless communications platform to replace fiber in fixed-wireless applications.

By Caroline Hayes, Senior Editor

Blog Review – Monday, June 26, 2017

Monday, June 26th, 2017

This week, hot on the heels of DAC, a review of the Austin event; Intel administers a dose of precision medicine; Challenges for drivers; How to choose between a GPU or FPGA and a blockchain reaction for the IoT

DAC 2017 took place in Austin, Texas, and Paul MeLellan, Cadence Design Systems, was there and has collated a wide-ranging report, with day-by-day news, including bats and bagpipes from the 54 th incarnation of the event.

Writing from a very personal viewpoint, Bryce Olson, Intel, advocates precision medicine, and looks at Intel’s scalable reference architecture to speed up the research and answers in medical care.

Vehicle safety is critical, and Stephen Pateras, Mentor Graphics, looks at self-test and monitoring in autonomous cars, using the Tessent MissionMode architecture. He explains in a clear, detailed manner, the IC test capabilities and simulation for self-driving cars.

Still with vehicle design, Robert Vamosi, Synopsys, flags up the security hazards around the connected car as sensors proliferate and hackers ramp up their assaults. He advocates software security and the communication protection afforded by the IEEE 802.11p protocol.

A handy white paper is brought to our attention by Steve Leibson, Xilinx, for those deciding whether a GPU is better than an FPGA in cloud computing, machine leaning, video and image processing applications.

I learned a couple of things from Christine Young, Maxim Integrated this week. One is that there is a job title of ‘chief IoTologist’, the other was to put the term ‘blockchain’ into context for the IoT. She reports from the IoT World Conference about how blockchain, using advanced cryptography, provides a “tamper-proof distributed record of transactions” and how the IoT Alliance is occupied in developing a shared blockchain protocol as a common identifier to secure IoT products.

Starstruck John Blyler, looks at the reality behind the stardust and conducts an interview with Dr Clifford Johnson, physicist at University of Southern California and script adviser for the National Geographic Channel’s TV program, Genius, about Albert Einstein.

Blog Review – Monday, April 10, 2017

Monday, April 10th, 2017

This week, there are traps and lures in the IoT, as discussed by ARM and Maxim Integrated; Xilinx believes a video tutorial is a good use of time; Get cosy with SNUG for some insight; and ON Semiconductor is keeping an eye on you

Beware of delivery men bearing IoT gifts, warns, Donnie Garcia, ARM, who also looks at trap doors and NXP’s Kinetis KBOOT bootloader to foil a new attack vector and advertise a related webinar on April 25.

Nagging parents had the right idea, decides Russ Klein, Mentor Graphics, remembering entreaties to turn off lights, and whose energy saving advice he now applies to SoCs and embedded systems, with the help of the Veloce emulator.

Gabe Moretti, Chip Design, gets a bit saucy, trying to figure just what is Portable Stimulus. He gets down to the nitty gritty with how the Accellera System Initiative can help, but still believes some areas need to attended to. Let’s hope the industry pays heed.

More warnings from Kris Ardis, Maxim Integrated, and connected devices. While a Jacquard print may not be to everyone’s taste, the idea of protecting the IoT and its data has universal appeal.

The appeal of Agile design is not lost on Randy Smith, Sonics, who writes about the concept and Agile software development. He deftly dives into advances in Agile hardware design and IC methodology for Agile techniques – keeping every design engineer on their toes.

A visit to ISC West, the security expo, has made Jason Liu, ON Semiconductor, think about surveillance systems, as he throws a spotlight on one of the company’s introductions.

14 minutes does not sound like a long time to pack in all you need to know about Zynq UltraScale+ MPSoCs and Vivado Design Suite, but Steve Leibson, Xilinx points readers towards an interesting, informative video, which he describes as a fast and painless way to see the development tools used in a fully operation system.

It sounds like a self-satisfied neck-warmer, but SNUG (Synopsys User Group) events can be informative. Tom De Schutter attended the one in Silicon Valley and relates what he learned from the technical track with experts from ARM, NVIDIA, Intel and Synopsys about prototyping latch-based designs, ARM CPU and GPU increasing densities and more besides.

Striving to improve the lot of IoT designers, John Blyler, Embedded Systems, talks to Jim Bruister, SOC Solutions, about markets, licensing, open source and five elements that will drive improvement.

Compiled by Caroline Hayes, Senior Editor

Cadence Launches New Verification Solutions

Tuesday, March 14th, 2017

Gabe Moretti, Senior Editor

During this year’s DVCon U.S. Cadence introduced two new verification solutions: the Xcelium Parallel Simulator and the Protium S1 FPGA-Based Prototyping Platform, which incorporates innovative implementation algorithms to boost engineering productivity.

Xcelium Parallel Simulator

.The new simulation engine is based on innovative multi-core parallel computing technology, enabling systems-on-chip (SoCs) to get to market faster. On average, customers can achieve 2X improved single-core performance and more than 5X improved multi-core performance versus previous generation Cadence simulators. The Xcelium simulator is production proven, having been deployed to early adopters across mobile, graphics, server, consumer, internet of things (IoT) and automotive projects.

The Xcelium simulator offers the following benefits aimed at accelerating system development:

  • Multi-core simulation improves runtime while also reducing project schedules: The third generation Xcelium simulator is built on the technology acquired from Rocketick. It speeds runtime by an average of 3X for register-transfer level (RTL) design simulation, 5X for gate-level simulation and 10X for parallel design for test (DFT) simulation, potentially saving weeks to months on project schedules.
  • Broad applicability: The simulator supports modern design styles and IEEE standards, enabling engineers to realize performance gains without recoding.
  • Easy to use: The simulator’s compilation and elaboration flow assigns the design and verification testbench code to the ideal engines and automatically selects the optimal number of cores for fast execution speed.
  • Incorporates several new patent-pending technologies to improve productivity: New features that speed overall SoC verification time include SystemVerilog testbench coverage for faster verification closure and parallel multi-core build.

“Verification is often the primary cost and schedule challenge associated with getting new, high-quality products to market,” said Dr. Anirudh Devgan, senior vice president and general manager of the Digital & Signoff Group and the System & Verification Group at Cadence. “The Xcelium simulator combined with JasperGold Apps, the Palladium Z1 Enterprise Emulation Platform and the Protium S1 FPGA-Based Prototyping Platform offer customers the strongest verification suite on the market”

The new Xcelium simulator further extends the innovation within the Cadence Verification Suite and supports the company’s System Design Enablement (SDE) strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently. The Verification Suite is comprised of best-in-class core engines, verification fabric technologies and solutions that increase design quality and throughput, fulfilling verification requirements for a wide variety of applications and vertical segments.

Protium S1

The Protium S1 platform provides front-end congruency with the Cadence Palladium Z1 Enterprise Emulation Platform. BY using Xilinx Virtex UltraScale FPGA technology, the new Cadence platform features 6X higher design capacity and an average 2X performance improvement over the previous generation platform. The Protium S1 platform has already been deployed by early adopters in the networking, consumer and storage markets.

Protium S1 is fully compatible with the Palladium Z1 emulator

To increase designer productivity, the Protium S1 platform offers the following benefits:

  • Ultra-fast prototype bring-up: The platform’s advanced memory modeling and implementation capabilities allow designers to reduce prototype bring-up from months to days, thus enabling them to start firmware development much earlier.
  • Ease of use and adoption: The platform shares a common compile flow with the Palladium Z1 platform, which enables up to 80 percent re-use of the existing verification environment and provides front-end congruency between the two platforms.
  • Innovative software debug capabilities: The platform offers firmware and software productivity-enhancing features including memory backdoor access, waveforms across partitions, force and release, and runtime clock control.

“The rising need for early software development with reduced overall project schedules has been the key driver for the delivery of more advanced emulation and FPGA-based prototyping platforms,” said Dr. Anirudh Devgan, senior vice president and general manager of the Digital & Signoff Group and the System & Verification Group at Cadence. “The Protium S1 platform offers software development teams the required hardware and software components, a fully integrated implementation flow with fast bring-up and advanced debug capabilities so they can deliver the most compelling end products, months earlier.”

The Protium S1 platform further extends the innovation within the Cadence Verification Suite and supports the company’s System Design Enablement (SDE) strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently. The Verification Suite is comprised of best-in-class core engines, verification fabric technologies and solutions that increase design quality and throughput, fulfilling verification requirements for a wide variety of applications and vertical segments.

Blog Review – Monday, January 23, 2017

Monday, January 23rd, 2017

This week’s blogs show the human face of automated driving; and why energy should be taken seriously. There is lift-off for SpaceX to bring more satellite comms and a poetic turn, in the style of Rudyar Kipling’s classic poem.

There is a human element to automated driving, namely Human Machine Interface (HMI) and Jack Weast, Intel, uses his second blog post to examine how and why it can be used. He promises more in part three into the company’s research.

Energy is a serious business, says Grant Pierce, Sonics, and the electronics industry must shoulder some responsibility for power savings. The company, with Semico Research is conducting a survey and wants your help into understanding today’s and tomorrow’s power requirements.

Boosting the satellites to provide point-to-point communications, the SpaceX Falcon 9 rocket put the first 10 Iridium NEXT satellites into Low Earth Orbit (LEO), equipped with Xilinx space-grade Virtex-5QV FPGAs to implement the satellites’ On Board Processor (OBP) hardware. Steve Liebson, Xilinx, includes a link to a video describing the constellation and the launch.

Celebrating the relationship with Ericsson, Dassault Systèmes’ Olivier Ribet, looks at how the latter’s Networked Society will transform the way we interact with the world around us and meet technology challenges, such as 5G, IoT and the cloud.

Moving to 10nm and lower process geometries pushes the boundaries of FinFET and the custom layout flow and this means trouble ahead, warns Graham Etchells.

A touch of culture, with a poem “wot I wrote” by Keith Hanna, Mentor Graphics. He deftly tackles Computational Fluid Dynamics (CFD) as Rudyard Kipling might.

Image data and the mysteries of how to create, access and use a Qimage to greatest effect is detailed by Laszlo Agocs, Qt, with three case studies to illustrate what can be done.

A sharp video addressing the interconnect verification challenges is hosted by Nimrod Reiss. Cadence’s Corrie Callenbach has found and highlighted the video.

Caroline Hayes, senior editor

Blog Review – Monday 07 November 2016

Monday, November 7th, 2016

Browsing the MIT Library; AI and HPC for cancer breakthroughs; FPGAs on Mars; Romancing ISO 26262; It’s IoT conference season; Who’s going to pay?

For smart and connected IoT devices, Intel has introduced the Intel Atom processor E3900 and Ken Caviasca, Intel explains how the series brings computing power nearer to the role of the sensor.

Crash scenes from Mars, as taken by the Mars Reconnaissance Orbiter’s High Resolution Imaging Science Experiment (HiRISE) reveal features previously unseen on the planet. Steve Leibson, Xilinx, explains how we have FPGAs to thank. (For the images, not the crash!)

Ahead of GE’s Minds & Machines Conference (November 15-16, San Francisco) Lane Lewis, Ansys, celebrates the marriage of the Simulation Platform and Predix Platform to create a profitable asset health monitoring and the industrial IoT.

As mobile payment matures, Martin Cox, Rambus Bell ID, identifies that tokenization is becoming a hot topic. His blog explains the role of the company’s Token Gateway as a means to integrate multiple mobile payment schemes. No excuse not to get a round of drinks in now.

Moving automotive and safety into the realm of Dungeons and Dragons, Paul McLellan, Cadence, reviews the recent DVCon Europe and how ISO 26262 – the critical safety standard – became a theme, but not necessarily one to dread and fear or avoid. Like St George, you just have to grit your teeth and tackle it head-on, to find the pot of gold that is critical safety design success.

Fresh from IoT Planet in Grenoble, France, Andrew Patterson, Mentor Graphics, is occupied by two topics – connectivity and security. He shares some interesting thoughts and statistics around these gleaned from the event.

Fascinating insights into the world of bio-medicine and computational bio-medicine are provided by Dr Michael J McManus, Intel. He explains how Artificial Intelligence (AI) and High Performance Computing (HPC) are used by researchers to analyze data and predicts an era of revolutionary cancer breakthroughs, of both drug development structures and genome analytics running on a single Intel cluster using Intel Xeon, Intel Xeon Phi processors and Intel Omni-Path architecture.

There is a fascinating collection of rare books at MIT, exhibited to mark Ada Lovelace Day. For those can’t walk the aisles of the MIT Libraries, Stephen Skuce, MIT Libraries, shows us through some of the collection relating to women who have contributed to science, math and engineering with its annual celebration of the history of women in the STEM (Science Technology, Engineering and Mathematics) subjects.

Caroline Hayes, Senior Editor

Blog Review –Monday, October 24 2016

Monday, October 24th, 2016

The how, what and why of time-of-flight sensors; Conference season: ARM TechCon 2016 and IoT Solutions Congress; Save time on big data analysis; In praise of FPGAs; Is it time for augmented and virtual reality?

Drastically reducing big data analysis is music to a data scientist’s ears. Larry Hardesty reports on researchers at MIT (Massachusetts Institute of Technology) have presented an automated system that can reduce preparation and analysis from months to just hours.

Keeping an eye on the nation’s bank vaults, Robert Vamosi, Synopsys, looks at the what bank regulators are doing to ramp up cybersecurity.

If you can’t head to Barcelona, Spain this week for IoT Solutions World Congress (October 25-27), Jonathan Ballon, Intel, reveals what the company will unveil, including a keynote: IoT: From Hype to Reality, what 5G means, smart cities and a hackathon.

Tired of the buzz, and seeking enlightenment, Jeff Bier, Berkeley Design, delves into just what is augmented reality and virtual reality. He examines hardware and software, markets and what is needed for widespread adoption.

Closer to home, 2016 ARM TechCon, in Santa Clara, California (October 25 – 27), Phil Brumby, Mentor Graphics, offers a heads-up on its industrial robot demo, using Nucleus RTOS separated by ARM TrustZone, and the ECU (Engine Control Unit) demo in a Linux-hosted In-Vehicle Infotainment (IVI) system. There is also a technical session: Making Sure your UI makes the most of the ARM-based SoC (Thurs, 10.30am, Ballroom E)

The role of memory is reviewed by Paul McLellan, Cadence Design System, as he discusses MemCon keynotes by Hugh Durdan, VP of the IP Group and Steve Pwalowski, VP of Advanced Computing Solutions at Micron. There is comprehensive pricing strategy and a look at industry trends.

A teardown of the Apple iPhone 7, by Dick James, Chipworks, links STMicroelectronics’ time-of-flight sensors with the Starship Enterprise. The blog has a comprehensive answer to questions such as what are these sensors and why are they in phones.

If the IoT is flexible, Zibi Zalewski, Aldec, argues, then FPGAs can tailor solutions without major investments in an ASIC. He takes Xilinx’s Zynq-7000 All-Programmable SoC as a starting point and illustrates how it can boost performance for IoT gateways.

Elegantly illustrating how multiple Eclipse projects can be run on a single microcontroller with MicroEJ, Charlottem, ARM, runs through a connected washing machine that can communicate via Bluetooth, MQTT, Z-Wave and LWM2M.

Caroline Hayes, Senior Editor

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