By Ed Sperling
It was a good week for emulation. Mentor Graphics joined forces with MoreThanIP to create emulation solutions for multi-gigabit Ethernet SoCs.  Mentor also won a deal from ZTE for its Veloce emulator, and it added emulation solutions for USB 3.0 products.

Cadence and Samsung have developed a 32nm HD digital camera SoC for Ambarella, which has been creating digital still cameras with high-definition video capabilities. Translation: lots and lots of pixels. Cadence also teamed up with Xilinx for system design, software development and testing of Xilinx’s Zynq platform. And Cadence announced its quarterly numbers, showing net income of $28.1 million for the quarter ended Oct. 1 ($37.3 million non-GAAP) vs. $126.8 million in the same period in 2010 ($11.2 million non-GAAP). Revenue for the quarter was $292 million vs. $238 million in 2010.

eSilicon inked a deal to use Synopsys’ Custom IC design solution for 28nm SoCs. And Synopsys’ DesignWare Audio IP achieved first-pass silicon for 65nm and 55nm process technologies from multiple foundries.

Open-Silicon launched an ARM Center of Excellence to provide complete SoC development solutions for low-power chip development for the networking, telecommunications storage and computing markets. This is becoming a very cozy relationship. Open-Silicon already has a multi-year licensing agreement in place with ARM.

Atrenta introduced early PPA analysis for ARM’s AMBA designer using its SpyGlass and GenSys products.  Atrenta also joined Cadence’s System Realization Alliance, which is no surprise considering it was one of the first to adopt Cadence’s EDA360 terminology.

Arteris won a deal from VIA Telecom for its high-speed inter-chip communications IP between mobile phone baseband chips and application processors.

Tensilica won a deal from EnVerv, which licensed Tensilica’s ConnX DSP cores for its smart grid power line communications SoCs.

By Ed Sperling
System-Level Design sat down with Ivo Bolsens, CTO of Xilinx; Charlie Janac, CEO of Arteris; Ravi Varadarajan, an Atrenta fellow; Sumit Dasgupta, senior vice president of engineering at Si2; and Herb Reiter, 3D/TSV working group chair for the GSA. What follows are excerpts of that discussion.

SLD: As we start re-using IP sometimes it won’t work in a stacked configuration the same way it does in a 2D structure. How big a problem is that?
Janac: With the interposer that shouldn’t be a problem. You’re only talking about logic-to-logic and memory where there is a problem.
Dasgupta: It depends on whether it’s hard IP or soft IP. If it’s expressed in RTL then maybe it can be synthesized and laid out, in which case everything you’ve said for regular logic applies to this IP block, as well. You’ve got to think 3D.
Reiter: Even with 2.5D Xilinx didn’t just take an FPGA and mount it in flip-chip fashion. With 2.5D you want to redesign your SoC to be more cost effective because 20% to 30% of the die is in the periphery in the I/Os. The power dissipation is in the I/Os. Those are all cost elements.
Varadarajan: In 2.5D, are there special buffer drivers?
Bolsens: Yes, there are special buffers. But there are other things you don’t need. You don’t need ESD surge, for example, which you would need in other buffers and I/Os. That causes power consumption and adds to cost.
Varadarajan: Is there any advantage to a buffer layer where you put large IPs onto it?
Bolsens: When you say 2.5D you make the decision that you don’t put the active layer into the interposer. Our interposer is just meant for interconnect. It has four layers of metal. Otherwise the interposer gets more expensive. That’s a tradeoff you make.

SLD: What’s the starting point in standards? Is it getting enough functioning chips out the door to really understand the issues?
Reiter: Based on what I’m hearing from the equipment industry, we need to come soon to a design for testability convention for 2.5D and 3D. Not only for the final test, but also for spec-in-progress testing. The Imec proposal is to make the bottom die bigger and have probing pads so you can test if the die is good before you put another die on top of it. I’m looking at the need to teach chip designers how to design for 3D. We should start with design for test.
Dasgupta: IEEE is going down that path. But as for what we should be doing, we’re collecting information as we go along. I don’t think we will create standards and say this is it. It will be a spiral method of development where we take little bits of everything at a time, starting from design planning down through the physical space and the verification space and finally to manufacturing. It’s going to be multiple versions of these standards as we go along. Si2 is finally getting started on this after two years. I expect this project will go on for several years.
Reiter: And we should not panic about the complexity because 22nm and 16nm will not be a cakewalk, either. Large corporations can choose between the two, but smaller companies really have no chance of doing a 16nm design because if one transistor is wrong the whole thing is dead.

SLD: The promise of 2.5D is you can take a 16nm design and put another layer on top of it, right?
Bolsens: Sometimes companies have this intellectual property about a certain vertical market segment, which they understand better than anyone else, and they can mold it into a chip. The problem is that to do that you need so much infrastructure that has no connection to your key competencies. Building services in a chip is not an easy thing to do, but in some cases it may be a differentiator between you and your competition. If the infrastructure is there and you can bolt your specific piece of silicon that captures your IP and you can leverage all the infrastructure, that’s an interesting value proposition.
Janac: Does that mean the eSilicon model prevails?
Reiter: I have eSilicon in my road map for exactly this reason. eSilicon will help small companies deal with complexity and get products out. In a 2D SoC you have to live with the process the rest of the SoC is using. Here you can rewrite the die business.

SLD: Does the adoption of standards slow down this whole movement into 3D?
Dasgupta: That’s difficult to answer because there are no standards. There is development going on. The pace at which people are beginning to clamor for standards is the right pace. Two or three years ago no one was asking for them. Today, all the leading players are asking about standards. That’s music to our ears. We know there’s demand out there. I don’t think standards are prohibiting progress, but if there were standards we would have faster progress, proliferation and adoption.
Reiter: I would hope some large players would bring out 2.5D and 3D chips in volume, which would really shock the industry into catching up. Then this big crowd of industry players left behind will put enough pressure on the industry to create standards so they can catch up. This lock-step game should not take too long, but two years is too short.
Dasgupta: No matter what standard you’re talking about, each one has its own heartbeat. You cannot be too early or too late. Herb’s point is well taken. At the beginning of every technology there are certain leaders who think that everything they do is IP and they will not talk about it with anyone. After a couple competitors come along and show they’ve been doing similar things, suddenly things open up. In 3D and 2.5D we are reaching that point.
Reiter: I can endorse this because I’m talking to some of the very big guys. These big corporations will not be able to cost-effectively manufacture everything that goes into a 3D configuration. They will want to buy pieces from the outside, and they may want to buy entire companies. A UPF corporation today only gets half the value from a CPF player if they’re folding it into the organization. The big guys are already thinking that standards will be good for them.

SLD: As we go forward, companies won’t have to do all the unique analog processes. They may take a processor, which may be a commodity, and put another piece of analog on it, which may be a commodity, as well. So aren’t we really commoditizing a lot of the pieces.
Reiter: Yes, and our industry may split into providers and consolidators—corporations that take a lot of these pieces and put them together. That’s a big business model change. It won’t happen overnight, but it is one of the possible outcomes.
Bolsens: One of the challenges is understanding business models better. I personally think one of the things that will drive standards will be business rather than technology. That will make the standards move faster than we have seen in the past. We also need standards to understand who’s going to do what and who’s responsible for what. The reason that package-on-package is picking up steam is that it’s really clear who owns that technology and where it fits into the whole chain. With 3D is it the packaging house, the foundry? Clarification of that will drive standards.
Dasgupta: TSMC had a presentation where they kept asking, ‘What is the business model?’ Every one of us needs to make money, of course. They were talking about the relationship between the OSATs and the foundries. This is very well understood in the 2D space, but in the 2.5D space and 3D space it gets fuzzy depending on whether it’s via first, via middle or via last. Today the foundries keep 80% of the profit. Once the OSATs get more sophisticated that will change. The business model, the financial model and the legal model have to change. Now you’re stacking die from different sources. If it fails, who’s responsible? Will there be a repair policy? Who’s going to repair it?
Reiter: This is a huge technical challenge and a huge capital investment.
Bolsens: That’s another reason we need standards. The OSATs are playing with very thin margins. But if we see them playing a critical role in this it will require an investment in technology. If they don’t see a return, that’s a problem for this technology. We need to understand that.

SLD: What happens to NoC technology here? Does that become standardized?
Janac: The NoC is a highly configurable IP, and in many ways it’s situational IP. Many companies will take it and use it in different ways. The actual silicon part, though, may become fixed.
Bolsens: One of the thing the NoC does is it allows you to make an abstraction of the physical interconnection. It will make it easier to adopt 3D technology. It could make it more transparent, whether it’s 3D or 2D.
Janac: With the logic tools we see this today whether it’s one die or two die, the network is the same in a logical sense. It also allows you to do a better job of isolation and partitioning.
Dasgupta: It’s divide and conquer.
Reiter: And where I see a NoC hopefully as very useful is in logic redundancy. Memory redundancy is easy, but logic redundancy is very difficult. You can turn off units and get better yield and control your costs.

By Ed Sperling
System-Level Design sat down with Ivo Bolsens, CTO of Xilinx; Charlie Janac, CEO of Arteris; Ravi Varadarajan, an Atrenta fellow; Sumit Dasgupta, senior vice president of engineering at Si2; and Herb Reiter, 3D/TSV working group chair for the GSA. What follows are excerpts of that discussion.

SLD: Putting memory on top of logic doesn’t necessarily require 3D standards, does it? That can be a 2.5D configuration.
Reiter: That’s correct. It could be isolated by an interposer with logic on the other side because of temperature challenges.
Janac: This is the most practical application we see. The logic-to-logic will come later because of the complicated technology that’s involved.
Reiter: And network on chip will give a lot of headroom for expansion of this configuration.
Dagupta: I’ve been tracking this for about 5 years. I think we will see 2.5D next year.
Janac: The other thing that’s driving it besides memory bandwidth is that people are running out of I/Os. They’re multiplexing I/Os just to get multiple peripheral standards out through the I/O. That’s crazy. Somehow additional I/O availability has to be freed up. The only way to do that is to go through silicon.
Bolsens: That’s one of the main reasons we initiated our 2.5D product. If you look at the I/O bandwidth efficiency, we are getting about 100 times better gigabits per watt capabilities. People are trying to improve the bandwidth with gigabit transceivers. But there’s also a cost of power and latency. That’s one of the things this technology is solving. I/O hasn’t kept up with the capabilities of transistors on a die.
Varadarajan: We have customers doing logic-on-logic/memory. They’ve gone to memory on logic, and there is available real estate on the memory die. So they look at which IP subsystem can be moved to the memory die. They are starting to explore that in a test chip scenario, but not in full production.

SLD: Will something speed this up?
Varadarajan: We have been inventing standards on the fly. Do you need two RDL (redistribution) layers or three RDL layers? You want to invent standards because if you have a choice between increasing the pitch between two RDL layers or three layers, which one will allow you to do the routing without condition and meet timing. When companies begin to work in these areas, it pays to have more standardization.

SLD: When we get into real 3D stacking, we will need a whole new set of standards, right? We’ll even need some standards around layout.
Dasgupta: We also need standards for how to model a TSV. That includes everything from a simple resistor to distributed transmission lines with parasitic transistors.
Bolsens: If you just look at a 20nm transistor next to a TSV, it’s a like a skyscraper next to a small shack. If you can imagine what the impact will have on a 20nm transistor—it’s something you can’t ignore. The modeling of a through-silicon via is going to be an important aspect.
Reiter: Even before we begin to measure certain standards we have to address the thermal mechanical effects. Today, in 2D SoCs, there is no worry about the chip’s expansion. There are some underfill and epoxy challenges, but these are overcome by the packaging guys. Now the chip architect has to be aware that if he puts two chips together that expand differently, or if you have a CPU with a 100-amp current and a sensitive analog chip on top of it, you have magnetic interference. There will be a lot of basic education necessary even before we can give standards a chance.

SLD: What happens to yield when we get into a stacked die?
Bolsens: That’s a logical extension of complexity. The challenge we will have is that if you think of future 3D systems where you’re going to partition the system into different planes, how do you test all the different parts? Today, every die works independently. In the future, you’re going to have to think about building a system on chip in three dimensions where you have incomplete systems on incomplete systems. How you test that will definitely be a challenge.
Dasgupta: I spent most of my career at IBM managing physical design tools. One of the things we told the router guys was to avoid vias. It was a discontinuity. It was not an RC or part of a transmission line. It causes reflections and interference, and its reliability is lower compared with a wire. And now suddenly we are enamored with this thing that is going to punch through layers of silicon. Somewhere we need to solve this madness. We need to make sure the quality of the TSV is equal to or better than a normal via. Otherwise we are going to have a lot of bad stacks.
Janac: Wide I/O is 1024. That’s the standard. And very deep.
Dasgupta: Yes, it’s the deep part that scares me.
Bolsens: This is still not millions. We need to see things in perspective. We are adopting this technology in a very careful way. There are a lot of challenges ahead, but that’s almost like boiling the frog. You do it very slowly.
Reiter: In my book, 3D is not an IC design technology. It’s a system technology. Something we really need to think about as quickly as possible is redundancy and self-repair. Otherwise we may never get something to the designer that inspires confidence. If you have a million vias, you better think about redundancy. With 0.01% failing, that’s a dozen or more.

SLD: But won’t you be using fewer vias with TSVs? And in addition, won’t that change design because most of these will be in the center of the chip, not at the periphery?
Janac: It certainly doesn’t help floor-planning.
Reiter: And IP re-use is not taking the 2D IP we now have and putting it into a 3D system. We have to reconceive a lot of our IP to make it suitable for 3D. Cost is everything, too, so we have to think about 3D from the beginning.
Dasgupta: There was statement made by an engineer from one company where they put logic on one layer, memory on another and I/O on the third layer. His conclusion was that to get significantly better performance you have to partition and floor plan in 3D. You can’t think 2D and expect it to work in 3D.

SLD: Then do we really know what standards have to be set?
Dasgupta: We are just scratching the surface on that.
Reiter: We have to understand and set a priority. Two years will not be enough.
Dasgupta: We got approved on a standards project two years ago and we haven’t done anything. Our board of directors asked what we’ve done so far and we said nothing. Their response was, ‘Good, because we’re not ready.’
Bolsens: That’s also where you see the importance of consortia like Imec and Sematech. Several industry leaders are working together to do the pathfinding approach and understand all the challenges and what we need to do there.
Reiter: There is also ITRI in Japan and Leti in France. Georgia Tech is also doing a lot of work in this area. 3D relies heavily on packaging. While the outside pin count may be reduced, it clearly needs more sophistication inside in regards to getting parastics under control.

SLD: How close are we on 2.5D?
Bolsens: It better work. There are some simplifications in 2.5D. You don’t have an active-on-active structure. You have an active-on-passive layer. You also have considerable thermal challenges with active on active, so the risks are lower with 2.5D. That’s where we have our first 28nm product. That’s where you’ll see some of the memory guys show up with solutions. But what we have done at Xilinx is build a captive product. All the silicon comes from inside, so life is a lot easier. It’s when you start combining chips from different vendors, aggregating them, and figuring out who’s responsible for that and for test—that’s when you start running into problems in the industry that still have to be solved. For captive products it’s a lot easier.
Reiter: Intel also announced some 2.5D products. They had to get an Altera FPGA and an Atom processor to make the periphery configurable. And in regard to 3D production, a number of memory vendors have announced products with as many as eight die. Memory will be the first one to utilize 3D because you can design it and use it multiple times.
Janac: It’s a simpler problem.
Reiter: There have been other announcements, too, but none of it is in volume production. I assume that’s because of cost.
Dasgupta: Limiting it to memory limits the risk. It’s the same die, the same technology node, and the distribution of the TSVs is easier to control because it’s a more regular structure.

By Ed Sperling
System-Level Design sat down with Ivo Bolsens, CTO of Xilinx; Charlie Janac, CEO of Arteris; Ravi Varadarajan, an Atrenta fellow; Sumit Dasgupta, senior vice president of engineering at Si2; and Herb Reiter, 3D/TSV working group chair for the GSA. What follows are excerpts of that discussion.

SLD: How far has the industry progressed with standards for 3D stacking to help speed along this technology?
Reiter: Is this open or proprietary standards?

SLD: Both, because one often leads to the other.
Dasgupta: That’s a good point. If you have proprietary standards then its evolution is not nearly as rapid as an open standard with many voices talking about it and many minds contributing to it. It is good to start with something that has been tested inside as a proprietary standard, but if it is opened up that’s the ideal mix. If it doesn’t start from zero that’s good, but openness is necessary.
Bolsens: Standards, in the end, have to be open. One of the things you want to achieve is to create enough critical mass and momentum around certain technology to make sure that the efforts—especially in new and emerging fields—are well spent and that there is a return on investment. Everyone needs to benefit from them. We are in the very early phase of development of this technology and everyone wants to make sure their efforts pay off.
Reiter: Standards are a lot of effort—and I’m speaking from experience. I drove the PrimeTime signoff standard. This was a three-year effort for me, and at Synopsys we invested 50 man-years to make it an industry standard. Today 95% of designers are using it for timing signoff, but three years is a long time.
Janac: A lot of standards that are made in standards bodies haven’t seen the heat of battle in customer designs and they haven’t been tested in the real world. Sometimes they’re convoluted. It’s the difference between a horse and a camel. The camel is a horse designed by committee. If you have something that has been used in production it’s much more robust, much more useful, and much more practical than something created by a standards body that hasn’t had the discipline of trying to get a design through production.
Dasgupta: I agree. If you start from the ground up by committee—and VHDL is a good example—it is painful. Verilog, in contrast, was already proven before it was delivered into an open environment. That’s the right model. You need to start off with something that’s already been proven. And if you keep it closed, then you don’t get the intellectual contributions that come with an open standard. At the point you’ve proven it, that’s where you open it up to the industry to make it widely accessible, implementable and accessible.
Varadarajan: We’re building an early stage prototyping system for 3D design exploration. We are right in the midst of all of this. If you stack a die front side to back, what sort of parasitics are you going to look at with microbumps and TSVs. A lot of this information is not available. We are working with technology steering committees such as LETI and Imec and hopefully what comes out of this is useful for the mainstream. When you have a stack configuration, how do you specify that? Do we have an XML specification? We need to see that either as a standard, or at least a specification with multiple people contributing to that. I do believe that 3D is real. Next year you’re going to start seeing logic on logic and interposers. Having multiple people using that is critical so we don’t have a repeat of UPF and CPF. We don’t want multiple standards evolving at once.
Reiter: That’s a very important point. If you want to succeed with a standard you have to bring it out at the right time and make sure there is enough momentum behind it to make the industry line up behind it. UPF vs. CPF was a very expensive accident for our industry.

SLD: Power will become an important part of this, for sure.
Dasgupta: We just made a contribution to IEEE of a subset of the CPF standard specifically to align some of the semantics representing power constraints. The syntax is not as important as clarity and similarity of semantics. Si2 has been a member of the 1801 working group. The goal is to bring them together.

SLD: What standards do we need for 3D to work?
Bolsens: It covers the whole ecosystem. How do you handle between foundries, packaging and assembly houses. You need agreements on the technology files you hand off to foundries. The whole modeling of the interfaces. We have to find agreements on how the interfaces will look, how they will be models, how they will work with technology from different origins. It’s a pretty complex thing. It reaches from EDA to design houses, testing, even equipment for thin-wafer handling. It requires a lot of players.
Reiter: Unless the equipment is lined up the cost will be unaffordable.
Dasgupta: At the RTL conference two years ago, a major semiconductor company announced that it had solved all the technical roadblocks to announcing a product. So where is it. There still isn’t a product. The reason is that there is still not a financial incentive to going to 3D, so 2D remains more competitive. There are things that happen vertically and things that happen horizontally. How is information exchanged between floor planning other areas and then transferred back.
Reiter: We cannot invent a totally new environment. We have 100,000 IC designers out there and they have their own way of doing things. As we introduce new standards and new technology, we have to make sure we don’t disconnect them.

SLD: The list of what has to be done with standards in 3D sounds like it will involve thousands of man-years of work.
Bolsens: I wouldn’t be surprised at that. There are so many different organizations involved. For 3D stacking there will be Si2, Jedec, Sematech, SEMI. No one organization will solve the whole 3D problem. It’s a multidisciplinary challenge. Different parts of our ecosystem will have to take care of it.
Dasgupta: The biggest challenge we face is time. If you look at the 2D space, many of the standards we use today have evolved over 20 to 25 years. We’re looking for that level of standards in two years.
Reiter: I don’t think two years is realistic. It will take longer.
Dasgupta: I think it will, too.

SLD: Where is 3D at this point? How real is it?
Janac: There are 2.5D test chips.
Reiter: And 3D, as well. There are big companies working on 3D stacks because the form factor is so much better.
Janac: There is logic to logic/memory, and there is the 2.5D, which is logic/memory.
Bolsens: I think the big driver will be logic/memory. That’s going to really make this technology mainstream because everyone is struggling to meet the bandwidth requirements. Providing wide memories with lower power and latency will be the killer app.

By Ed Sperling
The first 2.5D and 3D chips are expected to arrive next year, with the mainstream chip market expected to follow in 2013.

While this trend already has seen its share of hype, stacked die—whether through a series of TSVs in true 3D or through an interposer layer in 2.5D—is as real as Moore’s Law. In fact, it’s a direct result of Moore’s Law.

But unlike the progression of Moore’s Law so far, stacking of die will have ramifications for every part of the IC ecosystem. From a business standpoint, it holds the potential to revolutionize the speed with which chips are built for generalized as well as customized markets. From the technology side, it can radically boost performance by moving memory closer to processor cores and reducing bandwidth constraints. It also provides some of the benefits of classical scaling because it requires less power to drive signals over a shorter distance.

What is less clear is the number of obstacles that will be encountered along the way and what exactly those obstacles will be. In some cases, those obstacles are economic. How much will it cost to add an interposer layer, for example, versus a standard 2D package? In others, there are physical effects that have to be considered, such as the stress of drilling TSVs into die, thinning and handling of ultra-thin wafers and how to get heat out of a true 3D stack. And there are still questions about how all of this technology is going to be tested and verified.

Economic considerations and timing
“Initially, this is all about cost,” said Prasad Subramaniam, vice president of design technology at eSilicon. “Power may be an overarching benefit and people may pay more for that advantage initially. But first it is about cost. We believe the cost will come down over time as volume increases.”

The general consensus among companies across the supply chain is that the first stacked dies will begin to appear in volume over the next 12 months. Mainstream adoption is expected to ramp up over the next two years. That will include some true TSV-based 3D designs, which can leverage smaller form factors, as well as 2.5D, which is where the mainstream market adoption will occur.

“If you can do the chip on an MCM (multichip module) or SiP (system in package) then there’s probably no need for 2.5D,” said Subramaniam. “The real benefit is power, and if you enable more pins on a die you get more communication between multiple die. You can’t implement Wide I/O on an MCM. You can’t get the pitch to accommodate multiple signals.”

Xilinx has taken a first stab at using an interposer to link four different die. Ivo Bolsens, CTO at Xilinx, said the driving force for his company’s decision to use an interposer was yield. The success rate in producing four smaller chips is significantly higher than one large chip, even with an interposer in the middle.

Xilinx isn’t alone in trying to solve this problem. Samsung, Elpida and Micron all are sampling 3D memory chips using through-silicon vias, and STMicroelectronics and Infineon have introduced MEMS chips and sensors based upon stacked-die approaches.

“This has been a fairly rapid shift toward 3D,” said Steve Smith, senior director of platform marketing at Synopsys. “It all changed about the time Xilinx announced its prototype FPGA in October. After that, TSMC and GlobalFoundries began making noise about stacked die. The biggest benefit is that some of these chips can be designed the same way, which will increase their adoption. The only real worry is the alignment of bumps on the ‘Moore’s Law’ chips to connect to the interposer. You can do that with a spreadsheet analysis, though. There are no fancy tools required.”

Evolutionary development
As significant as stacked die are on the design and business of ICs, what is likely to unfold over the next few years is more evolutionary than revolutionary. While the memory makers develop complex architectures to improve throughput, they will mostly be packaged with existing technology that is part of an existing design methodology. In fact, some parts of design may actually get simpler.

“You can either put more logic on the chip or shrink the die,” said Smith. “But when you look at traditional place and route, that’s a bunch of black boxes. There are a lot of big macro blocks around the periphery. That’s where you put analog interfaces, and you can attach to memory in the middle.”

Even testing in 2.5D is not that difficult. Some will have to include built-in self-test (BiST) for embedded technology that cannot be easily tested, but for the most part there are no surprises in 2.5D configurations. Things get dramatically more difficult in true 3D packages, however.

“The question is how you bring all of these elements together to come up with a fully functional 3D device,” said Steve Pateras, product marketing director for silicon test at Mentor Graphics. “What’s happened in the industry is we’ve become very fragmented over the past 10 to 20 years. This is going to drive a blending of the IC fab with the packaging house to provide this kind of solution. Once this happens, there will be a lot of people out there who say they need this.”

What’s missing
There will also need to be new EDA tools developed—or at least significant extensions to existing tools—to make all of this work.

“With TSVs it all depends on what’s the pitch,” said Mike Gianfagna, vice president of marketing at Atrenta. “The denser the pitch the more packaging, and the cost in yield loss goes up exponentially. There also need to be thermal and stress models and a better way of calibrating these models, which right now is weak, at best. And with EDA tools, you need good thermal and mechanical stress models.”

All of this will take time to develop, of course. So will the tools to actually handle extremely thin die. Interposers are regular thickness, but in a true 3D stack the layers are much thinner and can easily break using current technology.
Beyond that, there also will have to be a business case for more companies to move to true 3D before that becomes a mainstream technology.

“Designs drive the process,” said Gianfagna. “EDA tools can work but without good data that doesn’t really matter.”

The future
Still, the number of choices that will become available once the semiconductor ecosystem adjusts and the processes are developed are enormous. Just as process technology has become refined to the atomic level, stacking of die adds a level of granularity for specific markets that addresses what can be put together quickly and for whom. A 3D stack may include a MEMS chip or an analog sensor built on the same base platform, for example, with minimal additional development time or cost.

And with foundry equipment expected to cost tens of billions of dollars at 14nm, there may be little choice but to pursue this path. The progression of Moore’s Law may continue intact—the number of transistors in a chip, rather than on a die will continue to grow—but not necessarily in the same plane or even from the same company.

By Ed Sperling
While EDA continues to generate solid returns on investment, the real growth is at the fringes of the market—new methodologies, new types of chips, and new ways of thinking about putting them all together.

In a keynote speech at the Mentor Graphics U2U conference—as in User To User—company chairman and CEO Wally Rhines showed off a number of areas that are either growing or poised for growth. DFM continues to post the largest growth as yield and chip viability connect the front end and the back end. Formal verification also is running at a 13% compound annual growth rate, as well. Layout and PCB are flat, even though they are profitable for companies that have tools there.

But Rhines said other areas are beginning to show significant increases:

– Cloud-based emulation is expected to be a significant growth market as companies begin leveraging resources as needed. Mentor is throwing its hat in the ring on this one, Rhines said, because “over the next decade this will be an area of enormous growth.” Synopsys CEO Aart de Geus announced his company’s plans to offer cloud services for debugging at the Synopsys User Group (SNUG) last month.

– Embedded software automation (ESA) will likewise grow at a rapid clip, in large part because chipmakers increasingly are responsible for developing some of the software to go with their chips. “A lot has to happen in embedded software to make it easier to develop,” Rhines said. He said that growth will depend heavily on the ability to re-use software, automation, verification and open standards.

– High-level Design is benefiting from a need to raise the level of abstraction to deal with complexity. Last year it grew 12%. Architectural exploration will add another round of growth to this area. “If you do this at a high-enough level you can make system-level tradeoffs,” Rhines said.

– Power Analysis will be a significant growth area, particularly as more accurate ways of estimating power come to market. The limitation, he said, is building a database of libraries that are meaningful.

– Software prototyping has shown significant promise as chipmakers reduce time to market by running software on virtual prototypes or models of chips.

– Intelligent testbenches in functional verification are proving extremely popular in complex designs, offering up to 10 times better coverage and 100 times faster times when run in multiprocessing configurations. “Intelligent test benches are graph-based, so there is a virtually linear scaling with multiprocessing,” he said. “People worried about verification in the future should not be.

Ivo Bolsens, chief technology officer at Xilinx, in a second keynote speech also pinpointed a new growth area for FPGAs, which he called hybrid chips. He said they will add the programmability and flexibility of FPGAs, some of the speed and efficiency of ASICs, and much quicker time to market.

“The aggregate compute capability of an FPGA is enormous,” Bolsens said. “The challenge is how to expose that to the designer in a cost-effective way.”

He noted there are two trends that will force this change. One is tighter integration of the CPU and programmable logic. The second is 3D packaging, which will enable high-speed connections to memory and ASIC logic functions through interposers and through-silicon vias. He noted the upside is radically improved bandwidth—up to 100 times—per watt.

By Ed Sperling
‘What if’ questions have become standard across multiple pieces of the design chain for any SoC, but the number is multiplying at each new process node.

When the industry begins moving to 2.5D and 3D over the next couple years, the number of tradeoffs will likely move from overwhelming to unmanageable. That will set in motion a number of efforts in semiconductor design.

So what’s behind these changes? One is simply the sheer number of tradeoffs that stem from SoCs with hundreds of millions of gates, I/O on and off the chip, an increasing amount of re-usable and commercially available IP and an overall effort by chipmakers to eke more performance for less power out of a design.

“There is no killer app anymore,” said Fred Cohen, director of the OMAP wireless ecosystem at Texas Instruments. “There are 20 of them. It’s impossible for an SoC vendor or an OEM to master all the complexity and innovation. So you need to engage with all these companies, and you need to do it almost on a daily basis.”

In the design space, that also means better modeling and more granularity for exploration. If there is an explosion of ‘what if’ dependencies, more needs to be dealt with at the architectural level. And it has to be dealt with more effectively.

“You synthesize from C or C++ down to RTL because you can simulate so many alternatives at a high level that the chances for stumbling on the optimal solution are higher,” said Wally Rhines, chairman and CEO of Mentor Graphics.

That’s been a driver behind the recent uptick in high-level synthesis and ESL modeling, but so far the tools are incomplete. All of the major EDA players say they are now working on solutions in this area.

“Models are becoming more refined,” said Frank Schirrmeister, director of product marketing for system-level solutions at Synopsys. “From there you need appropriate characterization of those models. Right now people make assumptions and then they refine those models once the data is available. The big question is yet another ‘What if.’ What happens if we move to a smaller technology node or 3D. Does it all become unmanageable?”

Lots of questions, not so many answers
Similar questions are being asked all over the semiconductor industry. In the FPGA arena, where advanced modeling has largely been hidden, companies are beginning to look at the possibility of similar design methodologies for 2.5D and 3D stacks.

“This kind of performance analysis and estimation and power analysis and estimation has never been seen in the FPGA world,” said Ivo Bolsens, chief technology officer at Xilinx. “You know the platform and understand the delay and the power consumption from building a component because you have the silicon with an FPGA, but the tools are not there to do the optimization.”

What’s important here is the ability to do architectural exploration with enough granularity to be useful. Power modeling, for example, tends to rely on high-level estimates up front, but that data is notoriously inaccurate and can cause problems further downstream in the design flow. Exploratory or “pathfinding” tools have been talked about for years, but the amount of complexity has grown at advanced nodes to the point where there is now a real market need.

Fig. 1: A 2.5D design. Source: Xilinx

Location, location, location
One of the interesting things about stacking die is a fundamental shift in what gets placed where—not so much from a thermal standpoint but from a connectivity standpoint.

This is more than a layout issue. It’s a complex series of tradeoffs between power and performance, taking into account proximity effects, heat, electromagnetic interference and even electrostatic discharge. In 3D, understanding which blocks talk with which blocks, when, and by what means isn’t a simple decision. It’s filled with tradeoffs. A processor that used to communicate over a standard bus through a general-purpose operating system may now include a dozen heterogeneous cores, each with a specific function and running at different voltages. Two or more may be working at the same time, or there may be only one important processor core running with an accelerator.

“In 3D the prime real estate will be in the center of the chip,” said Kurt Shuler, director of marketing at Arteris. “In 2D the most efficient way to route signals was at the edge of the chip. That creates a different problem set and a different set of tradeoffs. Models now have to be topographically aware, too.”

There is increasing attention being paid to network-on-chip approaches to deal with tradeoffs more easily, substituting one piece of IP for another, for example and reconfiguring the network to deal with that. “A company’s first chip might be 50% new IP and the derivatives might be 20% new IP. Within the system, the only lever for change is the interconnect. In 3D that’s a similar situation. To accommodate different subsystems you need a quick way to do that.”

Business, but not as usual
Two known good die stacked on top of each other may produce two bad die. That kind of risk cannot be overstated in stacking die because the investment is far too high for getting it wrong, both in terms of NRE costs and missing market windows. But with stacked die, risk also increases by the number of layers being stacked together.

“What 3D stacking adds is more ways of hurting or helping ourselves,” said Drew Wingard, chief technology officer at Sonics. “Once you winnow the choices based on economics, then you have to figure out what are the high-level user benefits. You may get more features, save power or energy and optimize on cost. You can see that in Apple’s approach to SoCs. Some of their products have been done with components that are behind the competition, but their focus on the user is so strong that they always hit it right.”

Those kinds of tradeoffs occur in power and performance, as well. “In general-purpose computing, you make everything run as fast as possible,” Wingard said. “It’s all about not having a choke point. SoCs are usually a set of primary use cases. They’re much more complex, and 3D will become even more complex.”

Conclusion
What emerges from discussions with engineers across the IC design space is a recognition that more has to be done up front, with greater accuracy and with greater ease. Rather than reducing the role of design engineers to the mechanics of place and route, it points to a much more complex set of tradeoffs that can be made using an automated set of tools.

“This is all about re-thinking the ‘what-if,’ said Mike Gianfagna, vice president of marketing at Atrenta. “It’s a bridge between what you propose for an on-chip interconnect, for example, and then you try out ideas. The analysis will last a few hours or, worst case, overnight. Do you need a wide TSV or a narrow TSV? Which is the best answer? What’s the projected cost and what are the parasitic routing delays.”

Gianfagna noted that the goal is an optimized configuration, which may be cheaper, lower performance for some uses, and more expensive and higher performance for others. But all of this will need to be tried out and tried again on a vast level, potentially opening vast new opportunities for tools, for a new type of expertise, and for far more interesting IC designs.

By Pallab Chatterjee
Just how ready is the semiconductor industry for stacked die? That was the subject of a recent panel discussion involving ARM, Atrenta, Xilinx, Samsung and Mentor Graphics.

The reasoning behind 3D stacking is becoming clearer at each node. I/O count and delay times are forcing different configurations, but the time frames for these changes and the gating constraints are still somewhat fuzzy.

In the area of uses, the discussion focused on three areas–memories, SoCs and computing systems (processor cores and memory). Memories have been using stacked die approaches for many years. These stacks use traditional wirebond technology, feature either standard or thinned die, and have a known cost model.

The advantage of memories is that there is common pin-out and stacked devices can utilize existing memory test methodologies by adjusting the address range for the design. The die in this application are stacked from the top of one die to the bottom of the next die. These products have shipped literally billions of parts in this technology at a very similar price point to standard wire bond. This methodology supports using known good die for the design, has compatibility with current design tools and has known thermal performance.

Computing systems have a different target for stacked die. These systems, however, require a different architecture. There is local 3D memory for each core that is connected, where the core is placed in the die by way of a vertical interconnect. These applications have very high I/O counts that cannot be run to peripheral I/O, so they cannot use memory-style connections. The die are stacked in a top-to-top format. These are the designs targeted for TSVs.

There are questions, however, about whether the TSVs should be part of the IP blocks and whether the models for the IP should include the timing for vertically stacked memory. The challenge with including them in the IP is related to the large variability in post-processing options for TSV creation by the fabs. The tools needed to model the TSVs and verify the IP is being used properly are still lacking, according to the panelists. Moreover, the thermal models, changes in strain after thinning, and multi-layer capacitive coupling for the die being stacked face-to-face are issues that need to be dealt with for generalized IP use.

These problems are not unsolvable. Xilinx has released products using multi-die technology, and for fixed topology applications there is an understanding of how to solve these problems. The generalized use of TSVs randomly distributed over a custom processor die leads to the creation of custom memory configurations and pin-outs, as well.

It is unlikely that a standards group will drive the memory compilers and designers to a standard pin-out for the blocks. Because the processor cores are soft IP and have different optimization tradeoffs, there is no standardized application target that would allow for the performance tradeoffs of the cores to hit a standard pin-out. In general. these will be custom designs and custom applications. The stacked die setup is targeted for very high volume or high ASP products that can justify the high cost of test.

With respect to SoCs, this platform will likely be one of the last to address TSVs because of the impact on the design and release cycle. Packaging, thermal, timing and power issues for multi-die SoCs is very complicated and is beyond the capacity of most EDA tools, especially in the context of billion-device ICs that already are pushing the limits of the tools. Advances are being made for this area, and tool vendors have discussed options for system verification that are being targeted at this use. These are still in development, and the current releases of the tools address some but not all of the use models for TSVs and stacked die, or silicon interposer and stacked die, but are not to the design tradeoff stage as yet.

In addition, this whole area is still bracketed by cost. Traditional system-in-package and wirebond-based stacked die are still the most cost-effective for consumer commodity chips. The key is to identify a device, market and performance metric that can justify the high production cost of this technology now.

By Ed Sperling
Mentor Graphics introduced its RealTime addition to Calibre for instant signoff verification in custom IC designs. What’s interesting is DRC checking at the layout stage of the design. Mentor also won a deal with CamSemi for its design and verification flow. And it added logic and physical synthesis support for Xilinx 7 series FPGAs.

Xilinx seems to be getting lots of attention these days. Synopsys added synthesis support for Xilinx’s ISE Design Suite 13.

eSilicon inked a deal with SMS, which will use eSilicon’s semiconductor manufacturing services business to produce its WiFi chips.

Arteris ran a note that TI is using the C2C and MIPI low-latency interfaces. Our guess is it has something to do with Arteris.  The company’s earnings were positive, too, as in cash-flow positive in 2010 and profitable in Q4. Looks like NoC technology is catching on.

Microsemi leveraged its Actel acquisition last year, rolling out a vertical suite of programmable FPGAs for intelligent management of solar panels in addition to Microsemi’s traditional DC-DC converters and MOSFETs. The company plans to follow suit in other vertical markets in coming months.

On the foundry front, TSMC sales dropped 7.8% between January and February, but they were still 8.8% higher than February 2010. It’s hard to figure out exactly what’s going on here as there are too many factors in play, including the recovery, Q4 buildup, and typical first-quarter uncertainty.

By Ed Sperling
Mentor Graphics inked a deal with GlobalFoundries to extend its computational lithography to 28nm. The technology helps bridge the gap between 193nm lithography and EUV, which still isn’t ready for prime time despite years of promises and hype. Mentor also rolled out the next generation of its Questa integration and verification platform.

Cadence extended its own verification IP catalog, which most chip companies now consider a vital technology for verifying third-party IP blocks. This will be an interesting move to watch over time because it simplifies the make vs. buy decision for chipmakers in the verification space. While many companies say they see value in VIP, in the past they have been reluctant to pay for it.

Synopsys introduced new IP for the final release of PCI Express 3.0, including a new DMA engine and support for a 256-bit datapath. The company also introduced Proteus LRC for lithography verification at 28nm and below.  And it pushed deeper into the FPGA space with a methodology manual for FPGA-based prototyping jointly developed with Xilinx, and the availability of its HAPS-600 prototyping solution.

Arteris teamed up with CEVA on multicore interconnect technology for CEVA’s DSP cores. CEVA also has licensed Arteris’ FlexNoC interconnect technology.