By Ed Sperling
‘What if’ questions have become standard across multiple pieces of the design chain for any SoC, but the number is multiplying at each new process node.

When the industry begins moving to 2.5D and 3D over the next couple years, the number of tradeoffs will likely move from overwhelming to unmanageable. That will set in motion a number of efforts in semiconductor design.

So what’s behind these changes? One is simply the sheer number of tradeoffs that stem from SoCs with hundreds of millions of gates, I/O on and off the chip, an increasing amount of re-usable and commercially available IP and an overall effort by chipmakers to eke more performance for less power out of a design.

“There is no killer app anymore,” said Fred Cohen, director of the OMAP wireless ecosystem at Texas Instruments. “There are 20 of them. It’s impossible for an SoC vendor or an OEM to master all the complexity and innovation. So you need to engage with all these companies, and you need to do it almost on a daily basis.”

In the design space, that also means better modeling and more granularity for exploration. If there is an explosion of ‘what if’ dependencies, more needs to be dealt with at the architectural level. And it has to be dealt with more effectively.

“You synthesize from C or C++ down to RTL because you can simulate so many alternatives at a high level that the chances for stumbling on the optimal solution are higher,” said Wally Rhines, chairman and CEO of Mentor Graphics.

That’s been a driver behind the recent uptick in high-level synthesis and ESL modeling, but so far the tools are incomplete. All of the major EDA players say they are now working on solutions in this area.

“Models are becoming more refined,” said Frank Schirrmeister, director of product marketing for system-level solutions at Synopsys. “From there you need appropriate characterization of those models. Right now people make assumptions and then they refine those models once the data is available. The big question is yet another ‘What if.’ What happens if we move to a smaller technology node or 3D. Does it all become unmanageable?”

Lots of questions, not so many answers
Similar questions are being asked all over the semiconductor industry. In the FPGA arena, where advanced modeling has largely been hidden, companies are beginning to look at the possibility of similar design methodologies for 2.5D and 3D stacks.

“This kind of performance analysis and estimation and power analysis and estimation has never been seen in the FPGA world,” said Ivo Bolsens, chief technology officer at Xilinx. “You know the platform and understand the delay and the power consumption from building a component because you have the silicon with an FPGA, but the tools are not there to do the optimization.”

What’s important here is the ability to do architectural exploration with enough granularity to be useful. Power modeling, for example, tends to rely on high-level estimates up front, but that data is notoriously inaccurate and can cause problems further downstream in the design flow. Exploratory or “pathfinding” tools have been talked about for years, but the amount of complexity has grown at advanced nodes to the point where there is now a real market need.

Fig. 1: A 2.5D design. Source: Xilinx

Location, location, location
One of the interesting things about stacking die is a fundamental shift in what gets placed where—not so much from a thermal standpoint but from a connectivity standpoint.

This is more than a layout issue. It’s a complex series of tradeoffs between power and performance, taking into account proximity effects, heat, electromagnetic interference and even electrostatic discharge. In 3D, understanding which blocks talk with which blocks, when, and by what means isn’t a simple decision. It’s filled with tradeoffs. A processor that used to communicate over a standard bus through a general-purpose operating system may now include a dozen heterogeneous cores, each with a specific function and running at different voltages. Two or more may be working at the same time, or there may be only one important processor core running with an accelerator.

“In 3D the prime real estate will be in the center of the chip,” said Kurt Shuler, director of marketing at Arteris. “In 2D the most efficient way to route signals was at the edge of the chip. That creates a different problem set and a different set of tradeoffs. Models now have to be topographically aware, too.”

There is increasing attention being paid to network-on-chip approaches to deal with tradeoffs more easily, substituting one piece of IP for another, for example and reconfiguring the network to deal with that. “A company’s first chip might be 50% new IP and the derivatives might be 20% new IP. Within the system, the only lever for change is the interconnect. In 3D that’s a similar situation. To accommodate different subsystems you need a quick way to do that.”

Business, but not as usual
Two known good die stacked on top of each other may produce two bad die. That kind of risk cannot be overstated in stacking die because the investment is far too high for getting it wrong, both in terms of NRE costs and missing market windows. But with stacked die, risk also increases by the number of layers being stacked together.

“What 3D stacking adds is more ways of hurting or helping ourselves,” said Drew Wingard, chief technology officer at Sonics. “Once you winnow the choices based on economics, then you have to figure out what are the high-level user benefits. You may get more features, save power or energy and optimize on cost. You can see that in Apple’s approach to SoCs. Some of their products have been done with components that are behind the competition, but their focus on the user is so strong that they always hit it right.”

Those kinds of tradeoffs occur in power and performance, as well. “In general-purpose computing, you make everything run as fast as possible,” Wingard said. “It’s all about not having a choke point. SoCs are usually a set of primary use cases. They’re much more complex, and 3D will become even more complex.”

Conclusion
What emerges from discussions with engineers across the IC design space is a recognition that more has to be done up front, with greater accuracy and with greater ease. Rather than reducing the role of design engineers to the mechanics of place and route, it points to a much more complex set of tradeoffs that can be made using an automated set of tools.

“This is all about re-thinking the ‘what-if,’ said Mike Gianfagna, vice president of marketing at Atrenta. “It’s a bridge between what you propose for an on-chip interconnect, for example, and then you try out ideas. The analysis will last a few hours or, worst case, overnight. Do you need a wide TSV or a narrow TSV? Which is the best answer? What’s the projected cost and what are the parasitic routing delays.”

Gianfagna noted that the goal is an optimized configuration, which may be cheaper, lower performance for some uses, and more expensive and higher performance for others. But all of this will need to be tried out and tried again on a vast level, potentially opening vast new opportunities for tools, for a new type of expertise, and for far more interesting IC designs.

By Pallab Chatterjee
Just how ready is the semiconductor industry for stacked die? That was the subject of a recent panel discussion involving ARM, Atrenta, Xilinx, Samsung and Mentor Graphics.

The reasoning behind 3D stacking is becoming clearer at each node. I/O count and delay times are forcing different configurations, but the time frames for these changes and the gating constraints are still somewhat fuzzy.

In the area of uses, the discussion focused on three areas–memories, SoCs and computing systems (processor cores and memory). Memories have been using stacked die approaches for many years. These stacks use traditional wirebond technology, feature either standard or thinned die, and have a known cost model.

The advantage of memories is that there is common pin-out and stacked devices can utilize existing memory test methodologies by adjusting the address range for the design. The die in this application are stacked from the top of one die to the bottom of the next die. These products have shipped literally billions of parts in this technology at a very similar price point to standard wire bond. This methodology supports using known good die for the design, has compatibility with current design tools and has known thermal performance.

Computing systems have a different target for stacked die. These systems, however, require a different architecture. There is local 3D memory for each core that is connected, where the core is placed in the die by way of a vertical interconnect. These applications have very high I/O counts that cannot be run to peripheral I/O, so they cannot use memory-style connections. The die are stacked in a top-to-top format. These are the designs targeted for TSVs.

There are questions, however, about whether the TSVs should be part of the IP blocks and whether the models for the IP should include the timing for vertically stacked memory. The challenge with including them in the IP is related to the large variability in post-processing options for TSV creation by the fabs. The tools needed to model the TSVs and verify the IP is being used properly are still lacking, according to the panelists. Moreover, the thermal models, changes in strain after thinning, and multi-layer capacitive coupling for the die being stacked face-to-face are issues that need to be dealt with for generalized IP use.

These problems are not unsolvable. Xilinx has released products using multi-die technology, and for fixed topology applications there is an understanding of how to solve these problems. The generalized use of TSVs randomly distributed over a custom processor die leads to the creation of custom memory configurations and pin-outs, as well.

It is unlikely that a standards group will drive the memory compilers and designers to a standard pin-out for the blocks. Because the processor cores are soft IP and have different optimization tradeoffs, there is no standardized application target that would allow for the performance tradeoffs of the cores to hit a standard pin-out. In general. these will be custom designs and custom applications. The stacked die setup is targeted for very high volume or high ASP products that can justify the high cost of test.

With respect to SoCs, this platform will likely be one of the last to address TSVs because of the impact on the design and release cycle. Packaging, thermal, timing and power issues for multi-die SoCs is very complicated and is beyond the capacity of most EDA tools, especially in the context of billion-device ICs that already are pushing the limits of the tools. Advances are being made for this area, and tool vendors have discussed options for system verification that are being targeted at this use. These are still in development, and the current releases of the tools address some but not all of the use models for TSVs and stacked die, or silicon interposer and stacked die, but are not to the design tradeoff stage as yet.

In addition, this whole area is still bracketed by cost. Traditional system-in-package and wirebond-based stacked die are still the most cost-effective for consumer commodity chips. The key is to identify a device, market and performance metric that can justify the high production cost of this technology now.

By Ed Sperling
Mentor Graphics introduced its RealTime addition to Calibre for instant signoff verification in custom IC designs. What’s interesting is DRC checking at the layout stage of the design. Mentor also won a deal with CamSemi for its design and verification flow. And it added logic and physical synthesis support for Xilinx 7 series FPGAs.

Xilinx seems to be getting lots of attention these days. Synopsys added synthesis support for Xilinx’s ISE Design Suite 13.

eSilicon inked a deal with SMS, which will use eSilicon’s semiconductor manufacturing services business to produce its WiFi chips.

Arteris ran a note that TI is using the C2C and MIPI low-latency interfaces. Our guess is it has something to do with Arteris.  The company’s earnings were positive, too, as in cash-flow positive in 2010 and profitable in Q4. Looks like NoC technology is catching on.

Microsemi leveraged its Actel acquisition last year, rolling out a vertical suite of programmable FPGAs for intelligent management of solar panels in addition to Microsemi’s traditional DC-DC converters and MOSFETs. The company plans to follow suit in other vertical markets in coming months.

On the foundry front, TSMC sales dropped 7.8% between January and February, but they were still 8.8% higher than February 2010. It’s hard to figure out exactly what’s going on here as there are too many factors in play, including the recovery, Q4 buildup, and typical first-quarter uncertainty.

By Ed Sperling
Mentor Graphics inked a deal with GlobalFoundries to extend its computational lithography to 28nm. The technology helps bridge the gap between 193nm lithography and EUV, which still isn’t ready for prime time despite years of promises and hype. Mentor also rolled out the next generation of its Questa integration and verification platform.

Cadence extended its own verification IP catalog, which most chip companies now consider a vital technology for verifying third-party IP blocks. This will be an interesting move to watch over time because it simplifies the make vs. buy decision for chipmakers in the verification space. While many companies say they see value in VIP, in the past they have been reluctant to pay for it.

Synopsys introduced new IP for the final release of PCI Express 3.0, including a new DMA engine and support for a 256-bit datapath. The company also introduced Proteus LRC for lithography verification at 28nm and below.  And it pushed deeper into the FPGA space with a methodology manual for FPGA-based prototyping jointly developed with Xilinx, and the availability of its HAPS-600 prototyping solution.

Arteris teamed up with CEVA on multicore interconnect technology for CEVA’s DSP cores. CEVA also has licensed Arteris’ FlexNoC interconnect technology.

By Ed Sperling
It was a good week for IP.

Atrenta and TSMC will jointly develop a soft IP qualification flow. Given the percentage of commercially developed IP being used and re-used in designs, this is a very good move. Along similar lines, TSMC named Synopsys its interface IP partner of the year. Think of this as a pat on the back for qualified IP.

Cadence and Xilinx rolled out an FPGA IP ecosystem microsite. This plays well into the former ChipEstimate model, which was purchased by Cadence.

Nvidia is using Mentor’s Olympus SoC tool for MCMM design closure of its graphics processors. . Mentor’s Nucleus RTOS, meanwhile, is being used in more than 2.3 billion mobile platforms, according to the 100 Million Club. That’s a big chunk of the planet.

Sequans Communications, based in Paris, licensed MIPS’ M14Kc processor core for its mobile platforms. Sequans makes LTE and WiMax chips for communications infrastructure.

Intel will invest billions in a new state-of-the-art semiconductor fab in Oregon. The company picked the right place. There’s certainly plenty of water there.

By Pallab Chatterjee
The National Association of Broadcaster show is the one place where you can be sure to find some of the most advanced technology on the planet—the kind of stuff used to broadcast, capture and edit 3D content. But while the market for this kind of technology is growing, the quantities of like products are still not high enough to warrant ASICs.

It’s a world dominated by FPGAs, and the leaders on the equipment side are Xilinx and Actel. They accounted for just about all of the visible FPGAs on the show floor. What was particularly interesting, though, was that the chips were not even the fastest chips in the FPGA companies’ lineup. They were not at the most advanced (smallest geometry) process. And they didn’t use the largest number of cores. In fact, most of the FPGAs were one or two generations behind.

The most popular chip on the show floor was the Virtex-4, which was used in most of the single-width and height cards from Grass Valley Group, Miranda and others. The cards are either single-, dual- or quad-channel functions. Based on the card size, mechanical cabling connections and simultaneous switching characteristics, moving to a higher channel configuration than a quad does not make a lot of design sense. As a result, the older technology (90nm, 1.2v core, sub 960 I/O) does just fine with the data rates, signal integrity and jitter levels that are required for video processing. These chips can support the mainstream SD and HD data rates, the 3Gb/s SDI channels for streaming data and the high speed 6.5Gb data channels, if required.

As the chips include both DSP cores and processor cores, the codec functions needed for signal processing, and signal conditioning are easily implemented. This split architecture, supported by the local in-die memory allows the flexibility to support the multiple standards such as MPEG2, JPEG 2000 and MPEG4. As some of these standards are still being finalized and adjusted (the 3D portion of the MPEG4 specification is in progress), the in-field programmability of the FPGAs is a major asset. This will allow currently deployed equipment to be upgraded to meet the data standards as they emerge, which would not be possible with an ASIC or SoC.

The globalization of video also has changed the hardware requirements for the post-processing and broadcast communities. It is not uncommon for a single editing station to be receiving input from PAL, DVB, ATSC, P2 media, SD card, 3Gb fiber, 6Gb fiber channels, SD and 720 / 1080 HD data sources. This combo of inputs requires mixing and editing hardware to perform transformation to common formats, in addition to signal steering. This mix of data formats requires the chips have multiple clock domains with very small skews and tracking that is systematic (frame- and line-based rather than absolute psec based). The FPGA products, with their multiple distributed logic functions and distributed clock domains, fit this requirement well.

While some of the high-density video functions are power-sensitive, the broadcast signal processing cards are not. High-speed cross point switches, which may be as large as 200 x 200 channels, are shooting for power factors in the 100mW to 400mW per channel range. The signal processing cards typically consume 25W to100W/channel for the rack based systems.

For 3D, the hardware can utilize the same base chips. As the 3D formats are based on left and right eye frames each being shown at half the data rate, the performance requirements for the processing chips do not change. The new 3D capable products featured a reconfiguration of the control logic for the dual-frame format, but left the interfaces the same while remaining on the same FPGA platforms.

The display side of the 3D world (TVs and set-top boxes) is much more standardized on their data and has a much more limited I/O requirement. While these applications are good targets for SoCs and ASICs, the signal-processing world for video appears to remain the province of FPGAs.

By Ann Steffora Mutschler
In an industry that was once fraught with patent infringement lawsuits, hostile takeovers and other exciting corporate warfare, the hardware-assisted emulation market has quieted down considerably. That doesn’t mean it has lost its luster, though. It still plays an integral, if not ever-increasing and expanding, role in the verification efforts of most semiconductor companies.

EDA Consortium statistics point to an emulation market that has been hovering around the $150 million or $160 million market for three years now, down from a high of about $250 million at the turn of the millennium. Facilitating the market contraction was the dot-com bubble bursting, which caused hardware emulation system prices to tank. Industry players remain optimistic that once the semiconductor industry recovers further, the emulation market will follow.

Where it’s used
Emulation fits squarely into the scenario of the massive SoC, and the fact that today’s SoCs include more and more embedded software. Traditional verification methods like simulation or HDL simulation can’t completely verify these designs and they take too long. This is where emulation comes into play. It can be used for hardware debugging at the block and system levels and even for embedded software validation.

Specifically, emulation addresses increasing hardware complexity in SoCs, particularly with multi-processor designs as well as increasing software content that is rising faster than hardware content. Both of these issues require hours of design validation and create a productivity gap that eventually translates into a profitability gap. And now with power being an intensely critical issue, especially for mobile devices and data centers, the need to analyze power consumption is critical both for different use cases as well as to verify the SoC after low-power techniques have been implemented. In addition, power analysis and power verification need to be done for the full SoC at RTL.

Depending on which vendor you speak with – and there are three main players (Cadence, EVE, and Mentor Graphics) – hardware-assisted emulation promises to improve hardware/software integration productivity by faster bring-up times, accelerating the verification environment by factors of 100 to 10,000, enabling earlier software integration, increasing program predictability while maximizing system quality before silicon, allowing hardware/software co-verification, deploying system-level metrics and coverage and confirming architecture power and performance through analysis and verification/validation at cycle accurate level with high performance.

Who Does What
At the heart of hardware-based emulation systems today reside either FPGAs or full-custom ICs to run the system. This is where things get interesting. EVE, the relati9ve newcomer to the emulation market (now 10 years old), is FPGA-based. Lauro Rizzatti, vice president of marketing and general manager of EVE-USA, said the company set out from day one to take a different approach from its competitors. EVE’s systems are based on commercial Xilinx FPGAs, which it has come under fire for using.

“On paper your tradeoffs are quite big when you do that which is essentially what Cadence and Mentor are saying when they are attacking us—that we are using commercial FPGAs and therefore compilation time is very slow and debugging is very limited,” Rizzatti said. “It might have been true in the early days but we have been working very, very hard in software to alleviate those known weaknesses.”

In terms of slow compilation times, Rizzatti admits a roadblock would be the fact that placing and routing an FPGA is really slow and EVE does not control the place and route. It uses Xilinx’s place and route. However, he pointed out, Xilinx has done quite a bit of improvement especially in terms of runtime. To improve debugging capabilities, he said EVE has added features for control of the internal of the FPGA in part through instrumentation that it built into the FPGA to provide visibility and additional software outside the FPGA to support that.

Mentor’s Veloce emulation product contains a full custom IC with an FPGA fabric as well as some additional capabilities to give the user full visibility. Specifically, for every clock at every node in the design, Veloce records the results for the user so when they’ve completed the emulation, they have a simulation-like waveform display that has all the information they need to debug.

“Cadence and Mentor invest lots of money in these full custom chips and we do it for good reason. One is that we can compile significantly faster and more predictably, more successfully than an FPGA-based approach and two, we have full unrestricted debug capability at speed,” said Jim Kenney, director of marketing for Mentor’s Emulation Division.

Moving forward, EVE believes that given the size of the emulation market, to develop custom silicon for an emulator is too expensive even if one vendor controlled the entire market. This path was the right one in the past but not in the future, Rizzatti said.

Kenney, meanwhile, said the solution is helping to grow the size of the emulation market. That includes hardware-assisted emulation for transaction-based test benches.

“The biggest change that has happened recently in emulation is the swaying towards transaction-based,” Kenny said. “Previously, design teams did a lot in circuit emulation that involved external hardware being physically connected to the emulator in order to provide interfaces and stimulus for their design. People are still doing that of course, but lately we’ve seen customers put a lot more focus on transaction-based especially with the advent of OVM and VMM so they are doing transaction-based test benches for their simulators now.”

Ran Avinun, marketing group director for the system design and verification segment at Cadence Design Systems, agrees. “There is a new opportunity to start to address the traditional RTL advanced verification market that was not addressed by most of the EDA vendors. Vendors of advanced verification—meaning HVL-based languages such as e, System Verilog, OVM—touched the surface in the past but didn’t really address it. We are getting to the point that we can take off and this is a $400 million or $500 million market that is mostly being addressed by simulation.”

Cadence defines the market as metric-driven verification. “We are starting to address it using OVM acceleration—actually taking a lot of the expertise and methodologies experience we have with OVM both through System Verilog and e and expanding this into acceleration,” Avinun explained.

This push to transaction-based is something of a swing-back to the late 1990s when there were simulation accelerators from IKOS and Zycad, but those ran out of steam because they couldn’t provide an advantage over the quickly accelerating workstation performance along with vendors like Cadence, Mentor and Synopsys tuning up their software simulators, Kenney recalled. But now with the advent of transaction-based test benches, simulation acceleration is coming back.

Mentor never actually left the space, he pointed out. IKOS (which Mentor acquired in 2002) had been developing a transaction capability because it was seen as the only way to get decent acceleration on an emulator. Fast forward to the present and Mentor has about 150 staff years into a product that grew out of that IKOS technology, TestBench XPress, a transaction-based environment for developing and running test programs, test bench on the workstation and the DUT running in the emulator.

“The key comes in helping to accelerate the testbenches, and this is where transaction-based comes in. It allows you to accelerate a significant amount of the testbench, primarily the transactors for the verification IP (such as a transactor for AXI, AMBA, PCI Express or Ethernet). If we can move some of that into the box and accelerate it, we start seeing some really good speedups,” Kenney said.

At the same time, customers also want to be able to leverage their pricey emulation purchases by allowing the system to be used as general-purpose resource. That means putting them in their data centers as opposed to their engineering labs. This would allow jobs to be queued up instead of the box being dedicated to a single project because of the external in-circuit emulation connections that are required. This is contributing to the push towards transaction-based verification, he noted.

Very closely related to emulation are FPGA-based prototyping and virtual prototyping. In fact, many semiconductor companies utilize two of the three in their verification efforts, Mentor and Cadence confirmed. While there are tradeoffs among the platforms, it is expected all three will co-exist in the market given the specific advantages and disadvantages to each approach. (For Cadence’s take on this, click here.)

Interestingly, running these system in conjunction with each other in what could be called a “hybrid” mode is garnering increasing interest among customers with usage models including emulation with FPGA-based prototyping; acceleration with virtual prototyping (SystemC, C/C++); and acceleration and emulation.

With more and more customers moving into simulation acceleration/transaction-based acceleration, the market for emulation in these areas could propel the revenue expansion vendors have been waiting for.

Editor’s Note: It has been suggested that Synopsys may have intentions to become an emulation provider as well, but the company disagrees. Synopsys does play in the FPGA prototyping space with the HARDI Electronics technology it gained when it purchased Synplicity in 2008 (Synplicity bought HARDI in 2007) and the CHIPit business unit of ProDesign that it also acquired in 2008. And, in terms of the virtual prototyping space, Synopsys pretty much cornered the market with its acquisition of both CoWare and VaST last month. The company stressed that it has no public intentions at this time to get into general-purpose emulation — right now; the focus is on HAPs and virtual prototyping.

By Ed Sperling
The consolidation of intellectual property from small developers to large players with integrated IP blocks is accelerating. Large IP companies are now developing integrated suites that are pre-tested for specific vertical markets, and new companies are sprouting up to make it easier to put even broader collections of IP together in meaningful ways.

It’s difficult to tell whether the trend is being driven more by the IP vendors or pulled through by chip developers looking to cut costs—or whether it builds upon the stamp of approval by foundries for certain pieces of IP. The net effect, however, is the creation of subsystems and partial platforms that are one step below reference platforms.

“A reference design suggests a complete solution,” said Eric Schorn, vice president of marketing for ARM’s processor division. “Customers don’t want us to go that far. But we are moving in a segment-oriented fashion. That’s the reason we bought a graphics processor company. We are making a processor along with a graphics socket for mobile phones and set-top boxes.”

The company isn’t alone in recognizing the opportunity for putting together more pieces of IP in very specific ways. Virage Logic’s recent acquisitions of ARC and NXP’s IP unit have positioned it to lead with integrated subsystems in markets such as high-performance audio and video.

“You have to have a reference platform these days,” said Yankin Tenurhan, vice president and general manager of Virage’s ARC business unit. “That’s not much different from the good old days of silicon, though, when you needed a complete solution and a full blown prototype. Philips, NXP, Texas Instruments and ST all have demonstrator chips for whatever you want on a cell phone. The same is happening in the IP world.”

Putting together the pieces
It’s not just the IP vendors that are putting together suites of IP. Two startups are focused on making IP easier to understand and integrate. Parallel Engines, which emerged from stealth mode this week, is focused on organizing IP by data mining pertinent information about everything from power requirements to the interfaces and interconnects.

“There are 12,000 pieces of IP out there, including 8,000 pieces of hard IP that are made by about 50 companies and about 4,000 pieces of soft IP,” said George Janac, CEO of Parallel Engines. “The hard IP is already in FPGAs from companies like Actel, Xilinx and Altera. You just need the soft IP to make it work.”

Somewhat conveniently, Janac’s brother, Charlie, is the CEO of Arteris, which makes network on chip technology that can be used to glue together these IP blocks.

“A company may have one or two pieces of IP that are the secret sauce and some software,” Charlie Janac said. “Why not drop those into an FPGA and connect up the other pieces of IP? Those two worlds are merging. We’re going to see much more custom logic on an FPGA.”

Another company involved in bringing IP together is Silicon IP, run by Kurt Wolf (formerly of TSMC), who said there’s a disconnect between chipmakers and IP vendors that still needs to be closed. “The chip guys distrust the IP industry,” Wolf said. “There’s more integration of IP, but there’s still a lack of confidence about how to choose, buy and license IP.”

Wolf’s company is focused more on bringing the two sides together with better information and connecting the pieces in an organized way.

The future
All of these efforts—by both large IP vendors and startups—are signs of just how important commercial IP has become in chip development. What began with embedded processors and standard memory designs has evolved into a huge market that actually gained momentum in the recent downturn.

Outsourcing is gaining ground at every level of business, even outside of the semiconductor world, but in the past most of the gains have been in areas where there was little value add. Outsourcing traditionally has been relegated to commodity services. What’s changing is that IP now includes areas that companies cannot do themselves in addition to those they don’t want to do, as well as the extremely tedious and time-consuming integration work that is necessary to create a final product.

When most analysts predicted a massive growth in IP at the beginning of the decade they were largely talking about small, relatively unsophisticated IP blocks pieces that can be put together by highly sophisticated companies. In the future, the differentiation may be less around the technology and more on getting very complex chips assembled and to market faster for specific market segments.

By John Blyler & Ed Sperling
Is the Electronic Design Automation (EDA) tools market shrinking or growing? That depends greatly upon how you define EDA.

A recent report by the Global Industry Analysts, based on information from EDA Consortium (EDAC), predicts that the global EDA tool market eventually will re-emerge to drive growth to $9.8 Billion by 2015. The report suggests that this growth will be fueled in part by the traditional efforts to improve efficiency and performance throughout the chip development process.

EDA Chip-Level Tools
Aart de Geus, chairman and CEO of Synopsys, expanded upon this finding in a recent interview. “As a percentage of our business, classic EDA is shrinking, but this is not a case of ‘classic EDA doesn’t grow.’” For example, in the past, EDA companies added front-end RTL synthesis and design tools with timing and power closure to improve the productivity of chip designers. Next, efficiencies were found in the back-end of the process by adding physical design with extraction and Design for Manufacturing (DFM) and Yield (DFY) tools. Today, EDA vendors are improving the value of system-level design with architectural tools.

Synopsys is indeed attempting to improve their architecture tool flow with the recent double acquisitions of two electronic-system level (ESL) design companies – VaST and CoWare. The emphasis on architectural integrated circuit (IC) design productivity has pushed traditional EDA chip companies to expand into the next level of product development, namely, package and board design and – on the software side – even application development.

But this time around, productivity and efficiency within the chip development process will not be enough to save EDA. In addition to continuing improvements in both front and back-end tool design, chip-level EDA companies must be successful in reaching outward to embrace new customers and industries.

Perhaps no one understands this shift in thinking better than Mentor Graphics, who has products in the chip, package, board and even embedded real-time operating system (RTOS) markets. “We (EDA chip tools) as an industry are stubbornly targeting a limited number of customers,” said Serge Leef, vice president of new ventures and General Manager of the System-Level Engineering Division at Mentor Graphics. “We really need to figure out where to go beyond that.”

There are four choices, according to Leef. One is to sell products to existing customers, which EDA companies will continue to do. The second is to sell new products to existing customers, which they are attempting in areas such as submicron design, DFM and yield enhancement. A third option is to sell existing products to new customers in places like China and India, but most of those companies are either part of multinational companies that already buy EDA tools or they’re underfunded startups that cannot afford tools. A fourth option is to sell new products to new customers.

On paper, the last option seems the most promising. The problem is getting the new customers to look at what EDA has to offer, which means that EDA companies must understand the needs of the new customers – i.e., different industries.

IP Drives Profit
A universal need shared by most new customers in today’s economically challenged markets is that of cost reduction. This has two effects. One is to increase the use of intellectual property (IP) blocks in chip-level design while the other is to move from ASIC to FPGA-based designs.

Increasing the use of IP was a primary theme in Virage Logic’s keynote address at the recent DesignCon show. That was expected, but the arguments that were used to support the growth of IP are worth noting. Brani Buric, executive vice president for marketing and sales at Virage, explained it this way: “As we move into consumer markets with low profit margins we must think beyond the technical challenges to the business issues. The question is not just how to do the design more efficiently in terms of cost, but whether to do the design at all.”

The business focus of this approach is reflected in its name, i.e., Design for Profitability (DFP). Companies focusing on profit might just write the spec for a new chip, then hand off the rest of the design and implementation to design companies such as eSilicon or Open-Silicon. Owning the spec would typically be a lot less expensive than owning any part of the implementation process. This approach relies heavily on IP blocks to build the chip to spec.

Interestingly, the growth of IP is one of the key drivers cited by in the Global Industry Analysts report for overall EDA growth. The reason that EDA tool revenues are expected to climb in 2015 is because EDA owns IP. By including Broadcom, Qualcomm and ARM as some of the largest IP licensing companies, EDA will indeed be one of the fastest growing sectors—at least on paper. The reasoning for this inclusion, according to EDAC, is that EDA tools are an integral part of licensing the IP, so IP licensing revenues should be counted in the EDA business calculations.

EDA in the Board-Level Market
The growing reliance on FPGA-based electronics is the second trend driven by profit-focused designs. But this is another area where companies like Actel, Xilinx and Altium are trying to engage a broader customer base, e.g., medical, industrial and automotive markets.

Actel’s purchase of Pigeon Point moves that company squarely into the Advanced TCA and MicroTCA world, which has been heavily utilized by communications companies and defense. Xilinx, meanwhile, is positioning its next-generation 28nm FPGA platform to help win business in non-traditional markets. And Altium has been focusing on a single database implementation of FPGA-based, board-level products that include embedded software development.

While all of these expansions reflect broader changes in the overall semiconductor industry, real growth in the EDA sector can only come from expansion beyond traditional markets. But there will always be a nagging question facing EDA companies moving into these new markets: Is this really EDA, or are we venturing into a new sector that reaches well beyond the confines of EDA to include a true system-level approach?

By The EEFocus Staff

FPGAs are booming in China. When Clement Cheung, director of marketing and applications at Xilinx Asia Pacific showed up to give a speech recently, he was worried not many people would come. He need not have worried.

The sales of all the major FPGA vendors show a significant bump in sales to the Asia/Pacific region. In Xilinx’s case, they exceed sales in North America, and there has been a huge increase in the number of FPGA engineers and engineers using FPGAs inside of China. This follows the shift of manufacturing to the Asia/Pacific region earlier this decade.

But Cheung said China is particularly important to FPGA vendors: “We pay more attention to the growth of Chinese enterprises because only they can truly influence the country.”

The proportion of FPGAs in communications and in the enterprise fell sharply following the 2001 downturn, but FPGA vendors managed to weather the latest downturn relatively intact by limiting their presence in communications to less than 50% and by hedging across multiple other markets.

“The main reason [for growth] is the 3G network deployment in countries like China,” said Clement Cheung. This was also one of the key reasons that the Asia/Pacific reason posted strong growth. Xilinx’s growth in China has been in the double digits, Cheung said.

FPGAs have been particularly popular because they lower the barrier of entry for design companies. It currently costs millions of dollars for an ASIC mask, but an FPGA is a much less expensive alternative. Huawei, which applied for the most patents inside of China in 2008, based a lot of its work on FPGAs.

“In China, FPGA engineers have a larger number and all of them stand on the same starting line,” Cheung said. “But FPGAs are more than a pure chip game. At present, most engineers need to consider signal integrity, layout, timing and other system-level issues.”

Xilinx CEO Moshe Gavrielov pointed out that the device functions had changed in the FPGA industry over the past 25 years, evolving from the simple circuit such as peripheral interface and glue logic to the main chip of whole system. “The concept of platform was not obvious because customers didn’t need too many application designs in the past. Today, the chip, software and whole design environment all need to be combined together for the project design.”

–EEFocus is the Chinese media partner of System-Level Design.