Jasper Design Automation introduced a power-aware version of its formal verification tool, adding optimization for multiple voltage and power-management domains. The tool now can create an internal power-aware formal model based upon power partitioning specs.

Real Intent teamed up with DeFacTo Technologies to deliver an RTL signoff flow for both clock-domain crossing and design for test, which the companies say speeds up the signoff process. There has been a lot of attention focused on the growing signoff problem over the past few months.

Achronix taped out a finFET-based FPGA using Synopsys’ physical design and verification. FinFETs should greatly improve the power/performance characteristics of FPGAs, which is why there has been a big rush by FPGA vendors to the latest node.

South Korea’s MagnaChip adopted Mentor Graphics’ process design kit automation process and custom IC platform. MagnaChip makes AMS semiconductor platforms. The company also won a deal with CNH, which makes agricultural and construction equipment for its wiring and harness design software tools, which are becoming more popular as off-road vehicles add more sophisticated electronics.

Yamaha was able to reduce power consumption for its mobile consumer chips by 10% using Cadence’s characterization tools. The improvements are the result of automating the functional descriptions of cells and the specification of worst-case conditions.

Open-Silicon celebrated its 10th anniversary. The company has shipped more than 78 million chips over that period.

People may be overweight, but at least they’re putting their money where their mouths are—so to speak. Shipments of sports and fitness monitors will total 250 million units between 2013 and 2017, according to IHS iSuppli.

Android and iOS accounted for 92.3% of all smartphone OSes shipped in Q1, according to IDC, and Android’s share accounted for 75% compared with iOS’s 17.3%. Moreover, while shipments of iOS increased from Q1 2012 to the same period in 2013, its market share dropped nearly 6%. Android’s shot up nearly 17%.

By Ed Sperling
Synopsys continued its buying spree, acquiring verification IP developer ExpertIO. Synopsys will absorb the entire ExpertIO team, including CEO Craig Stoops, into its verification group. Terms of the deal were not disclosed. What’s particularly interesting is that ExpertIO’s partners include all of the Big Three EDA vendors.

Synopsys also is collaborating with Sigrity to accelerate signal integrity analysis, and it won a deal with Yamaha, which is standardizing on its Processor Designer tool for custom DSPs.

Mentor Graphics won a deal with Altera, which will use its Voloce emulator to verify its next-generation FPGAs.  Mentor also won a deal with Fujitsu Semiconductor, which is expanding its use of Mentor’s Calibre platform for physical verification and DFM. e

Open-Silicon rolled out a 28nm version of its Interlaken IP core for chip-to-chip packet transfers for networking products.

Arteris reported more than 100% growth in NoC technology licensees in 2011. The number is now 39, up from 18 at the beginning of last year.