<?xml version="1.0" encoding="UTF-8"?><rss version="2.0"
	xmlns:content="http://purl.org/rss/1.0/modules/content/"
	xmlns:dc="http://purl.org/dc/elements/1.1/"
	xmlns:atom="http://www.w3.org/2005/Atom"
	xmlns:sy="http://purl.org/rss/1.0/modules/syndication/"
		>
<channel>
	<title>Comments for System-Level Design</title>
	<atom:link href="http://chipdesignmag.com/sld/comments/feed/" rel="self" type="application/rss+xml" />
	<link>http://chipdesignmag.com/sld</link>
	<description>Deep Insights for Chip Architects and Engineers</description>
	<lastBuildDate>Wed, 15 Jun 2011 14:29:30 +0000</lastBuildDate>
	<sy:updatePeriod>hourly</sy:updatePeriod>
	<sy:updateFrequency>1</sy:updateFrequency>
	<generator>http://wordpress.org/?v=</generator>
	<item>
		<title>Comment on EDA&#8217;s Big Hurdles by ed</title>
		<link>http://chipdesignmag.com/sld/blog/2011/06/05/edas-big-hurdles/comment-page-1/#comment-13457</link>
		<dc:creator>ed</dc:creator>
		<pubDate>Wed, 15 Jun 2011 14:29:30 +0000</pubDate>
		<guid isPermaLink="false">http://chipdesignmag.com/sld/?p=5009#comment-13457</guid>
		<description>It depends on how you define EDA. The classical portion of EDA--place and route, synthesis, etc.--has definitely lost momentum. It&#039;s just too expensive to get chips out the door. That&#039;s the biggest problem that EDA has to wrestle with because it limits the number of customers who can use EDA tools. EDA has always existed with the blessing of the big IDMs, but the problems they have solved over the years have created even more difficult problems--and those problems collectively cost too much to solve. That has to be fixed, or Moore&#039;s Law will become irrelevant. One way to do that is re-use of IP, IP subsystems, and changing what&#039;s put into a package. That turns the biggest challenges into integration and faster software code development, which is where a lot of the attention is now focused. Is that classical EDA? No, and the backgrounds of people may change from electrical engineering to an expertise in physics, software, math and business. Maybe it needs a different name, but the broader business of solving these new problems is just getting started.</description>
		<content:encoded><![CDATA[<p>It depends on how you define EDA. The classical portion of EDA&#8211;place and route, synthesis, etc.&#8211;has definitely lost momentum. It&#8217;s just too expensive to get chips out the door. That&#8217;s the biggest problem that EDA has to wrestle with because it limits the number of customers who can use EDA tools. EDA has always existed with the blessing of the big IDMs, but the problems they have solved over the years have created even more difficult problems&#8211;and those problems collectively cost too much to solve. That has to be fixed, or Moore&#8217;s Law will become irrelevant. One way to do that is re-use of IP, IP subsystems, and changing what&#8217;s put into a package. That turns the biggest challenges into integration and faster software code development, which is where a lot of the attention is now focused. Is that classical EDA? No, and the backgrounds of people may change from electrical engineering to an expertise in physics, software, math and business. Maybe it needs a different name, but the broader business of solving these new problems is just getting started.</p>
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		<title>Comment on EDA&#8217;s Big Hurdles by Wes Lentie</title>
		<link>http://chipdesignmag.com/sld/blog/2011/06/05/edas-big-hurdles/comment-page-1/#comment-13386</link>
		<dc:creator>Wes Lentie</dc:creator>
		<pubDate>Fri, 10 Jun 2011 17:38:31 +0000</pubDate>
		<guid isPermaLink="false">http://chipdesignmag.com/sld/?p=5009#comment-13386</guid>
		<description>Come on Ed, EDA is dead. Just look at DAC - there has been no new blood coming into EDA for centuries. Just a bunch of old, has-beens running the big EDA companies and Gary Smith. Gary has been wrong more often than a broken clock and all he does is praise Wally so Mentor can keep paying him (where is Icahn?). But he&#039;s all EDA&#039;s got. Cooley? You pay enough and Cooley, like Gary, will publish whatever you want. Every year we hear the same old drivel from narcissist-Aart and Wally (difficult to say who is the less &#039;original&#039; thinker between the two); there are no risk takers, no one is funding any new start-ups (hence innovation is dead). Any one who could has escaped EDA and all that is left is the inmates running an asylum that is decrepit and crumbling.</description>
		<content:encoded><![CDATA[<p>Come on Ed, EDA is dead. Just look at DAC &#8211; there has been no new blood coming into EDA for centuries. Just a bunch of old, has-beens running the big EDA companies and Gary Smith. Gary has been wrong more often than a broken clock and all he does is praise Wally so Mentor can keep paying him (where is Icahn?). But he&#8217;s all EDA&#8217;s got. Cooley? You pay enough and Cooley, like Gary, will publish whatever you want. Every year we hear the same old drivel from narcissist-Aart and Wally (difficult to say who is the less &#8216;original&#8217; thinker between the two); there are no risk takers, no one is funding any new start-ups (hence innovation is dead). Any one who could has escaped EDA and all that is left is the inmates running an asylum that is decrepit and crumbling.</p>
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		<title>Comment on Who&#8217;s In Control? by Tom Quan</title>
		<link>http://chipdesignmag.com/sld/blog/2011/05/26/who%e2%80%99s-in-control/comment-page-1/#comment-13179</link>
		<dc:creator>Tom Quan</dc:creator>
		<pubDate>Thu, 26 May 2011 19:42:14 +0000</pubDate>
		<guid isPermaLink="false">http://chipdesignmag.com/sld/?p=4914#comment-13179</guid>
		<description>I would argue that TSMC has built a very comprehensive and deep ecosystem covering RDA, IP and design services, rival by none.</description>
		<content:encoded><![CDATA[<p>I would argue that TSMC has built a very comprehensive and deep ecosystem covering RDA, IP and design services, rival by none.</p>
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		<title>Comment on Version Control Nightmares by Shiv Sikand</title>
		<link>http://chipdesignmag.com/sld/blog/2010/12/16/version-control-nightmares/comment-page-1/#comment-12658</link>
		<dc:creator>Shiv Sikand</dc:creator>
		<pubDate>Mon, 18 Apr 2011 18:22:04 +0000</pubDate>
		<guid isPermaLink="false">http://chipdesignmag.com/sld/?p=4016#comment-12658</guid>
		<description>The challenge is no longer revision control. The real difficulties lie in building content management systems that understand IP and their derivative relationships and the ability to propagate both data and meta-data between parents and children incrementally and bi-directionally.</description>
		<content:encoded><![CDATA[<p>The challenge is no longer revision control. The real difficulties lie in building content management systems that understand IP and their derivative relationships and the ability to propagate both data and meta-data between parents and children incrementally and bi-directionally.</p>
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		<title>Comment on Embedded Computing Down To Two Major Camps by JTK</title>
		<link>http://chipdesignmag.com/sld/blog/2011/01/27/embedded-computing-down-to-two-major-camps/comment-page-1/#comment-12399</link>
		<dc:creator>JTK</dc:creator>
		<pubDate>Tue, 15 Mar 2011 17:44:38 +0000</pubDate>
		<guid isPermaLink="false">http://chipdesignmag.com/sld/?p=4220#comment-12399</guid>
		<description>Interesting article!  Thanks for distilling the issues.</description>
		<content:encoded><![CDATA[<p>Interesting article!  Thanks for distilling the issues.</p>
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		<title>Comment on EDA Forecast: More Clouds by Harry Gries</title>
		<link>http://chipdesignmag.com/sld/blog/2011/02/24/eda-forecast-more-clouds/comment-page-1/#comment-12353</link>
		<dc:creator>Harry Gries</dc:creator>
		<pubDate>Mon, 07 Mar 2011 06:00:54 +0000</pubDate>
		<guid isPermaLink="false">http://chipdesignmag.com/sld/?p=4430#comment-12353</guid>
		<description>I guess if you keep repeating the message enough times, eventually people will listen. I predict that within the next 6-12 months, you will see at least 1-2 major companies in the industry make a big move towards the cloud. Verification is certainly the most likely 1st application.</description>
		<content:encoded><![CDATA[<p>I guess if you keep repeating the message enough times, eventually people will listen. I predict that within the next 6-12 months, you will see at least 1-2 major companies in the industry make a big move towards the cloud. Verification is certainly the most likely 1st application.</p>
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		<title>Comment on Progress Report: Nanoelectronics by HERBCYCLOPEDIA</title>
		<link>http://chipdesignmag.com/sld/blog/2009/09/24/progress-report-nanoelectronics/comment-page-1/#comment-12210</link>
		<dc:creator>HERBCYCLOPEDIA</dc:creator>
		<pubDate>Fri, 25 Feb 2011 06:49:47 +0000</pubDate>
		<guid isPermaLink="false">http://chipdesignmag.com/sld/?p=1607#comment-12210</guid>
		<description>I indeed think nanotechnology has a great future.</description>
		<content:encoded><![CDATA[<p>I indeed think nanotechnology has a great future.</p>
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		<title>Comment on Tailoring IP, Tools And Flows by Paula Jones</title>
		<link>http://chipdesignmag.com/sld/blog/2011/01/27/tailoring-ip-tools-and-flows/comment-page-1/#comment-12198</link>
		<dc:creator>Paula Jones</dc:creator>
		<pubDate>Thu, 24 Feb 2011 18:00:04 +0000</pubDate>
		<guid isPermaLink="false">http://chipdesignmag.com/sld/?p=4248#comment-12198</guid>
		<description>Yes, the world is getting more and more application-specific. Yet it still costs too much to make one chip for every single application. Because of the cost of chip design, it’s important to make one chip that could be used, for example, in an entire line of printers – so certain features would be turned on and off depending on the exact model. This requires programmability, and that’s why processor-based solutions make sense.

Tensilica is all about tailoring IP. That’s why you can start with our base Xtensa processor architecture and tailor it for everything from our HiFi Audio to our newest ConnX BBE64 LTE Advanced DSP and lots of things in between. Tensilica’s expertise is in providing not just the base architecture but also tools that automate the customization process plus generate a complete matching software tool chain, so you’re always assured of a matching compiler, simulators, debuggers, etc.</description>
		<content:encoded><![CDATA[<p>Yes, the world is getting more and more application-specific. Yet it still costs too much to make one chip for every single application. Because of the cost of chip design, it’s important to make one chip that could be used, for example, in an entire line of printers – so certain features would be turned on and off depending on the exact model. This requires programmability, and that’s why processor-based solutions make sense.</p>
<p>Tensilica is all about tailoring IP. That’s why you can start with our base Xtensa processor architecture and tailor it for everything from our HiFi Audio to our newest ConnX BBE64 LTE Advanced DSP and lots of things in between. Tensilica’s expertise is in providing not just the base architecture but also tools that automate the customization process plus generate a complete matching software tool chain, so you’re always assured of a matching compiler, simulators, debuggers, etc.</p>
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		<title>Comment on Version Control Nightmares by Srinath Anantharaman</title>
		<link>http://chipdesignmag.com/sld/blog/2010/12/16/version-control-nightmares/comment-page-1/#comment-10585</link>
		<dc:creator>Srinath Anantharaman</dc:creator>
		<pubDate>Fri, 17 Dec 2010 20:42:40 +0000</pubDate>
		<guid isPermaLink="false">http://chipdesignmag.com/sld/?p=4016#comment-10585</guid>
		<description>This is a very timely and accurate description of the problems with managing the explosion of design data distributed across multiple design centers. Over the past dozen years, we’ve seen a steady rise in design teams large and small, in multinationals and startups, coming to grips with the need for version control and design data management. Recently, with the growth in analog and mixed-signal content on every chip, the need is becoming acute. Just this year, we’ve had over 20 startups and small design groups (10 engineers or less) adopt our hardware configuration management system (HCM - version control and design data management built specifically to meet the requirement of hardware design teams). Design teams are realizing that the problems you have highlighted are very real and they are taking steps to address them.</description>
		<content:encoded><![CDATA[<p>This is a very timely and accurate description of the problems with managing the explosion of design data distributed across multiple design centers. Over the past dozen years, we’ve seen a steady rise in design teams large and small, in multinationals and startups, coming to grips with the need for version control and design data management. Recently, with the growth in analog and mixed-signal content on every chip, the need is becoming acute. Just this year, we’ve had over 20 startups and small design groups (10 engineers or less) adopt our hardware configuration management system (HCM &#8211; version control and design data management built specifically to meet the requirement of hardware design teams). Design teams are realizing that the problems you have highlighted are very real and they are taking steps to address them.</p>
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		<title>Comment on Experts At The Table: The Hidden Costs In Design by Gary Dare</title>
		<link>http://chipdesignmag.com/sld/blog/2010/11/12/experts-at-the-table-the-hidden-costs-in-design-2/comment-page-1/#comment-9930</link>
		<dc:creator>Gary Dare</dc:creator>
		<pubDate>Wed, 17 Nov 2010 04:05:47 +0000</pubDate>
		<guid isPermaLink="false">http://chipdesignmag.com/sld/?p=3866#comment-9930</guid>
		<description>Readers interested in this topic should definitely explore the possibility of virtual platforms in their design process.</description>
		<content:encoded><![CDATA[<p>Readers interested in this topic should definitely explore the possibility of virtual platforms in their design process.</p>
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	</item>
</channel>
</rss>

