Comments for System-Level Design

Comment on FinFET Technology by ed

ed — Mon, 03 Jun 2013 10:29:36 +0000

What’s the problem?

Comment on Mythbusting: Co-Design by Kevin Cameron

Kevin Cameron — Wed, 27 Mar 2013 18:44:47 +0000

Manycore/parallel programming needs a hardware-like approach to software design, which can be addressed by bringing some aspects of HDLs into C/C++, and a large chunk of that can be done in open-source (g++/clang).

http://parallel.cc

Since the EDA companies wouldn’t make much money on that approach unless they can get their C++ synthesis flow working better, I’m sure they won’t be pushing for it anytime soon.

The disconnect is also due to the hardware design paradigm being stuck at RTL where no programmer wants to go. A higher level paradigm like CSP or asynchronous FSMs would work for both camps.

Comment on The Rise Of Layout-Dependent Effects by Hazem Hegazy

Hazem Hegazy — Thu, 14 Mar 2013 22:59:12 +0000

In our discussions with customers we concluded that LDEs like well proximity and stress have minimal impact on design architectures. For example, variation in circuit performance due to such effects is only ~3-4% on a stable 45nm process node. As technology advances, we are hearing about less variability because of the increased regularity in standard cell layouts. For example, at the 28nm process node, our observations have shown standard cell delay variability approaching half of what is typical at 45nm.
In general, LDEs causing circuit variability tend to be handled during the cell/device characterization phase. With inherently low variability in the building blocks, the contribution of LDEs to full chip variation is captured with LVS tools in the normal design flow and is easily corrected.

Comment on The Current State Of Model-Driven Engineering by Olaf Barheine

Olaf Barheine — Fri, 21 Dec 2012 08:27:07 +0000

MDSD is a good thing, because it significantly speeds up the development process, especially when the source code is generated from the models with a good quality. I myself use the UML since more than a decade. One problem, however, are those project partners who do not know UML well enough or not at all, because they are for instance hardware experts and not software designers. In those cases it can be very time consuming to explain the meaning of all these diagrams.

Comment on Power Trumps Performance In Mobile Design by jb

jb — Fri, 02 Nov 2012 17:21:58 +0000

Hi Jim. Good points. Moore’s Law has a lot of momentum in the semiconductor community, but mobile consumers live by the Power Law (battery life).

Comment on Power Trumps Performance In Mobile Design by Jim

Jim — Tue, 30 Oct 2012 18:28:33 +0000

This is a really insightful article. If mobile companies begin to target advancements in power over advancements in features I think this could honestly be revolutionary. Why does Moore’s Law not apply in this sphere? Because not enough attention is paid to it. If Blackberry wants an edge on Apple this could be somewhere they might want to look.

Comment on System Bits: October 16 by F David Patcg

F David Patcg — Wed, 17 Oct 2012 00:04:18 +0000

Some questions.
1. If only a drop of the suspension liquid is place after the first pass, are the particles washed away?
2. If too much of the suspension liquid is used in the second pass, are the particles washed away?
If yes to both, then the relative amount of suspension liquid is critical. Also the suspension liquid is bound to the particles in it and are not free to wash away previous coated particles.
Do you agree with this?

Comment on Where Does It Hurt? by Zvi Or-Bach

Zvi Or-Bach — Sat, 06 Oct 2012 16:52:31 +0000

Yes,3D IC is a compelling path for future scaling but not just the stacking version/TSV but far more so the monolithic 3D IC, with <100nm thin silicon layer. In fact it is now clear that the leading vendors in scaling – the NV NAND vendors are moving aggressively into monolithic 3D technologies. And we would expect that the logic vendors eventually will follow. For 'scaling-up' (3D), we need very rich vertical connectivity that is orders of magnitudes better than what TSV provides. And the good news is that the fundamental patent for ion-cut expired last month, so now many vendors could adapt this exciting technology for 3D IC.

Comment on Hardware-Software Tops Priority List For ASIC Prototypers by Thermal Loft Insulation

Thermal Loft Insulation — Tue, 04 Sep 2012 09:51:13 +0000

Nice Info about prototyping priorities 2012.But I want to know what the exact bring-up time should be.

Comment on EDA’s Cloudy Vision by Gary Smith

Gary Smith — Thu, 24 May 2012 23:22:49 +0000

It’ll get more complicated as IC Design moves to a Heterogeneous Computer environment while the Cloud remains Homogeneous.

Gary