By Tiffany Sparks
This month, the eyes of the electronics industry were literally and figuratively on the Consumer Electronics Show. Reports put attendance for CES at upwards of 150,000 people. Just to put that figure in perspective, that’s roughly equivalent to the entire population of cities like Springfield, Mass., or Sioux Falls, S.D. (according to Wikipedia). And that’s actually larger than the population of other cities like Bridgeport, Conn.; Syracuse, N.Y.; Alexandria, Va., or Sunnyvale, Calif.

News articles, product reviews, blogs, and re-caps about the latest and greatest innovations showcased at CES dominated the Internet and our industry’s consciousness this month. With 2,700 exhibitors, it seems everyone (outside of Apple, of course) was there to show the latest products that feature electronics, and a press contingent of roughly 5,000 international journalists were on hand to write about it. It would be interesting to find out how many thousands of articles and blogs were written about products at CES.

I personally read dozens of articles with obligatory mentions of tablets, smart phones, and game consoles. There were write-ups on 55-inch organic LED or OLED HDTV screens. Some articles were on things getting smaller (tablets), while others focused on things getting bigger (does anyone truly need a 100-inch flat screen?) Articles on the automotive sector focused on electronics driving infotainment as well as plug-in and solar technology. Then, there were a few mentions of smart fridges and electronics that are driving functionality in household appliances like stoves and washing machines. Ah, all well and good—devices that should continue to make our lives easier and even more convenient. But, I’ll be honest, it sounded a bit humdrum.

By most accounts, a single gadget didn’t steal the spotlight this year. Annually, most of the CES reporting tends to focus on what I’d call the “sexy” stuff—those things that are extremely attractive to the average consumer with hot brand names. That’s understandable to appeal to the mass market. However, it’s good to also celebrate those innovative products using semiconductor technology that can have a profound effect on individuals outside the mass market.

This month’s edition of IEEE Spectrum featured what is described as “14 life-altering, game-changing advances” in its 2012 Top Tech Special Report. Some of the advances written about already have been making news, such as 3D ICs, extreme ultraviolet lithography (EUV) and the proliferation of plug-in cars. But the report also looks at advances that will truly change people’s lives.
The first article is about an exoskeleton walking suit developed by California-based Ekso Bionics, that uses robotics to enable paraplegics to walk. The article talks about how advances in power efficiency enabled weight in the exoskeleton to be redistributed, making the suit less clunky than if it needed to rely on bigger batteries and motors. A new model of Ekso’s exoskeleton will have walking sticks with “motion sensors that communicate with the legs, allowing the user to have complete control.” Wow, how amazing that must be for someone who lost the use of their legs.

Another life-altering advance is the creation of a retinal prosthesis that will allow certain people who are without sight to see again. A system created by Second Sight Medical Products uses a tiny video camera, visual processing unit and an array of electrodes implanted in each eye. Bionic vision—how cool is that, especially to the roughly 200,000 people in the United States and Europe that could benefit from the system, according to the article.

The sheer size and scope of CES on its own has a certain “Wow” factor. However, incessant news about more power-efficient and application-rich smart phones and tablets loses some of the sizzle in the vortex that is CES. With so much coverage and focus, I guess I’m getting numb to that. But IEEE Spectrum’s coverage on impressive advances like an exoskeleton walking suit and bionic vision have me once again marveling at the power of semiconductor chips and the life-altering impact they truly can have. Wow, indeed.

–Tiffany Sparks is senior director of corporate marketing at Atrenta.

By Mike Gianfagna
Growing up in New York City leaves lasting memories. The coming holiday season evokes some strong ones. The Christmas tree in Rockefeller Center is an example. Christmas always seemed to radiate in all directions from that huge tree perched above the ice skating rink behind Radio City Music Hall. And then there was the ball dropping on New Year’s Eve in Times Square. For the most part, New Yorkers don’t understand time zones on that evening. Midnight in Times Square ushers in the New Year for the entire planet, at that instant in time, period. All these memories are colored with a combination of fantasy and reality.

As New Year’s Eve approaches once again, I begin thinking about the future. What will 2012 bring? Will the economy continue to mend? What will the presidential election mean to all of us? These are important questions, but I would like to focus on something closer to home: What will the EDA landscape look like in December 2012? OK, not as lofty a topic, but nonetheless important for at least some of the readers of this blog. I would like to make some rather bold predictions that have a helping of both fantasy and reality. This seems appropriate for the holiday season. Here we go…

Foundry consolidation will certainly continue to occur. Will we be able to count the number of companies building 45nm and below material on one hand? And if that consolidation continues, what will become of the business we currently call “mainstream EDA?” Today, the mainstream of EDA is defined by the tool chain that starts at logic synthesis and ends at mask data preparation. That tool chain is getting more focused and tuned to the manufacturing process every day. So, what if there are only five or less process targets? Is that really a market, or simply another opportunity for consolidation?

I see consolidation as a distinct possibility. With that in mind, here are my “predictions” for what the EDA landscape will look like in December 2012:

TMSC will buy Synopsys and spin out everything above logic synthesis, forming New Company No. 1.

Not to be left out, GlobalFoundries will acquire Cadence and do the same thing. Now we have New Company No. 2.

All this M&A activity will attract a group of “EDA insider” private investors to pool resources. They will collectively decide that it’s time to do an EDA roll-up. That roll-up will include select parts of Mentor Graphics, as well as a few other small EDA firms. New Company No. 3 is born. As part of that transaction, the remaining foundries will bid against each other to acquire the Calibre business from our investment group, and that one will be fun to watch. Who will win? It may not be TSMC or GlobalFoundries.

So who are the Big Three in EDA when all this settles down? It’s a different landscape for sure. Who knows what the names will be, but EDA will be different and hopefully better. Better in the sense that the focus will now be on higher levels of abstraction, an area that could find new customers and new budget. I’ll be the first to admit that these predictions are a bit “out there.” Recall my comments about blending fantasy and reality. The logic that leads me to these outcomes has holes—quite a few, in fact. Regardless, all of this *could* happen. I’d like to hear your views on the subject.

In the meantime, have a great holiday season. If you work in investor relations at Synopsys, Cadence or Mentor, don’t wander too far from the telephone though.

–Mike Gianfagna is vice president of marketing at Atrenta.

By Tiffany Sparks
“Time-to-market” and “time-to-volume” – are they overused marketing buzzwords? Until recently, I would have argued yes.

After all, it seems like very few solutions in the semiconductor supply chain are not marketed along the lines of addressing time-to-volume or time-to-market challenges. But just because buzzwords become trite, it doesn’t mean they aren’t still relevant.

In fact, perhaps it is just the opposite.

During a presentation at the recent TSMC Open Innovation Platform Forum, there was a reference to shortening time-to-volume windows for consumer electronics devices. I’d seen the data before, as Semico has published it for years. But perhaps I had become de-sensitized, because it was the context that proverbially whacked me over the head and made me more carefully consider and appreciate the time-to-market and time-to-volume challenges the industry faces today.

From the time black-and-white TVs were introduced, it took nearly 20 years for 1 million units to be sold. When color TVs came along, that time span was cut in half with the first 1 million units sold roughly over a decade. Then, it took just about 7 years to move the first 1 million VCRs, but it took just a year to move the first 1 million DVD players upon their introduction.

Apparently, it took 74 days to sell the first million units of the original Apple iPhone. Now, Apple’s latest version of its smartphone, the iPhone 4S, topped 4 million units sold the first weekend it was available—including 1 million pre-orders in the first 24 hours—in what was a new record for the iPhone.

Wow.

Take a moment to think, or rather appreciate, what it takes to get a product like this to market. Consider the entire supply chain from design, sourcing, prototyping, and ramp-up, and the many players participating in this supply chain: semiconductor, third-party IP, design tools, design services, foundries, materials vendors, distributors, test and packaging, software and content providers, OEMS and much more.

Time-to-volume is not merely a buzzword. It’s a major accomplishment. And what do you do for an encore?

Consumers will continue to demand their products to be smarter, faster, better … and cheaper too, of course. And these aren’t just new products, but replacement products as well. Time-to-market windows will continue to shrink, and reliable time-to-volume will continue to be vital.

So the pressure on the design chain will continue to grow. Do you really have any time for re-spins or delays when you’ve got a customer like Apple breathing down your neck to deliver so volume can be ramped for millions of units to be delivered in a window of mere days? First-time right, time-to-market and time-to-volume are all alive and well, but now they need to be underlined, in bold, with three exclamations coming after them to articulate the urgency and importance.

How will the EDA industry keep up and meet the challenges of time to market (!!!) and time to volume (!!!)? I don’t know the precise answer.

But I do know that there is no other option.

–Tiffany Sparks is senior director of marketing communications at Atrenta.

By Tiffany Sparks
Lately, I find myself in a reflective mood, pondering what’s changed over the past 10 years.

Of course, with the 10th anniversary of 9/11 earlier this month, there’s been intense focus on what the world was like 10 years ago and what has changed since that fateful day: the thousands of lives lost, first on 9/11, then the lives lost in Afghanistan and Iraq; the geo-political changes in the United States and around the world as we’ve waged a war on terror; the changes in air transportation (before redress numbers, plastic bags, three ounce containers and full body scanners) and the intense focus on security. Yes, so much has changed … and when I think of that anniversary it is with a heavy heart because to me, the world became a darker place that day.

But while 9/11 is a somber anniversary, there’s another 10-year anniversary that takes me in another direction. One of awe and wonder.

Oct. 23, 2011 marks the 10th anniversary of the introduction of the iPod (it officially was not released until Nov. 10, 2001 though). Can that only be 10 years ago? Do you remember a time when “iPod” and “downloads” weren’t part of our every day lexicon? And it was just 10 years ago! On the day the iPod was introduced, Apple’s stock was $9.07 (adjusted for dividends and splits). Now it hovers around $400, and Apple is challenging Exxon as the most capitalized company in the world. The iPhone wasn’t introduced until 2007, and the iPad came out in April 2010. It is mind-boggling (to me) to think about the industries spawned just from these devices.

A big part of my reflective mood is personal. I recently changed jobs after 10 years, leaving the foundry industry to return to the EDA industry. When I joined my previous company just over 10 years ago, 0.13 and 0.18 micron were the major nodes in production, 90nm was leading edge, and 300mm production was just getting started. “Convergence” was being discussed as a hot trend, but computer, communications and consumer were largely disparate markets. And 10 years later … 28nm is leading edge, millions and millions of 300mm wafers have been shipped, and computer, communications and consumer have converged to the point where it is hard to know where one stops and the other starts. Now, we have smart phones, tablets and clouds.

And as I return to the EDA industry, I find that EDA has changed quite a bit, too (although the love of acronyms remains). Ten years ago, EDA was focused mostly on the back-end of design with physical implementation. While that is still important, there seems to be a growing interest in solutions that help streamline the design process at the front-end. System Realization and SoC Realization are emerging as new EDA focus areas, and what used to be a single chip is becoming a 3D stack of chips.

So innovation marches on.

Yes, 10 years ago, there was no iPod. As well as no Facebook, Twitter or Linked-In. Now, I wonder what the next 10 years will bring. I’m not a futurist. I don’t have a crystal ball. But I know the designs will continue to get more complex. Time-to-market windows will continue to shrink. Spoiled consumers will continue to ask for better graphics, more functionality, longer battery life and a lower cost. And innovation will continue.

Ten years ago, I only used my mobile phone for phone calls and messages. Today, I call, text, check email, take pictures, play games, get news, watch video, get directions and check traffic.

What kind of device will we have in 10 years? If the last 10 years of innovation are any indication of things to come, it will be more than we can imagine today.

–Tiffany Sparks is senior director of marketing communications at Atrenta.

By Kiran Vittal
In a December 2010 blog, my colleague Ron Craig wrote that 94% of respondents to a survey said that timing constraints were a problem. Well, no surprise there. But 70+% said they planned to simply “try harder” during their next project to avoid these problems. Did they really think that was a viable solution?

That blog featured a good illustration of the problem. It gave me a good laugh.

But I want to set the record straight. Not everyone thinks “trying harder” is the only solution. Test engineers are proving to be more evolved and forward thinking.

It wasn’t long ago that the design community didn’t ostensibly care about test. At the front end, RTL designers focused more on clocks, reset connectivity and scannability. Yes, they needed to pay attention to design-for-test guidelines and SoC DFT connectivity, but they were also perfectly happy to throw their design over the wall to the DFT expert. It was the job of the DFT expert to focus on test quality and coverage, at-speed test and ATPG/MBIST. For any problems, the DFT expert would throw it back over the wall to the designer for iterations. Seemingly, the two sides lived in different worlds.

That situation is changing. The test problem is seeing more visibility throughout the organization, and more is being done up front. What is driving this?

Of course, a big factor is the increasing complexity of designs. Given the size of today’s SoCs, designers are no longer able to design all the IP blocks from scratch, so there is much wider adoption of third-party IP. With that comes the need to qualify and verify the IP. You need to know if the chip will function according to your design intent, and that requires careful test planning. Also, as we move down the technology curve past 45nm, another issue that has cropped up is the problem of “at-speed” defects. No longer are we looking at merely “stuck-at” fault defects. The cost of the chip is increasing because of the need for at-speed testing based on an actual use model rather than a limited test pattern. And that is making the test problem quite a bit more difficult.

Then there’s the challenge created with additional functionality. Today’s mobile devices function as GPS and MP3 players, along with being phones, cameras, video recorders and much more. And the SoCs behind these mobile devices need to function in these different modes seamlessly, so they need to be designed in such a way that the chip goes into a particular mode of operation as required. That too requires more sophisticated test strategies.

All of this is against the ever-present backdrop of the time-to-market challenge. In a fast-moving, consumer-driven environment, missing a market window can literally be a death knell for a product or even a company. A matter of weeks could make or break the success of a product line. Test can have considerable impact on design schedules. Functional changes made during post-synthesis place-and-route can profoundly impact test quality. Throwing it back to the designer could add weeks to the schedule.

A better way is emerging. We are seeing a growing use of RTL test analysis tools. Tools that verify IP quality early, measure the completeness of at-speed tests, and determine if a design will achieve 98% or 99% stuck-at coverage. Test engineers, engineering managers and RTL designers alike are realizing that addressing DFT early, at RTL, will make things easier on the back-end design flow. RTL engineers and DFT experts are working together more effectively. And that is highly evolved behavior.

–Kiran Vittal is director of product marketing at Atrenta Inc.

By Mike Gianfagna
I’ve always been a fan of superhero movies. I would say the Terminator series is the last time I really liked Arnold Schwarzenegger. I bet I’m not alone in that opinion. I think it’s terrific when downtrodden bands of X-Men use their strange powers to defeat evil.

The summer blockbuster season is in full swing with movies like Green Lantern and Captain America. A good time will be had by all. At the heart of these movies, there is a basic premise of good triumphing over evil. But what sets the true blockbuster apart from the also-rans (besides great special effects) is a story that goes beyond the traditional formula—something that digs deeper and takes a fresh approach.

So I’ve got superheroes on the brain today. But the superhero topic I’m thinking about goes beyond the traditional approaches. I’ve got my own “superhero” screenplay for the EDA industry. As I see it, there is a villain right under our nose that needs defeating. It’s one that has the power to destroy life as we know it. That villain is the resistance to change and complacency. Continuing with our superhero thread, let’s call this foe Dr. Sameway.

Dr. Sameway would have you believe that you can build your next SoC the same way you did it before. Just use the same point tools with the same scripts. Maybe add another server or two, a few more engineers perhaps, and you’re good to go. Many of us see the folly in this. Not too long ago, Atrenta conducted a survey regarding the challenges of timing closure. That survey found that a majority of respondents reported they had trouble closing timing on their last design because of faulty timing constraints. What would they do differently next time? The majority answer was to try harder with the same tools. Dr. Sameway won that round.

The battle with Dr. Sameway rages a lot these days around IP re-use: 80% or more of your chip consists of third-party or legacy IP. Original circuit design is becoming a boutique art form. How is all this IP verified as complete, correct and compliant with the intended application? In most cases, the user tries it and sees what happens during synthesis, place and route. They “hope” for the best. Our sales VP always says that “hope is not a good strategy.” He’s right.

So how do we defeat the insidious evil of complacency? How do we finally neutralize Dr. Sameway? I firmly believe a new and fresh approach to design methodology is needed. An approach that is more evolutionary than revolutionary, but one that clearly puts more focus on the process of design much earlier than before. The concept of focusing more effort on “getting it right” earlier in the design process is not new. It’s been around for a while, but the complexity of current SoCs has now made it mandatory. There are many names for the idea. I like SoC Realization. To stay with our theme, let’s call this superhero The Realizer. Can The Realizer defeat Dr. Sameway? I think he must, or all of us are doomed to a life of missed deadlines, over budget projects and poor growth.

The concepts of SoC Realization have been well publicized. Google the term and have at it. Some companies have embraced the term (like us). Some are in denial. Others fear The Realizer because they believe he was invented by an evil empire. At the end of the day, it’s all hype. The realities of the marketplace will decide whether The Realizer will defeat Dr. Sameway. I’m not sure you will ever see this movie at the box office. If I had the budget, I would film it. But maybe our marketing dollars can be spent on other activities that will defeat Dr. Sameway. Stay tuned, we’ll see. And enjoy all those summer blockbuster movies while you’re at it.

–-Mike Gianfagna is vice president of marketing at Atrenta

By Mike Gianfagna
The Design Automation Conference is almost here. That major focal point for the EDA industry where we gather to explain the present, predict the future, have a bunch of serious meetings and maybe a little fun, too.

Some companies will stage an incremental update of their strategy and others will outline a major new strategy. This year, Atrenta will be talking strategy, with some announcements and a whole lot of demos to back it up. We’ll talk at length about SoC Realization—the part of the SoC design process that sits between system level design and silicon implementation. Pictorially speaking:

We’ll also have a little fun. For the first time, we have a trailer for DAC and a spokesperson, of sorts. If you have a little over a minute, check out this video.

I digress, this is starting to sound like a sales pitch and that’s not the point. The diagram, above, borrows a market segmentation that was originally proposed by Cadence a little over a year ago in their white paper entitled “EDA360, the Way Forward for Electronic Design.” One can certainly debate some of the concepts in that white paper, but the basic premise that SoC design is composed of a system design component, a silicon implementation component, and a piece in the middle that ties the two together does make a lot of sense.

Silicon realization is what pays the bills at most EDA suppliers today. That’s where the heavy lifting of synthesis, place & route, extraction, verification and tapeout occurs. It’s also an area that has become highly competitive and which is seeing some consolidation. We’ve all heard the refrain – chip complexity is going up and tapeouts are going down, as are the number of foundries in the world. Does this mean that someday there will only be a few monster chips being built by a few foundries? That’s quite unlikely. The market will find a way to differentiate.

Re-use will help, especially as we move from IP re-use to subsystem re-use. New technology advances like 3D stacked die will also help. The complexity of these new SoCs, or whatever we will call them, will demand design at a higher level of abstraction. It will simply be too hard to design any other way. So, the regimes of system realization and SoC realization will become the new battleground where end users compete for the next big thing.

But what about the foundation of EDA—what about silicon realization? Let’s start with an observation. Silicon realization flows are becoming more tuned to the target process. That tuning involves implementation flows that are lithography- and variability-aware, among other things. So the question is this: If there are to be only five (or fewer) foundries in the world, why don’t they each just buy a silicon realization flow and take it in-house? That will result in a well-calibrated, predictable and robust path to silicon. In that world, old EDA becomes part of the manufacturing process, and new EDA becomes, well, something else. It’s time for a new name.

–Mike Gianfagna is vice president of marketing at Atrenta.

By Mike Gianfagna
I lost a long-time friend this past week. He was a member of the EDA community and so I will dedicate this blog to a discussion of the late Dr. Aaron Ashkinazy—the person, his contributions and the process for his work.

The person. Aaron had a lot of friends. We’ve all been reminiscing about him this past week and some consistent comments arise. He was one of the most intelligent and kindest people we knew, someone who would never speak ill of anyone and as far as any of us can recall someone who never lost his temper. His calm and gentle rendering of significant insights will be sorely missed.

The contribution. I first met Aaron when I joined the Design Automation department of RCA Solid State in the late 1970’s. Recall those were the days before an EDA industry, so you wrote your own tools or you didn’t have any. Aaron was working with a fellow named Henry Hellman on the design of a new logic simulator. That software was ultimately called MIMIC, and Aaron was referred to by most as the Father of MIMIC. That name, MIMIC, has a colorful history all its own. There were many proposed names before we settled on MIMIC (Module Imitating Modern Integrated Circuits). My memory is too weak to remember all of them, but I do remember the first—JERKS (Jewish Engineers Release Kosher Simulator)—and the last, FINALE (Final Idiotic Naming of Advanced Logic Emulator). MIMIC became one of the fundamental design tools for all digital ICs at RCA.
It performed multi-level logic and concurrent fault simulation, and supported Verilog, VHDL and a few other esoteric languages of the day. There were many documented cases where the Verilog simulator would provide the wrong result and MIMIC would provide the correct result, but that’s a discussion best kept for another day. Aaron continued to develop complex scientific software across many domains until his passing.

The process. A multi-level logic and concurrent fault simulator used on all digital IC designs at RCA was a fairly significant achievement. What is interesting is that this incredibly complex piece of software was architected, written, tested, documented and supported by four people. When RCA entered the merchant application-specific integrated circuit (ASIC) market in 1981, the user base for MIMIC grew across the world. Not counting field AEs, the support staff for MIMIC then grew to about six, and there were a lot more libraries to support, as well.

As I think back to those days of internally developed EDA, there are many stories like this. Small teams who worked incredibly well together building substantially complex pieces of software that were used on a worldwide basis by internal and external (ASIC) customers. Today, I have a lot of friends who run engineering groups at EDA companies, both small and large. Most of them are never home. They always seem to be traveling all over the world to visit development teams that work for them. They struggle to keep everyone in sync and spend a lot time trying to manage everyone to a consistent level of quality. We all deal with these issues. Most companies have a global workforce.

This past week I’ve thought about the early days when I first met Aaron, when everyone worked in the same room more or less. Was that a better way to do things, or is my memory coloring the past in a favorable light? I’m not sure, but I do believe this: If the sophisticated networking and collaboration tools we all use could foster small, high-performance teams, that would be a good thing. I’m fairly sure Father MIMIC would agree.

By Ron Craig
Here in the United States it’s tax time again. Along with every other loyal taxpayer, I’ve been working on identifying every conceivable deduction I can think of to minimize my overall tax burden. I’m not an expert on tax law, but as far as I can tell I still can’t take advantage of the non-tax deductible dependents we like to call ‘the cats.’

Our own demanding house guests survive on roughly 20 hours sleep per day, and spend the rest of their time either engaged in random acts of madness or consuming food that appears to cost more per ounce than my car. That being said, I do have to hand it to them. They are the masters of stress-avoidance. Granted, they haven’t exactly amassed any possessions during their short lives, and they’ve hardly ventured more than 10 yards from the front door, but as I hack my way through my ‘to do’ list I can’t help feeling that it wouldn’t be so bad to swap roles with them for a day.

Fig. 1: Cat

I attended an interesting panel session at DesignCon recently that touched on how project teams tend to take the opposite approach to ‘the cats,’ amplifying rather than avoiding stress. A myriad of issues can delay tapeout, and the panel discussed the measures they have taken (or would like to take) to avoid these issues. What it often came down to in the end was that there are always better ways of doing things, but barriers to better methodologies persist. Design teams continue to struggle with inconsistent use of design tools across their organizations, for example, which make handoffs and co-operation more difficult. It’s hard to focus on these methodology issues when faced with the relentless search for ‘best in class’ tools, however. For their part, EDA vendors often make the problem worse due to their inconsistent and incomplete adoption of standards—often seeking to exploit a standard as a competitive advantage rather than a means of growing the overall pie.

One of the more compelling questions asked by the panel moderator (Ed Sperling of System-Level Design) was if it was possible to further shrink project schedules. One panelist noted how his most recent project was three months ‘from concept to tapeout,’ which is an incredibly short time. He further pointed out that such an aggressive schedule could only be achieved through extensive IP re-use. And it’s not just the IP itself. What about the ancillary data such as timing constraints, verification environments, etc.? Timing constraints were acknowledged to be a particular burden, especially because bad ones cannot only slow tapeout but hide issues until they pop up in the field. There are a lot of issues to balance, but at least one company is proving it can be done.

The good news is that these issues (to quote a former government figure) are ‘known unknowns’ rather than ‘unknown unknowns’ and a variety of creative solutions are regularly being put in place across the industry to mitigate them. Chip failures may be something that we continue to worry about, but at least we’re becoming better at stress-avoidance.

–-Ron Craig is senior marketing manager at Atrenta.

By Bernard Murphy
CES 2010 was quite a party, coming off the misery of 2008-2009. Tablets were everywhere, smart phones are racing ahead, the PC is dead. Our industry is reinventing the electronic experience yet again. I saw one forecast of a $1 trillion consumer electronics market within a few years. This is heady stuff. It restores hope not only in the future of electronics but also the possibility that electronics growth may help to power the global economy back to solid growth. It makes you proud to be an engineer (with perhaps a little queasiness over accelerating an electronically connected and personally disconnected society).

And yet… This is not easy money. Consumers are fickle, they have a finely tuned sense of value, and everyone with a stake in electronic products wants a piece of their wallet. Products must be feature-rich, adaptable to a wide range of markets and quickly re-spun to add more features or different form factors. If you think these devices already have all the features they need, think about Google “near-field communications” or “energy harvesting.” This is not a market for long-term enterprise/catalog product teams. This is pure survival of the fittest, and fit means fast and adaptable. Check out this article if you want more Darwinian analogies.

This consumer market is not just another turn of the screw on “chips are getting bigger, time to market is shrinking.” This is qualitatively different. The size of the prize and the level of competition dictate we will be paid only for features. The premium for development, and time to market for a new feature introduction (especially if you are not first to market with that feature), can be six months or less. In this new reality it is essential to drive cost and risk out of product development. Handcrafted, integration-focused register transfer level (RTL) design commands no differentiated value and increases cost, risk and delay. High-level synthesis has its place at the block/algorithm level but is not the solution to the integration problem. Think Dell—fast feature assembly needs pre-defined, well-characterized reusable blocks assembled as automatically as possible with robust hookup checks to reduce (not eliminate) debug cycles in verification.

Several thought leaders—including Texas Instruments and STMicroelectronics among IDMs, and Samsung and Canon among system OEMs—already have re-engineered their design processes around exactly this approach. They have organizations that produce, maintain and qualify IP (and inspect incoming IP), platforms on which they can quickly spin variants and automated assembly tools and dedicated integration teams to reduce cycle time to handoff RTL. But this is not a game only for the rich or for major corporate initiatives. Small companies and teams are achieving the same level of productivity using the same methods, scaled down. All it takes is a willingness to set the process and tools in place, to forgo tweaking (starting from someone else’s RTL, and tweaking is not re-use) and to accept that it’s now all about execution in delivering platform variants.

The party was fun and the opportunity is tremendously exciting, but it’s only for those who are ready to change their game.

–Dr. Bernard Murphy is chief technology officer at Atrenta.