By Ed Sperling

Daniel Nenni runs down a list of six reasons why he doesn’t think Samsung will succeed in the foundry business. You remember Samsung—one of the big three in the Common Platform world, along with IBM and the foundry formerly known as Chartered Semiconductor (now GlobalFoundries). Does that mean the company’s foundry business is in trouble? Maybe not, but it’s an interesting discussion.

Mentor’s Dennis Brophy writes that the IEEE is hosting some outreach sessions in Bangalore starting this week. If there was ever a clear indication that hardware development is strong in India, this is it. This should be interesting news in China. Break out the Windex.

Cadence’s Jack Erickson wants to know when the design world will move from RTL to TLM and what that means for job security—including his own. Is there a future for RTL engineers? You bet.

For anyone who had doubts about emulation, Mentor’s Ralph Zak has found a new use for it: simulation acceleration. Anything that can reduce verification time is worth some attention.

Si2’s Steve Schulz digs down further into product development kits and the role of standards in maintaining interoperability in part two of his epic. Move over Edward Gibbon.

John Aynsley, CTO of Doulos, looks at the integration of TLM 2.0 into VMM 1.2. He pays special attention to analysis ports, which can be used to distribute transactions to passive components during verification.

Team Specman notes, as well, that Specman will now support ARM’s Amba 4 protocol. This is good news for the ARM-centric world, but the bus structure may have limited uses going forward—particularly at advanced geometries and in vertical stacking.

SLD: The EDA industry often gets the blame for lack of progress in semiconductor design. Why?
Domic: Sometimes the EDA industry gets criticized that we haven’t invested in systems—whatever that means at a certain level. Part of the issue is the wide spectrum of the problem and the lack of definition. We can get you a tool to get from ‘D’ to ‘G’ in a certain sequence.
Leef: And combined with that are poor economics. People interested in solving the system-design problem at the front end are not very numerous. When I used to run the internal EDA organization inside Silicon Graphics we had a guy who was the architect of the graphics pipeline. He had all sorts of fascinating problems and all kinds of things he wanted to model—but he was only one. If a commercial EDA vendor could satisfy him they would sell one copy of the product and charge $1 million for it. The areas with the problems also have poor economics.

SLD: With modeling environments like TLM 2.0, hardware-software co-verification and high-level synthesis, there are a whole bunch of new areas that are not well defined or included in the flow. How do you deal with this?
Leef: There is a dimension of co-verification that has been well understood, which is at the RTL level where you have your design in RTL and you introduce a processor that is expected to run embedded software. The co-verification problem is essentially solved. You have a transmission mechanism that allows the software to be simulated very rapidly with hardware that is not all relevant, and the transmission slows down when you want to observe the bus cycles. At that level of abstraction, this has been solved. But at the higher level of abstraction what we’re running into is a lack of commonly accepted practices as to how people model systems like that. There are numerous examples where people decide to create abstract models that go really fast, and at the end of the day these models are rejected because they do not have enough details to be useful. And once they have enough details to be useful they lose the speed.
Kaul: Most of EDA is not market-sector dependent. RTL-to-GDSII uses the same synthesis tools and place-and-route tools. But when you get to system-level design, people designing cars have very different needs from the people designing airplanes, who have very different needs from the people designing DSPs. The models are key to that. The amount of detail needed on the models varies based on the kind of analysis you want to make. That’s one of the reasons why the market requires very deep domain problem about what the end customer is doing. For most of EDA, you need to understand semiconductor design. But with system-level design you also need a deep understanding of the end market. It’s hard to build, and especially to build it in a cost-effective way.
Leef: If you look at Bosch in the automotive sector, they really do need to model the hardware. However, once they deliver their solution to BMW, then BMW no longer cares what’s inside the electronic control unit. They care about the software and the network. They assume the electronic control unit and all the underlying hardware works correctly. Even though they characterize the problem as system simulation or co-verification, what they’re trying to analyze is drastically different from what Freescale or Infineon are trying to analyze before they gave it to Bosch.
Domic: The problem there becomes how many. In general, the EDA industry is investing much more. EDA has had emulation for quite awhile. We offer boards based on FPGAs where you can map and do some of the software verification. The reason a larger investment is going into these areas is the need for models. It may be hard to create a model for BMW when all they care about is the connection with the outside world. But when a platform gets standardized like a TI OMAP, where you have a couple of ARM cores and DSPs, you can’t provide a virtual platform. The problem has to be bound and specified.
Leef: The back-end part is relatively predictable. At the end of the day you’re going to build silicon. But the front-end part is more and more application-specific. IBM uses similar language to what we use, but once you dig into what they’re trying to accomplish it’s quite different. For example, they were talking about doing simulation at the car level and they were talking about simulating a network that contains 80 computers with sensors and actuators, gigabytes of software, all united by different types of networks. You’re not trying to verify the correctness of a Freescale semiconductor that lives on the ABS (antilock braking system). You’re trying to figure out when a customer presses the brakes, what are the external things that can be tolerated. That involves simulation of traffic on the network, mechanical modeling of the brake system.

SLD: Is this even an EDA problem?
Busco: And how have companies solved this in the past? Is it through in-house modeling? Or have they not even used automation?
Leef: The degree of design automation declines as you move further from tier-two suppliers. The silicon providers in this case—Infineon, Freescale, Renesas—are no different than TI and Intel in terms of the problems they’re trying to solve. When you go to Bosch and Delphi, they start to look more like PCB players. And then you go to the next set of players, they’re airframe designers. It’s a system of systems. The people who run those companies come from either a mechanical background or a financial background. They don’t have a direct appreciation of design automation. They wouldn’t think twice about spending $300 million to $400 million on prototypes, but they would argue over a $5,000 or $50,000 piece of software forever.
Kaul: People in those areas would use C models or The Mathworks.
Leef: The degree of automation in automotive is variable. One company has been trying to use MatLab Simulink, which only allows them to look at one dimension.
Domic: Given this lack of uniformity, and everyone trying to build something ad hoc, people try to answer very specific and narrow questions. Does the ABS react and work with the steering system? It’s a very specific question. You’re not trying to create a model that describes everything that happens to the car because that’s impossible with the current technology. On the other hand, when you do RTL for a chip you have an expectation it is an incredibly complete description of what a chip does. We have no tools that would synthesize a transaction-level model into a C model down to RTL. One part of the problem is that when you build a model you are trying to answer a very specific question.
Leef: The problems you’re describing are deterministic. In distributed systems, determinism is lacking. The problem they’re trying to find as the customer presses the brakes is why the signal doesn’t get to the brakes. It’s because the network is jammed with the temperature reading from the rear seat. The traffic on the bus is something that is irrelevant.
Kaul: These are very domain-specific and very hard to make a commercial business out of. That’s why customers end up doing a lot of this on their own.
Busco: To take a baby step of synthesis and try to raise the abstraction of that hasn’t been more accepted in the design community. Everyone does RTL synthesis. There are so many different domain languages, whether it’s C or SystemC or something based on MatLab, and yet designers are very hesitant to let go of the control and the quality of results they get from RTL.
Leef: The hardware guys are really married to this idea of precision and concurrency and timing being embedded into the language and the software guys see it differently.

SLD: Is it becoming a choice? You’re no longer designing the RTL. You’ve got power issues, software and signal integrity issues. Can you ignore these new techniques and still progress with a chip?
Kaul: Why haven’t people moved higher? Because getting from RTL to silicon is still such a problem. People need to have the level of control they get from RTL, and they need the visibility downstream to be able to design those chips.
Domic: The tools have progressed in terms of taking care of these things. But 20 years ago, if you look at RTL description languages, Intel had its own language, IBM had its own, and Digital [Equipment Corp.] had its own. VHDL took over. There are a myriad of descriptions above RTL.
Leef: But they don’t have a link to implementation.
Domic: I don’t think that’s a problem, because RTL methodology in large companies took over before synthesis was a viable alternative. Intel was using IHDL in the mid-1980s. I don’t think the key issue is a lack of a path to synthesis. But we have not done a good job in telling developers that C may not be perfect, but it’s more than enough to make good progress. Verilog may not be perfect, but for a lot of people it solved 90% of their problems.

System Verilog appears heading for some serious overhauling. Mentor’s Dave Rich says there were 472 updates to the latest Language Reference Manual, along with 986 open issues.

Along the same lines, there’s another interesting note about extensions to the language at the tail end of a blog on the Synopsys site by Vishal Namshiker of Brocade and Srinivasan Venkataramanan from CVC Pvt. Ltd.

So what does this all mean to verification engineers? A panel at DVCon, as reported by Cadence’s Richard Goering, focused on things that keep verification engineers awake at night. In our humble opinion it’s better to be sleepless and think about  solutions than to wake up screaming. What would the neighbors think?

Mentor’s Jon McDonald addresses irrational expectations vs. reality in high-level design. The bottom line is garbage in yields garbage out. That may be the most important equation to ever hit the ESL world.

Si2’s Steve Schulz looks into process design kit standards and why they’re so important—and why PDK standards are so hard to create.

Tets Maniwa drills into the annual EDA Consortium’s CEO forecast panel on Gabe Moretti’s Gabe on EDA site. It’s a good representation of the view from the top.

What exactly is real time? It depends upon where you go for the definition. As Mentor’s Colin Walls points out, the answer isn’t as obvious as it sounds.

Harry Gries has a photo that should not be missed, and his blog is certainly worth reading, too. It’s about radically rethinking projects. That’s been a common theme lately on all sides of chip design.

Mentor’s Steve Collis brings up an interesting analogy. If it’s easier to consume less food than to work it off at the gym, then shouldn’t the same apply to consumer electronics? This could be a literal interpretation of food for thought.

Daniel Nenni jumps into the comparisons between the major foundries—TSMC, GlobalFoundries and IBM. There’s a particularly interesting note in there about 40nm tapeouts. More than 60 customers have taped out chips at that process node at TSMC. There’s also some interesting information about interconnects, insulation and changing the resistance of copper.

Mentor’s Thomas Bollaert looks at a post from Synopsys’ Frank Schirrmeister and says it will be quite some time before chips are an assemblage of IP blocks. Sounds like a challenge. Pistols at dawn?

Mentor Graphics introduced a tool for thermal characterization for semiconductor packaging and design, which has become essential as density on an SoC continues to grow, along with both active and static power leakage. The new FloTHERM IC solution is a Web-based platform that simplifies many of the characterization and validation tasks.

Rumors of Magma’s death appear to have been overstated. The company generated revenues of $31 million for its fiscal Q3, ended Jan. 31. It had a net loss of $2.6 million, but when you compare that to a net loss of $78 million in the previous year—not to mention that the company beat expectations—things are definitely on the upswing. Revenue is expected to be relatively flat over the next quarter. Like many EDA companies these days, proof of success will be the bottom line, not the top line. Magma says it has positive cash flow.

Intel Capital and a group of 24 VC firms pledged to invest $3.5 billion in U.S.-based technology companies over the next two years. Intel’s share will be $200 million. In addition, a group of 17 technology companies ranging from Intel to EMC, Cisco, Marvell and Broadcom said they will increase their hiring of college graduates—some by doubling their hiring over previous years—to sustain the market for future scientists and engineers. This is very good news.

IBM put a green spotlight on the lithography process, creating fluorine-free photo-acid generator compounds that are used to transfer patterns onto wafers. Green is good, and in IBM’s case it’s also the green that comes from licensing patents.

TSMC is collaborating with Dialog Semiconductor on a bipolar-CMOS-DMOS technology that can improve power management in chips for portable devices. Dialog, in case the name doesn’t ring a bell, is based in Stuttgart, Germany.

GlobalFoundries Singapore—the company previously known as Chartered Semiconductor—announced a tender offer for any and all of its senior notes due in 2010. Consider this yet another step in a complete takeover of this foundry by ATIC, the Abu Dhabi-based investment powerhouse.

Advances in silicon technology have enabled unprecedented levels of integration in today’s SoC designs. These designs are developed through integration of various sub-systems. After the architecture and top-level micro-architecture are reasonably complete, the task of developing and integrating sub-systems begins. These sub-systems may be developed ground-up with brand new sub-system RTL. Additionally, many of the sub-systems can be sourced as IP from third parties or from an internal library of legacy designs. Integration of these sub-systems begins at appropriate times in the workflow.

This white paper describes typical issues faced by designers in these three fields. The paper highlights the need to address implementation issues for the chip project early in the design cycle. The paper then reviews current “rule-checking” approaches and gives an overview of the Atrenta approach to the problem. To download the paper, click here.

A recent report by the Global Industry Analysts, based on information from EDA Consortium (EDAC), predicts that the global EDA tool market eventually will re-emerge to drive growth to $9.8 Billion by 2015. The report suggests that this growth will be fueled in part by the traditional efforts to improve efficiency and performance throughout the chip development process.

EDA Chip-Level Tools
Aart de Geus, chairman and CEO of Synopsys, expanded upon this finding in a recent interview. “As a percentage of our business, classic EDA is shrinking, but this is not a case of ‘classic EDA doesn’t grow.’” For example, in the past, EDA companies added front-end RTL synthesis and design tools with timing and power closure to improve the productivity of chip designers. Next, efficiencies were found in the back-end of the process by adding physical design with extraction and Design for Manufacturing (DFM) and Yield (DFY) tools. Today, EDA vendors are improving the value of system-level design with architectural tools.

Synopsys is indeed attempting to improve their architecture tool flow with the recent double acquisitions of two electronic-system level (ESL) design companies – VaST and CoWare. The emphasis on architectural integrated circuit (IC) design productivity has pushed traditional EDA chip companies to expand into the next level of product development, namely, package and board design and – on the software side – even application development.

But this time around, productivity and efficiency within the chip development process will not be enough to save EDA. In addition to continuing improvements in both front and back-end tool design, chip-level EDA companies must be successful in reaching outward to embrace new customers and industries.

Perhaps no one understands this shift in thinking better than Mentor Graphics, who has products in the chip, package, board and even embedded real-time operating system (RTOS) markets. “We (EDA chip tools) as an industry are stubbornly targeting a limited number of customers,” said Serge Leef, vice president of new ventures and General Manager of the System-Level Engineering Division at Mentor Graphics. “We really need to figure out where to go beyond that.”

There are four choices, according to Leef. One is to sell products to existing customers, which EDA companies will continue to do. The second is to sell new products to existing customers, which they are attempting in areas such as submicron design, DFM and yield enhancement. A third option is to sell existing products to new customers in places like China and India, but most of those companies are either part of multinational companies that already buy EDA tools or they’re underfunded startups that cannot afford tools. A fourth option is to sell new products to new customers.

On paper, the last option seems the most promising. The problem is getting the new customers to look at what EDA has to offer, which means that EDA companies must understand the needs of the new customers – i.e., different industries.

IP Drives Profit
A universal need shared by most new customers in today’s economically challenged markets is that of cost reduction. This has two effects. One is to increase the use of intellectual property (IP) blocks in chip-level design while the other is to move from ASIC to FPGA-based designs.

Increasing the use of IP was a primary theme in Virage Logic’s keynote address at the recent DesignCon show. That was expected, but the arguments that were used to support the growth of IP are worth noting. Brani Buric, executive vice president for marketing and sales at Virage, explained it this way: “As we move into consumer markets with low profit margins we must think beyond the technical challenges to the business issues. The question is not just how to do the design more efficiently in terms of cost, but whether to do the design at all.”

The business focus of this approach is reflected in its name, i.e., Design for Profitability (DFP). Companies focusing on profit might just write the spec for a new chip, then hand off the rest of the design and implementation to design companies such as eSilicon or Open-Silicon. Owning the spec would typically be a lot less expensive than owning any part of the implementation process. This approach relies heavily on IP blocks to build the chip to spec.

Interestingly, the growth of IP is one of the key drivers cited by in the Global Industry Analysts report for overall EDA growth. The reason that EDA tool revenues are expected to climb in 2015 is because EDA owns IP. By including Broadcom, Qualcomm and ARM as some of the largest IP licensing companies, EDA will indeed be one of the fastest growing sectors—at least on paper. The reasoning for this inclusion, according to EDAC, is that EDA tools are an integral part of licensing the IP, so IP licensing revenues should be counted in the EDA business calculations.

EDA in the Board-Level Market
The growing reliance on FPGA-based electronics is the second trend driven by profit-focused designs. But this is another area where companies like Actel, Xilinx and Altium are trying to engage a broader customer base, e.g., medical, industrial and automotive markets.

Actel’s purchase of Pigeon Point moves that company squarely into the Advanced TCA and MicroTCA world, which has been heavily utilized by communications companies and defense. Xilinx, meanwhile, is positioning its next-generation 28nm FPGA platform to help win business in non-traditional markets. And Altium has been focusing on a single database implementation of FPGA-based, board-level products that include embedded software development.

While all of these expansions reflect broader changes in the overall semiconductor industry, real growth in the EDA sector can only come from expansion beyond traditional markets. But there will always be a nagging question facing EDA companies moving into these new markets: Is this really EDA, or are we venturing into a new sector that reaches well beyond the confines of EDA to include a true system-level approach?

Integration of third-party intellectual property (IP) into integrated circuit (IC) designs has always been a potential time trap for IC designers. IP design rule violations that were waived by the foundry show up during IC verification without any indication as to their waived status. The IC designer has no choice but to analyze and resolve these errors just like any other, wasting significant manhours and cycle time.

Calibre Auto-Waiver, Calibre nmDRC’s automated waiver management capability, provides IP designers with automated identification of design rule violations granted waiver status during IP development. During integration of the IP into larger designs, IC designers can use Calibre Auto- Waiver to recognize and remove these errors during design rule checking (DRC), avoiding the need to analyze and debug waived errors. In addition, Calibre Auto-Waiver identifies any waived errors that fall into “marginal” waiver status, allowing the IC designer to investigate these errors as needed to ensure manufacturability. After DRC is complete, Calibre Auto-Waiver enables the designer to quickly review the waiver status of all IP errors, as final assurance that no IP error has been overlooked.

This paper explains the Calibre Auto-Waiver product, and discusses how the auto-waiver process significantly reduces the time and risks associated with implementing third-party IP. To download this paper, click here.

In the last few years, the trend in CPU performance improvement has shifted from raw computational speed to parallelism as various memory and power (heat dissipation) limits have been reached at the higher clock frequencies. After surpassing clock speeds of 3 GHz, further CPU performance improvement is now achieved by increasing the number of computational elements (cores) within a given CPU package. This means that in order for software applications to run faster on the latest machines, they need to take advantage of the new multicore architecture.

This becomes especially important for electronic design automation (EDA) applications. With growing design size and complexity, continued EDA tool performance improvements are necessary to help design teams meet their schedules. However, given the intricacy of EDA tools, many factors need to be taken into account when implementing multicore analysis hardware support to ensure fast turnaround time and optimal use of compute resources. In this paper, we discuss the evolution of multicore analysis computer hardware; the various approaches to implement multicore analysis support, specifically for static timing analysis tools, such as PrimeTime; and how to optimize hardware and software settings to improve turnaround time. To download this paper, click here.

By Ann Steffora Mutschler

The age-old question of whether to make or buy is time immemorial, and is particularly true for the cyclical semiconductor industry. At the end of the day, the answer comes down to how the decision maker feels about having or losing control.

Fifteen years ago, whether to make or buy something—be it the design, libraries, memory, implementation, verification, testing, mask set, even manufacturing—was not relevant because an alternative didn’t exist. All semiconductor companies were integrated device manufacturers (IDMs) and did everything from concept to finished product as their title implies. Chips were created by a company for their own purpose: to be put it into a system and sold in a box, whether that was a PC or a mainframe. Think IBM or Digital Equipment Corp. (DEC).

As Moore’s Law allowed for the increase of chip complexity, combined with demand for new and different products, along with other market dynamics, the fabless semiconductor industry was born. Until the mid-’90s, the majority of chips manufactured were used in data processing and computing applications. Then came the explosion in consumer-demand for technology, spawning new and varied semiconductor and systems companies to meet the needs of markets.

These changes drove the disaggregation of the IDMs and served as the genesis of the standalone EDA, capital equipment, tester, packaging, and foundry industries.

As time has moved forward, with leading-edge process technology at 40nm, it now makes increasing sense in many cases to buy some of the individual pieces in a chip. And for many companies, it is not enough to simply purchase individual pieces. They now want a third party to pull everything together. It all comes down to the numbers, said Kalar Rajendiran, senior director of marketing at eSilicon.

“In 2004, when 0.13 micron was the leading edge, a mask set probably cost $300,000. Today, the bleeding edge is 40nm and a mask set is about $1.5 million, depending on the number of layers. That is a five-fold increase in the mask set cost over five years. Leaving out really large semiconductor companies like nVidia, Broadcom, and others, who are in the billions of revenue, there are lots and lots of companies that are in the $100 million dollars or less range,” he said. “These companies have good products, but in terms of the investments they need to make in order to get a product out it could easily be $30 to $40 million to completely produce a chip from the idea all the way to fully qualified product.”

Most semiconductor companies don’t have that kind of funding in big pieces. Even in the heyday of VC funding, a semiconductor company would never get $30 million or $40 million in one chunk. “When you are doled out a few million here and there, you can’t really use that to build an entire team,” he added.

The past five years have seen complexity and costs increase so much that if you look at it just from the cost side, it is impossible for all but the largest IDMs to go it alone. That leaves the majority of semiconductor players weighing the pros and cons of outsourcing.

Brani Buric, executive vice president of marketing and sales at Virage Logic, observed that for customers the ‘make vs. buy’ decision can be broken into three categories.

First, more noticeably today than five years ago, is whether the company going to do design in-house or buy complete design services. “Five years ago I would say that the whole COTS business as a part of the fabless process was at a high,” Buric said. “What has happened in the meantime, especially as we are moving to new processes, the cost of development has become very, very high. That includes having an engineering team, having folks in-house developing IP, doing test chips, test process, paying for mask sets—every single component is going up. So the first ‘make vs. buy’ decision occurs once somebody has a spec. Do they need to do design in-house or they can find somebody who is in business of doing designs and get the design done or even get silicon back?”

Buric believes this is the driving force behind companies such as Global Unichip, eSilicon, Open-Silicon and VeriSilicon. Even traditional ASIC companies such as Texas Instruments, LSI Corp. and NEC have outsourced their manufacturing. “There is definitely a new trend where people have an idea, they have a spec, but they don’t need to implement the spec [themselves], and that is the first breaking-point decision in the ‘make vs. buy’ process that we didn’t see five years ago.

Second, if the customer believes they must do their design in-house, it would likely be in a case where they believed their spec had tremendous value that they didn’t want to share. Then, they would make the decision about what they had to build in-house vs. what they could buy or outsource.

In some cases, a company may do its own RTL design but outsource the physical implementation and the back-end implementation possibly to a company such as eSilicon or Open-Silicon. Connected to this is the choice of whether to completely own the design. The difference is basically long term and what they want to accomplish with the design. “If they believe that long-term they have a manufacturer that will give them good prices for silicon and they stay with a single source (which are typically designs that have high value beyond the cost of silicon), then they may stay with them and just say, ‘You own IP, I don’t care. My IP is in my specification,’” Buric noted.

However if the company is more price-sensitive, they may decide at the beginning to go with outsourcing and later on decide to move. For example, they may do the design and back end in-house because they are strong enough and don’t need external help. In that case, they would immediately become the owner of the IP rather than let their design services provider own the IP because that gives them independence in future decisions. That gives them the freedom to move from one foundry to another.

Third, for every single piece of IP that a company must use and decides to own, critical decision-making points concern whether that IP is available and if it is silicon-proven. “If it is available, is silicon proven and fits their needs, then in 99% of cases the decision will be to buy. If it is not silicon proven then they may think about making it. The only time when people don’t make the decision to buy is if there is no IP available or if there is no service company that has a proven track record of developing a specific IP,” Buric said.

Texas Instruments is intimately aware of the ‘make vs. buy’ decision, especially in regard to its manufacturing. Since November 2001, the company has gradually shifted all of its logic manufacturing to foundry partners – a big change for the chip giant, which at one time in its history was one of the world’s biggest IDMs, and owned everything from the wafers to the capital equipment.

However, the changes have allowed the company to remain nimble in the market. Tom Thorpe, vice president of external development and manufacturing at Texas Instruments explained, “One thing that we are really clear about at TI is that we want to maintain independence and be able to move loadings from one foundry to another based on quality, cost, delivery and service so that we can maximize our responsiveness to our customer base. The IP is a big part of that discussion because if you partner with a foundry and use IP that has been designed only for that foundry, or which that foundry has paid for, then you can’t take that IP somewhere else.”

Thorped noted that one of the key factors in TI’s decision-making process is figuring out how to maintain independence. “We’re outsourcing a whole lot of our production, especially on the leading edge, so we have to figure out how to maintain our independence. That means you have to either do the IP yourself or contract with some firm to do it for you. And we have to pay for it. Otherwise the foundry pays for it and it’s going to lock us in. Certainly you want to have components of the IP which are owned by your company.”

A major part of that decision is what makes one company’s product different from another’s, but that differentiation changes over time. “There is always something new that you want to keep internal in order to have a competitive advantage,” Thorpe said. “Over time, whatever it is that you were keeping to yourself becomes common enough that other people start to do it and then it is no longer a competitive advantage. When that happens you might as well buy it from some third party. It’s just a natural progression. There’s nothing we can do in this industry that people don’t know about over time.”