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Cost Reduction Is Real SLD Value

By Richard Goering
When Gary Smith gave his annual briefing on the Sunday before the 2010 Design Automation Conference, I was somewhat surprised that the topic wasn’t ESL. Gary’s talk was titled, “Don’t Panic! SoC Costs Will Come Down.” It took me a few minutes to realize that the talk really was about ESL, or system-level design – it was just presented in a somewhat different way.

While many arguments have been raised on behalf of system-level design, one that hasn’t been emphasized enough is SoC cost reduction. True, ESL techniques can speed development times for complex SoC hardware and software, but the real value lies in the ability to reduce overall SoC costs. SoC hardware and software development costs are threatening to top $100 million by 2011, according to the International Technology Roadmap for Semiconductors (ITRS), so reducing that cost has become critical for anyone who wants to make a profit with an advanced node SoC.

Gary identified virtual prototyping as the technology with the most promise for cutting SoC development costs. Software virtual prototypes allow early software development without the need to build anything, potentially saving months of development time, a savings that can be translated measurably into dollars. Moreover, virtual prototypes save money and time down the road by ferreting out hardware/software interaction problems early.

What about unit costs related to packaging, manufacturing, and test? With a limited amount of information about a new design, some initial IP selections, and some knowledge of the process, it’s possible to get useful estimates of power, performance, area, and cost itself. You can look at different architectures and packaging choices and see the impact on cost. Some people do this sort of thing with spreadsheets, but there are automated tools that make the task much easier.

High-level synthesis can potentially reduce both development costs and unit costs. Development costs are much lower because the design cycle is speeded up by months, and fewer engineers are generating much more value. Unit costs can be lower because you can experiment with different micro-architectures rapidly and see the impact on power, performance and area. You then can use this information to optimize for cost.

Of course, if the virtual prototype environment is tied to high-level synthesis, you’ll save even more money on development costs. If both the virtual prototype and the high-level synthesis tool accept the SystemC TLM standard, and models are synthesizable, the same models can be used in both environments.

I have heard it said that 70% of the potential power savings in a design occur at the system level. Could the same be true of potential cost savings? In any case, I think ESL providers and promoters should talk more about cost savings, and include some realistic examples and metrics to illustrate what’s possible. Can a system-level design approach reduce NRE SoC development costs by $5 million or $10 million or $25 million? Can it reduce unit costs by allowing, for example, a smart and early decision about packaging? Show specifically how and why, and there’s sure to be a lot of interest.

–Richard Goering is manager of technical communications at Cadence Design Systems, and author of the Cadence Industry Insights blog.

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