Where Open Source EDA Works – And Doesn’t
By Richard Goering
As the EDA editor for EE Times for many years, I developed an interest in open-source EDA software. I wrote about various projects and tools, and put together a directory of open-source EDA tools that ran on the EE Times Web site. Despite my interest, open-source EDA tools never gained much traction—certainly not like the embedded software development world, where open-source software and tools are the norm.
But that doesn’t mean open source doesn’t have a place in EDA. It’s just a different place, as I’ll suggest.
You can’t say open-source EDA tools have had zero impact. There are tools and projects that have been around for quite a while, including the Alliance VLSI CAD suite, the Icarus Verilog simulator, and the gEDA (GNU EDA) tools for circuit and board design. A quick Google check showed that these are still around. A recent search for “EDA” on Sourceforge.net turned up more than 50 entries, although some don’t really look like EDA to me.
Open-source EDA tools have found some use by students, hobbyists, and consultants, but are not generally used by large semiconductor and systems companies. However, several open-source EDA tools have led to greater things. The open-source Jeda language was the starting point for verification provider Jeda Technologies, and an open-source utility helped launch design data management provider IC Manage. The open-source Open SystemC Initiative (OSCI) SystemC simulator helped fuel the growth of SystemC.
So why hasn’t there been more open-source EDA software? Unlike the embedded world, where a GNU C compiler can serve many thousands of users, EDA consists of a number of specialized niches with small audiences. The tools are very sophisticated and need lots of support. Nobody wants to rewrite an open-source IC design tool while taping out a chip. To get into chip design, you have to be a fairly large company with deep pockets, so free tools may not be much of a draw.
But one place that open source EDA can work is standards. An example is the Accellera Universal Verification Methodology (UVM) 1.0 Early Adopter standard, and its Open Verification Methodology (OVM) predecessor, both available under an Apache 2.0 license. A rich community of users and contributors evolved around OVM, and the same will almost surely be true of UVM. As an example, Cadence contributed open-source libraries for e and SystemC to OVM, and contributed an open-source UVM reference flow to the UVMworld site.
Models present another opportunity for open source. A recent article in the SLD community, “Moving to Open-Source Software,” noted that EDA users don’t want to get into the insides of commercial simulators, but they do want control over models. Virtual platform provider Imperas has launched an open-source modeling effort through its Open Virtual Platforms (OVP) initiative. This initiative provides a simulator that’s free for non-commercial use, open-source peripheral and processor models under an Apache license, and open APIs. Users can build virtual platforms and develop software with these models.
Clearly there are some limitations. If you “extend” an open-source standard, your extensions are not standard until a standards organization says they are. If you go into a processor model and change some code, it might operate differently from what you expect. But it seems clear that open-source software does have a place within EDA. It’s just a matter of where you look.
–Richard Goering is manager of technical communications at Cadence Design Systems, and the author of the Cadence Industry Insights blog.
Tags: Cadence