Comments for It's The System http://chipdesignmag.com/sld/goering Deep Insights for Chip Architects and Engineers Thu, 24 Feb 2011 21:30:20 +0000 hourly 1 http://wordpress.org/?v=3.0.4 Comment on SLD Is About People, Too by Martin http://chipdesignmag.com/sld/goering/2011/02/24/sld-is-about-people-too/comment-page-1/#comment-263 Martin Thu, 24 Feb 2011 21:30:20 +0000 http://chipdesignmag.com/sld/goering/?p=56#comment-263 Hi Richard, Good observation on training and education. That's why we started the Academic Connection Program for SystemC-AMS this year, fully supported by Universities who teach EE and CS/ICT at the same time, including system-level AMS! More on: http://www.systemc-ams.org/ Regards, Martin Hi Richard,

Good observation on training and education. That’s why we started the Academic Connection Program for SystemC-AMS this year, fully supported by Universities who teach EE and CS/ICT at the same time, including system-level AMS! More on:
http://www.systemc-ams.org/

Regards,
Martin

]]> Comment on An Irreverent View Of “ESL” by Kevin Cameron http://chipdesignmag.com/sld/goering/2010/04/22/an-irreverant-view-of-%e2%80%9cesl%e2%80%9d/comment-page-1/#comment-7 Kevin Cameron Thu, 06 May 2010 16:19:49 +0000 http://chipdesignmag.com/sld/goering/?p=3#comment-7 Ken/Richard, I disagree that pure virtual signoff is not realistic. To some extent it is inevitable if chips keep getting bigger and re-use more IP, doing test spins (on all the IP) would be too expensive. I expect part of the shift to ESL will be a move to fault-tolerant (chip) design such that both design mistakes and the inability to get a 100% working die are less of a problem. "the accuracy that only emulation or FPGA prototypes can provide" is just digital function, it doesn't cover mixed-signal, power or thermal issues. To some extent I liken the current EDA tool flow to Microsoft Windows 9X which was built on top of DOS. We need to swap out some of the old tools for new ones that are designed specifically for sub 45nm Silicon. Ken/Richard, I disagree that pure virtual signoff is not realistic. To some extent it is inevitable if chips keep getting bigger and re-use more IP, doing test spins (on all the IP) would be too expensive.
I expect part of the shift to ESL will be a move to fault-tolerant (chip) design such that both design mistakes and the inability to get a 100% working die are less of a problem.

“the accuracy that only emulation or FPGA prototypes can provide” is just digital function, it doesn’t cover mixed-signal, power or thermal issues.

To some extent I liken the current EDA tool flow to Microsoft Windows 9X which was built on top of DOS. We need to swap out some of the old tools for new ones that are designed specifically for sub 45nm Silicon.

]]> Comment on An Irreverent View Of “ESL” by Richard Goering http://chipdesignmag.com/sld/goering/2010/04/22/an-irreverant-view-of-%e2%80%9cesl%e2%80%9d/comment-page-1/#comment-6 Richard Goering Fri, 30 Apr 2010 23:24:53 +0000 http://chipdesignmag.com/sld/goering/?p=3#comment-6 Ken -- I agree that pure virtual signoff is not realistic. At some point prototype hardware is needed. In the SoC design world, virtual prototypes are great, but design teams will still need the accuracy that only emulation or FPGA prototypes can provide. For that matter post-silicon debug will always be needed, but the hope is that the people who do it won't find anything significant. Ken — I agree that pure virtual signoff is not realistic. At some point prototype hardware is needed. In the SoC design world, virtual prototypes are great, but design teams will still need the accuracy that only emulation or FPGA prototypes can provide. For that matter post-silicon debug will always be needed, but the hope is that the people who do it won’t find anything significant.

]]> Comment on An Irreverent View Of “ESL” by Ken Karnofsky http://chipdesignmag.com/sld/goering/2010/04/22/an-irreverant-view-of-%e2%80%9cesl%e2%80%9d/comment-page-1/#comment-5 Ken Karnofsky Fri, 30 Apr 2010 19:34:58 +0000 http://chipdesignmag.com/sld/goering/?p=3#comment-5 Richard, I agree with your definition of “true System-Level Design (SLD)”, but the vision of complete virtual signoff is unlikely to be practical any time soon. In fact, automotive engineers have been pursuing this goal for some time. Many are using Model-Based Design to develop a variety of applications from powertrain to body controllers. On the path from no SLD to 100% signoff without physical prototypes, these engineers are using models to verify their designs before using hardware, but are not trying to replace the hardware entirely. The key is to model enough of the behavior to find most errors early and reduce testing costs. Given current technology, the cost of building a model that fully replicates all system behavior is prohibitive. Moreover, at some point you need a real prototype vehicle to drive in order to fully validate the design. Engineers today use multidomain simulations that enable different domain experts to build sub-system models and integrate them to verify system-level behavior. Automotive engineers have used Simulink, for example, to simulate the vehicle dynamics including analog, digital, software, mechanical, and hydraulic components to do early verification of their systems. That is, they develop and rigorously test powertrain, stability, braking, and other critical systems long before they build physical prototypes. Many automotive control systems have gone into production using this methodology because it dramatically reduces errors and consequently development costs. This multidomain capability gives engineers the flexibility to integrate sub-system models with different levels of abstraction into the same system model. This enables each sub-system designer to do detailed design exploration and verification while using an abstract model of the rest of the system as a test harness. One way to advance the movement of SoC-centric ESL toward SLD is to integrate it with Model-Based Design so that system and hardware engineers can work more effectively together. - Ken Karnofsky MathWorks Richard,

I agree with your definition of “true System-Level Design (SLD)”, but the vision of complete virtual signoff is unlikely to be practical any time soon.

In fact, automotive engineers have been pursuing this goal for some time. Many are using Model-Based Design to develop a variety of applications from powertrain to body controllers. On the path from no SLD to 100% signoff without physical prototypes, these engineers are using models to verify their designs before using hardware, but are not trying to replace the hardware entirely. The key is to model enough of the behavior to find most errors early and reduce testing costs.
Given current technology, the cost of building a model that fully replicates all system behavior is prohibitive. Moreover, at some point you need a real prototype vehicle to drive in order to fully validate the design.

Engineers today use multidomain simulations that enable different domain experts to build sub-system models and integrate them to verify system-level behavior. Automotive engineers have used Simulink, for example, to simulate the vehicle dynamics including analog, digital, software, mechanical, and hydraulic components to do early verification of their systems. That is, they develop and rigorously test powertrain, stability, braking, and other critical systems long before they build physical prototypes. Many automotive control systems have gone into production using this methodology because it dramatically reduces errors and consequently development costs.

This multidomain capability gives engineers the flexibility to integrate sub-system models with different levels of abstraction into the same system model. This enables each sub-system designer to do detailed design exploration and verification while using an abstract model of the rest of the system as a test harness.

One way to advance the movement of SoC-centric ESL toward SLD is to integrate it with Model-Based Design so that system and hardware engineers can work more effectively together.

- Ken Karnofsky
MathWorks

]]> Comment on An Irreverent View Of “ESL” by Kevin Cameron http://chipdesignmag.com/sld/goering/2010/04/22/an-irreverant-view-of-%e2%80%9cesl%e2%80%9d/comment-page-1/#comment-4 Kevin Cameron Wed, 28 Apr 2010 03:05:02 +0000 http://chipdesignmag.com/sld/goering/?p=3#comment-4 Having worked on the Verilog-AMS and SystemVerilog committees, and worked with SystemC, I definitely agree there is some way to go to get to full SLD. I have had an interest in hardware/software trade-off as well as mixed signal design for many years, and motivated by the failure to shift SV into ESL space, I decided I could probably do something better myself. For ESL you want a programming language with hardware modeling capability, rather than an HDL, so I decided to go with C++ and add HDL style thread support. Analog/mixed-signal is in the design spec (but not on the web). You can find the code and some examples at - http://parallel.cc As a bonus you can just use it for programming your multicore hardware. Who's going to give me a lot of money? Having worked on the Verilog-AMS and SystemVerilog committees, and worked with SystemC, I definitely agree there is some way to go to get to full SLD. I have had an interest in hardware/software trade-off as well as mixed signal design for many years, and motivated by the failure to shift SV into ESL space, I decided I could probably do something better myself. For ESL you want a programming language with hardware modeling capability, rather than an HDL, so I decided to go with C++ and add HDL style thread support. Analog/mixed-signal is in the design spec (but not on the web).

You can find the code and some examples at – http://parallel.cc

As a bonus you can just use it for programming your multicore hardware.

Who’s going to give me a lot of money?

]]>