If we consider the structure of an ASIC from inside to out, then naturally the IP forms the seasoned stuffing. The ASIC die is therefore the chicken; the substrate becomes the duck; and finally the package ends up as the turkey. While in food terms the challenge of the turducken is in making sure it gets cooked the whole way through and to perfection, the challenge of the ASIC is making sure that everything comes together perfectly and works to spec. Checking that the strange beast of the turducken is cooked correctly and that the flavors blend together perfectly when eaten is similar to being able to test the ASIC to ensure performance to spec once it is integrated into the final product. I hadn’t thought much about the overall solution or covered them in previous blogs, but after being involved in a number of projects where test had come up many a time in discussions, the whole solution became something of interest in terms of how IP plays into it.

Even at the macro scale of the overall chip, the smallest ingredients matter to a large degree. IP becomes not only about the cost, size and performance of the individual blocks, but how they fit into the ASIC along with the other IP and how the overall device becomes testable in a way conceived by the designers from the project concept. DFT, or design for test, has become increasingly important as the internals of the design become more deeply embedded with, well, the internals of the design.

Being able to get to these parts and test them is something that needs to be considered from the concept and throughout the design right up to package level. Scan chains at the individual IP level can end up costly at the chip level in terms of how they fit in with the overall device testability. Longer time on the tester or having to use a more expensive tester can produce unforeseen costs. In many cases we end up having to rethink test plans and add to test costs due to the microeconomics of the design, much like the wrong stuffing in our turducken can cause a complete change in the end result.

Fortunately with current designs we are able to test much more of the design through scan chains, BIST and MBIST and by using tools such as Synopsys’ Tetramax or Mentor Graphic’s TestKompress. Close cooperation with IP vendors to understand the built-in test that they have included in their IP also helps ensure good fault coverage. With respect to memory testing, it has become much simpler recently and is now considered straightforward. But more complex IP, such as SerDes IP, is becoming increasingly complex in the test environment due to the need to test not only through loopback testing, but also to test functionality and to test that at speed. Functional testing of this IP requires more complex test structures with active components leading to more costly and complex test boards. To understand the economics, logic and functional requirements and options, the designer must work closely with not only the IP vendor but also with the end customer and have a good knowledge of tools and testers available to him, including their limitations.

So unlike the turducken where the chef keeps his fingers crossed in the hope that things turn out to plan and can only probe the temperature, the ability to test the complex ASIC begins from the concept stage and enables the design, manufacture and test of the end product to happen seamlessly. You might enjoy your turducken, but having your ASIC work first time is much more satisfying.

–Doug Ridge is strategic source manager at eSilicon.

There are at least two fundamentally different applications for 3D technology that are driven by completely different incentives. The mobile space is driven mostly by the need for reduced power, height and area. The infrastructure and networking space is driven by the need for yield improvement and the ability to insert more memory than is monolithically possible—at much lower power. Mobile devices need thin architectures and very thin packages. On the other hand, larger networking devices require thicker 3D ICs or interposers to handle the flatness needed for larger die and the side-by-side architectures of the devices.

These are really exciting times: 3D and 2.5D technology could change the entire landscape and architecture of ASICs. This already has started in FPGAs and ASSPs, but ASICs face a particular challenge. ASICs do not generally have the benefit of high volume required to secure sources, influence foundries, and gain early access to 3D technology—which they need if they want to be in a leadership role in this implementation.

The exponentially rising cost of tapeouts at lower nodes has resulted in fewer tapeouts at these emerging technologies. As a result there are fewer experts in this field. Some companies will be able to spend a lot of money developing the technology and hence developing the expertise in the field. The rest of us will have to rely on strategic partnerships to help and hand-hold as we cross the threshold into this technology.

Fig. 1: A basic 2.5D structure.

Foundries and assembly houses are keeping their 3D-IC cards close to vest and waiting for industry leadership to come from the users of 2.5D and 3D technology. Obviously, they do not want to spend all that money to find out later that they need to change course to follow the prevailing current.

eSilicon has spent a good amount of time and effort on 3D- and 2.5D-IC technology. We believe that ASICs will need what we are referring to as a menu for “tiles,” such as memories, microprocessor subsystems, integrated passive devices, FPGA die, and other devices. In that model tiles are proven building blocks. A 2.5D or 3D-IC implementation could include tiles in leading-edge technologies like 28nm, with a lower NRE thanks to a 65nm-based interposer. The proven tiles mean the design team doesn’t have to re-invent the wheel, saving time and reducing risk.

Fig. 2: An example of a 3D IC.

We—along with our partners—certainly want to take a leadership role in the 3D-IC space. At the same time, we need to understand where the prevailing currents are flowing. I do not think any of us will have all the answers, but ongoing conversations with partners and customers are getting us closer to understanding where the need is. Once you know where the need is, the direction will become abundantly clear.

–Javier DeLaCruz is eSilicon’s semiconductor packaging director.

The sad irony of the current situation that plagues America’s, perhaps, closest ally is that the last comparable Japanese experience was delivered to them by the very country that, today, is prepared to do most anything to assist them. We’ve all come a long way and it’s within that notion that we can find hope the world will rally to aid a nation that has contributed enormously to our high standard of living, and our appreciation for tradition in both work and friendship.

We wish our Japanese friends every good fortune to repair their country and move forward, once again.

I am told the two Japanese characters for the word crisis translate to chaos and opportunity. My guess is it is now in the Japanese tradition to move the discussion from crisis to opportunity; from tragedy to productivity. The world is watching an orderly, disciplined Japan rebuild capacities, craft new supply chains, re-qualify new sources for key raw materials… conserve, repair, improve, perfect; Japanese style.

eSilicon, like every other member of the semiconductor industry, has evaluated dependencies, availabilities and alternate plans to accommodate the needs of our customers. As a Value Chain Producer (VCP) we have published nearly daily reports to our customers, identified critical risks to their production, proposed alternative solutions to minimize those risks and, otherwise, tried to keep them informed as we untangle the web of impact from this natural, now commercial, disaster. I, for one, believe we will keep the chips flowing, manage some delays and keep the supply side under control.

I do worry about demand. I can easily imagine major Japanese industrial companies deciding to manage their G&A expense by not buying items, such as servers and routers, which in turn slows the demand for those system components…another off year for semis? We’ll see. The good news is that the total demand won’t go away. More likely, we’ll just see some delays.

So, here’s our counsel to our customers: Stage your product at the CMs. That is, carry some extra inventory and have it as available as possible for when the system demand returns to normal (if it dips at all). The worst that could happen is inventory is managed down, then system demand returns and you, our customers, are facing ASIC type lead times to re-engage.

The CMs will go for this as well. They need to protect their revenue stream, which means every component needs to be ready and available for the inevitable ramp. Don’t be the long pole in the tent. The VCP model can help with die bank inventory, managing the supply chain with the benefit of the ability to make trade-offs with suppliers over a large portfolio, report progress in Japan, qualify new sources…and so on.

Japan will bounce back mostly because of the tenacity of the Japanese people. In the meantime, an efficient distribution and usage of its goods and services by the rest of the semiconductor world is required for revenue and repair. I am proud of the contribution all VCPs are making in these challenging times, and to assist Japan in attaining its goals. There has never been a better opportunity for us to serve our customers, suppliers and the Japanese people, than right now. Let’s see this through.

–Jack Harding is chairman and CEO of eSilicon

Cross Section of TSVs, source: P. Leduc, LETI, D43D, 2010

Terminology
• 2.5D: refers to having one or several die mounted to another inactive die with thru-silicon vias in order to route nets between the active die and to the substrate.
• 3D-IC: refers to one or several die mounted to the backside of an active silicon die through these TSVs
• Glass interposer: A die made of glass with vias that connect both sides of glass die together for signal/power transmission.
• Silicon interposer: A die made of silicon with vias that connect both sides of glass die together for signal/power transmission.
• Tile: a die mounted to a glass-interposer, silicon interposer or 3D-IC. These generally have microbump pitches of 30-80um.
• TSV: Thru-silicon-via, a via that connects two opposite sides of a silicon die/wafer. This can be seen in the image in the upper right corner.

Short flat microbumps, source: KK Tzu, ITRI, RTI 2010

EDA tool infrastructure
The market for the design of 3D-IC and 2.5D interposers really started with several niche players making standalone tools to address this need. Most of these are on open-architecture platforms, so they share data with some other EDA tools. It is not clear if these niche EDA tool companies will gain significant market share before the larger EDA tool companies have a chance to surpass them. At least one of the major EDA tool companies is already presenting a solution at tradeshows. The lack of design kits from the wafer fabs has given these large EDA companies a chance to catch up and apply their greater resources to enter this 3D-IC and 2.5D design space.

One interesting observation I made after seeing some of these tools in action is that they appear to be built on package design platforms instead of physical design platforms. This may be because 2.5D solutions look like miniature package substrates that then get inserted into other more-conventional package substrates. Therefore, from an EDA tool perspective this can appear much more like a stacked-die package design rather than a physical design on silicon. What has not been clearly demonstrated is the solution for 3D-IC in ASIC designs, by a major EDA tool company. This would appear much less like a stacked-die layout and more like a physical design, so there is still some more evolution needed in the tool space to address this 3D-IC technology. Critical steps such as LVS (layout versus schematic) checking still have limitations with this technology. Additionally, timing analysis of nets between chips in this space is further complicated by the TSV connections and routing on different die without signal buffering.

Most sources agree that 3D-IC will not likely be mature enough for wide adoption for another two years or so in the ASIC space. On the other hand, 2.5D is much further along with regards to EDA tool readiness, likely due to the silicon-interposer’s similarity to an embedded package substrate.

Short copper posts with solder, source: E. Beyne, IMEC, RTI 2010

Interposer supply
The good news here is that there are several interposer suppliers in the market enabling the 2.5D marketplace. The bad news is that their solutions are considerably different from one another and so are their cost structures. The major wafer fabs are keeping their cards close to their chest until clear standards emerge in order to avoid the expense of re-tooling at a later date. For those of us in the ASIC space, this poses some interesting questions. Either partner with new suppliers for early access to the technology or wait until the major industry players open their doors with standard design kits. Only a select few are being given a sneak preview of the incomplete design kits as early adopters. The rest either end up waiting by the sidelines or partnering with the select few able to access these design kits.

Wafer probe
Probing of the tiles that interface to the silicon interposer or 3D-IC die cannot be done with conventional vertical-probe or cantilever probe technology. After all, these microbump pitches of 30-80um are too tight for these conventional approaches. Instead, several companies are devising new families of probe cards, which are generally based on MEMS technology. This means that the up-front cost for a probe card may go up considerably. MEMS probe cards have been available for some time, but the finer technology needed may make these a little more difficult to manufacture and maintain. The production cost structure here is not well understood yet, but at least a solution exists.

Tall posts with solder tips, source: P. Royannez, et.al., IME, RTI2010

Assembly
Assembly is one of the hurdles that has been addressed, but unfortunately there is little uniformity in how this is done. Some solutions in the wafer-to-wafer (W2W) format utilize a multitude of bonding techniques, but in the ASIC space this should not be a major concern. It is unlikely that W2W bonding will be used in ASICs other than embedding stacked memory die in a 2.5D or 3D ASIC solution. At this point, the wafers are already bonded to each other and will likely be delivered by the memory suppliers in tape-and-reel format.

The two options for ASIC assembly of TSV devices will be die-to-wafer (D2W) and die-to-die (D2D), but I expect D2D to be the prevalent format for ASIC solutions. The reason I expect D2D to be the dominant format for ASIC assembly is that this allows the greatest flexibility of what to put on the TSV wafer, and it also eliminates the difficult thin-wafer handling. Wafers with TSV will be somewhere in the 50-150um thick range, and, if given the option, the assembly sites would surely opt for the more robust D2D solution.

There are no clear assembly standards. Standards are being initiated for wafer handling as well as reliability, but assembly still has a hole in standards coverage. For example, some TSV technologies have copper posts with solder on the end, others have round bumps, while others may have relatively flat connections that are meant for having copper posts on both die in order to form the interconnect. Examples of these can be seen on the lower three images in this post. The assembly for these different formats may require different assembly strategies that may not be easily mixed. In addition, the gap between the die may be different resulting in different underfilling (plastic gap-filling between the die) materials and methodologies. In order to have multiple die capable of assembly on the same 2.5D or 3D-IC device, the assembly processes need to be compatible. At the moment, ASSP and FPGA providers design all of the die in the package, but this may not be the case in the ASIC space. For this, standards will be required to enable this technology for those of us the in ASIC realm.

Reliability
JEDEC’s JC-14.3 committee is working on the reliability standards required for this technology. This will clearly address concerns currently preventing wider adoption of the technology. Having standards that clearly define reliable packaging will help us all, so we are looking forward to the output of this committee.

Shipment of TSV wafer and die
SEMI and Sematech have been working on standards primarily for handling these delicate TSV wafers and die. The current directions include bonded wafers, bare die, W2W attachment methods, etc. These standards normally take about a half-year to release, so expect to see the fruit of this effort towards the middle of 2011. This happens to coincide with the expected release of the wide-IO memory standard being developed by JEDEC. This means that the end of 2011 should see a significant flurry of activity.

–Javier DeLaCruz is eSilicon’s Semiconductor Packaging Director.

In the epic battle of cost and performance, MCMs (multi-chip modules) had generally lost to SoCs (systems on chip) due to higher package-assembly costs and lower performance. The tides are turning.

Four factors have been in play in recently:

1. Package assembly costs of MCMs have been dropping in recent years.
2. MCM package technologies are becoming commonplace instead of being relegated to certain applications such as memory or image sensors.
3. Emerging technologies are eliminating performance limits on MCM’s.
4. Tapeout costs are increasing exponentially as wafer technology nodes shrink.

Tapeouts that only cost about $200k a few nodes ago now run in the millions of dollars at 28nm. This means companies will need to have fewer tapeouts in order to support their product lines. The risk with each tapeout is higher and there is not much room for adding different flavors of product unless there is a considerable market for each individual product.

MCMs may serve as a solution for this issue. One approach for MCMs is to create a base chip that can interface with several different devices to make a family of products. The base chip can remain the same, but it can be paired with complementary devices and potentially different packages to gain the variety of interfaces or functionality needed to serve multiple markets or customer requirements.

What drives the cost?
The interconnect between these chips is the main cost factor. Direct die-to-die wirebonding can be the least expensive, assuming the die are planned for MCM integration. That means there are no funky wirebond angles or dense traces on a laminate acting as jumpers to move a signal from one side of the die to the other. Mixing interconnect methodologies such as flipchip and wirebond can drive up costs, but even this option is becoming mainstream.

The single most expensive cost driver is poor planning. If two die are designed in isolation, integrating them into a low-cost MCM will be more expensive (possibly much more) than if at least one of the die was designed with an awareness of the interconnectivity of the other die in the MCM package.

Area Benefit
Package-on-Package (PoP) technologies have been mainstream for some time. The last Apple iPhone A4 processor used a flipchip die on the bottom package and two wire-bonded stacked memories for the upper package. The benefit here was driven mainly by board area, but this volume application is also helping to drive down cost for this approach in the industry.

Applications such as high-end network processors are not as cost sensitive. For these applications, the adoption of MCM packaging really has been driven by area reduction and external pin count reduction. By bringing the memory devices into the package, the number of balls needed to connect to the PCB is considerably reduced. While this does not appear initially to be a cost-incentivized action on the package, it does reduce the overall system cost. Depending upon how this is executed, bringing external memory (bare die or packaged memory) into the MCM actually may be a much less expensive option under some circumstances.

What will drive MCM adoption?
Cost and area savings are clear and valid reasons for moving towards MCM’s, but a drive towards flexibility may be the next large factor. The ever-increasing cost of a tapeout means that it may no longer be practical to have a family of parts that serve various segments in a market. Instead, a single tapeout that integrates other devices to add flexibility may offer the opportunity to have a family of parts with a single tapeout.

This is a new angle on design and re-use. Design and re-use was a cornerstone of SoC IP, but now the re-use may come from die that are shared across multiple packages in order to mix and match interfaces or additional functionality. We have already seen many of these strategies in the market as well as in our own activity. This driver may not tackle the unit-cost challenge but it certainly addresses the issue of rising NRE costs for the most advanced nodes. The difficulty here is changing the mindset of ASIC design teams so they start with this end-game strategy in mind.

This MCM activity requires much more concurrent activity with what was once considered downstream activity such as packaging, thermal management, signal integrity, etc. Some companies will understand this and take advantage of it sooner. Once they’ve established a critical mass of complementary die to use in adding flexibility to their ASICs they will have an advantage over those who underestimated the extent of the potential benefits of MCM adoption.

–Javier DeLaCruz is eSilicon’s Semiconductor Packaging Director.

For each of the four major elements we have evolved down a different strategic path. For the processor, ARM, MIPS and a couple hangers-on have given the market an IP roadmap so potent that even the discussion of a homemade solution has become as rare as the IP was 15 years ago.

The I/O spans a relatively broad range from the pedestrian to 17-gig SerDes, the latter constituting such a bold technical challenge that all the serious suppliers can be counted on one hand and even that group is shrinking down to our partner, Avago Technologies, and a few IDMs; it’s hard and is what it is. In other words, no SoC developer has any measurable influence over the technology. The fact that a high-performance SerDes actually does its job over a hundred lanes or more is a borderline miracle. One needs to design around it, not vice versa.

The customers’ RTL has and continues to be the object of most of the EDA munching and crunching—the search for smaller, faster and lower power. Since the processor and I/O have been purchased off-the-shelf, the customer design is the focus of most attempts to optimize.

This brings us to the fourth major category…memory. Much like the other third-party IP on an SoC, memory has been off-the-shelf for all but the largest companies. Simply put, one bought a memory that was “close enough.” And for many designs going forward that solution will continue to be the right one; it works, is silicon tested, is widely used and well documented…why not? However, for some SoCs where the rest of the IC has been optimized to a level of diminishing returns it may be that a customized memory will offer some options to reduce area, power and improve performance.

In fact, for many advanced SoCs that is precisely what we are observing. The 40nm and beyond crowd has it figured out…customized memory could be a rich vein of potential optimization.

The SoC development model is here and will only become more important a means to manage cost and time to market. Of the four major SoC elements memory may be the newest and, possibly, the last frontier for optimization. But one thing is for sure—if a developer is going to spend the $50M to $100M needed to bring a 28nm IC to market, he/she will at least understand the tradeoffs of customized memory vs. off-the-shelf memory. It’s a knowable trade-off and is one worth considering.

–Jack Harding is chairman and CEO of eSilicon

Let’s take an example of a basic WiFi-enabled ASIC. What is the lowest-cost solution? Well, it depends upon what it is going into. If the part is going into a handheld device such as a smart phone, then the lowest-cost solution would likely be a WLCSP (wafer-level chip-scale-package), which is much like a bumped die without a package. Given that the PCBs (printed circuit boards) used by smart phones can handle this smaller bump pitch and trace/space geometry, this makes a lot of sense. On the other hand, if this was going into a home Internet router, a WLCSP would be enormously expensive since it would require utilizing PCB design rules that are uncommon for these larger PCB’s found in typical home routers. It would end up making the system cost go up as the PCB required to route the WLCSP would be likely cost several dollars more. Instead, going to a larger conventional TFBGA with something like 0.8mm or 1.0mm ball pitch makes sense. This is a clear example of how a more expensive package is a better-cost solution.

There are many tradeoffs to be made. The previous example is based on exit routing rules. Let’s consider an example of thermal and signal integrity considerations on a processor-type device. When making the tradeoffs between a thermally enhanced PBGA (HSBGA) or a flipchip BGA (FCBGA), the HSBGA may be less expensive from a packaging cost standpoint. They may both work thermally and electrically, and the HSBGA may be less expensive, so that may appear as the more logical choice, right? Maybe not! With a deeper analysis, you may find that the more expensive FCBGA is a more prudent solution. The FCBGA will likely end up consuming less of the signal integrity budget (reflection and loss) and would also be considerably more thermally efficient then a HSBGA. This may end up requiring a less expensive PCB and a smaller heatsink. It may also require less airflow or none at all.

Please make sure to consider the cost of the system above all else. The cost of the individual component may not be nearly as relevant. Having all of the resources available to make decisions at multiple levels upfront is paramount. If you do not have these resources easily available, finding a partner that can bring these vantage points to the table will work to your advantage.

–Javier DeLaCruz is eSilicon’s Semiconductor Packaging Director

By Jack Harding

I can remember back to 1995 and the first time I heard Joe Costello at Cadence speak publicly about the “disaggregation of the supply chain.” Disaggregation? Was that even a word in Webster’s Dictionary? It didn’t matter because, like many other concepts championed by Joe, it was the word every journalist and analyst in the semiconductor space was using to describe the phenomenon of the vertically integrated companies (IDMs) buying goods and services from a rapidly expanding number of specialists that could perform the same internal function faster, better and cheaper.

In other words, Joe observed the force that has driven our ecosystem for the last 15 years—the totally disaggregated supply chain.

Now, this has been going on since the early ’70s and was well under way for assembly, EDA and wafers. But in 1995 it was different. The very notion of a company even attempting to stay vertical was deemed a folly survivable only by the giants: Intel, IBM, Samsung and a handful more. The difference by then was The Fabless Semiconductor Association (FSA), now the Global Semiconductor Alliance (GSA), was born. Venture capital funded only those companies that outsourced and off-shored. Hundreds of companies were formed to resolve the specialized opportunities born out of the relentless growth in complexity.

Well, Joe isn’t prognosticating as much these days, but even those of us slower on the uptake can see that trend is waning.

We are reintegrating—or may be we should call it anti-disaggregating. Anyway, think about this. Just like the semiconductor “cousin” industries of enterprise software and contract manufacturing, the semiconductor space is rolling back up. EDA is on an IP acquisition tear. Big semiconductors companies are swallowing a smaller fish per week. Even Intel picked up Wind River. Say what?

And if you think this is just a fad consider this reality: When your supply chain rolls up…you’d better, too. Why, because they will use their rediscovered clout to tell you what the price is going to be. Think about it. If you don’t like what price Flextronics quotes you can you go to Solectron, right? Oops. Flex bought them a while ago. If Synopsys charges a dear price for some of its AMS products can you run over to Virage? Virage who? You get the point.

So who can afford to be small? Nobody. In a roll-up universe the sideliners get shoved into a black hole.

Yes, complexity is still increasing relentlessly, some would say exponentially. But, it appears the financial rewards of size are trumping the specialization benefits of disaggregation. In other words, at least for this 15-year cycle, size has defeated specializations as the margin of victory.

Enter the VCP (sounds like a Bruce Lee movie). The Value Chain Producer was and is the logical response to those companies that care not to play the semi game (OEMs) or cannot play effectively (the smaller fabless guys). VCPs aggregate both the technical skills and the buying power to emulate the bigger players in the rollup game. On the supply side, their customers tap into a VCP’s long-term and efficient relationships with suppliers that are rewarded with lower pricing and better allocation. From an engineering perspective, most companies cannot possibly hire and retain the array of people with the skill sets required to develop a 40nm chip. That club is shrinking every quarter.

So, here are the choices: 1) Grow like hell yourself and outperform the market until you are a “big guy”; 2) assume a “big guy” will acquire you and to your satisfaction (BTW, the last guy to get acquired gets the worst deal because he represents the smallest percentage of the market), or 3) buy yourself some time by working with a VCP until you figure out 1 or 2. The worst thing that happens to you is you pay less for a better product with less risk.

Joe was right fifteen years ago. I believe the facts support the idea the VCPs are right today. Don’t kid yourself about playing this game alone. The market is rolling and rolling fast. Your buying power has eroded. The skill sets have already become too expensive and critical, and the semiconductor market is reintegrating while you sit by and watch.

–Jack Harding is president and CEO of eSilicon.

This article will use some real-life examples from the electronics industry and describe one way for a fabless semiconductor company or a system OEM company to place itself in a position that greatly reduces the likelihood of being afflicted by inattentional blindness when making key decisions relating to their product development. The tangible benefit of course is being able to get a product out to the end-market at reduced risk, lower total cost of ownership and shorter time to market.

Good enough is optimal
Remember the Apple Newton, an early PDA from Apple Computer (now Apple). According to reports, one of the issues that plagued the development and delayed the release of that product was the very high bar that the company set for the product of being able to recognize free-style handwriting. The market, at that time, had a burgeoning need for a hand-held PDA and U.S. Robotics seized that opportunity, defined an alphabet that their PDA could recognize and successfully launched the Palm Pilot product. Meanwhile, the Apple Newton faded into the sunset. This is an example of a company trying to build a perfect product versus taking a good-enough approach that meets the customer need and getting to market quickly.

In the chip-development space, manifestation of this kind of problem can be seen with companies invariably trying to move to the next generation process node and attempting to integrate a multitude of their previous generation chips. Moore’s law is so ingrained in our system and minds that, irrespective of the market segments, companies always try to integrate all they can into their next chip instead of thinking whether an MCM or SiP may be a better way for their next product. A better approach for the next product may be to simply leverage their existing chips, integrate them in a SiP, add a new software stack and release the product to market earlier than the competition, so a lion’s share of the market can be captured.

Good enough is detrimental
The talk of the world nowadays is how it was possible for Apple to have not noticed the “Antenna” problem before it released the iPhone4. This is neither a quality problem nor a manufacturing problem but rather a design problem. No one knows exactly what happened during the design review phase and what tradeoffs were considered and taken. Knowing there will be millions of iPhone4 users who will be holding the phone differently should have been a primary factor that went into the design of the phone and the location of the antenna. It is the holding-hand/phone physical-contact interface that must have been of paramount importance in the design of the product. Knowing that the phone design will work for a good percentage of users was not an acceptable tradeoff. This is a situation where good enough was not an acceptable choice. In fact, it was a bad choice. One can only guess if this had anything to do with the sudden departure in August of Apple’s senior VP of devices hardware engineering. Given the huge following that Apple has and the popularity of the iPhone, Apple will weather this storm and come out ahead. But any other company in this situation would have likely fared very poorly.

In the chip-development space, manifestation of this kind of problem may be seen with companies that are building products for the communications market. Example: Some companies purely focus on procuring the lowest cost SerDes IP without any regard to what their finished chips will interact with on either side of the data flow. For example, if you’re building an NPU chip, it is very important to note whose switch fabric chips and whose Framer/MAC chips will be used in the system. Depending on that, you will know whose SerDes IP is being used in the Framer/MAC chips and the switch fabric chips. The reason this is important is because using the same SerDes IP in your NPU chip will ensure your chip will not have any interoperability issues by design. This makes it easier for the NPU chip company to sell its chips to system companies such as Cisco and Juniper. The NPU chip company may have to do variants of its chip depending on which system companies it wants to sell to but the effort and cost involved may be well worth it.

A better way
Bringing products to market today is a multifaceted, global process often requiring involvement from a range of suppliers including foundries, IP suppliers, design tool and services providers, test and packaging/assembly service providers, just to name a few. This semiconductor value chain differs depending on a customer’s unique requirements and design.

As a customer, if you’re trying to interface directly with these entities, there is a good chance that you may be affected by inattentional blindness. For example, going direct with a foundry will cause one to see all the great benefits of the latest process node and distract them from seeing if these features are really needed for their product.

Interfacing directly with an IP supplier may cause the customer to see only the best features of that IP and the IP cost but distract the customer from seeing if that is the right choice of IP for its products given where and how its products will be used in the system.

Seeking the services of a Value Chain Producer (VCP) may be the better way to get the customer’s products built. A VCP’s goals are always aligned with those of the customers, as the VCP’s sole motivation is to help its customers get their products designed, manufactured and productized with minimized risk, shortened time to market and optimal total cost of ownership. An independent VCP—meaning one that is not partly owned by a foundry or any other supply chain entity—does not have any vested interest to promote a particular process node or piece of IP or a package.

Conclusion
It is imperative that businesses ask the pivotal question of “Is this good enough?” at every key decision point of the product development including system architecture and design, process technology selection, IP selection, package selection, multi-chip integration decision, including service provider selection. As discussed in this article, it is not an easy decision. For the same customer, the “good enough” choices made for one product may not be good for other products. And where it makes sense, choose an independent partner to help make those choices.

Kalar Rajendiran is senior director of marketing at eSilicon.

For years, a 45×45mm body size was really the upper limit on organic flipchip packages (HFCBGA). The reason for this was the curvature of the package laminate that occurred due to the thermal expansion mismatch between the silicon (2.5ppm/°C) and the substrate (17ppm/°C). As the package grew, this curvature caused a flatness problem for the field of solderballs on the package.

This spec is referred to as coplanarity and is governed by JEDEC standards. For these larger packages, the spec for coplanarity is 0.2mm. This is a very important and seldom discussed dimension in larger packages because it will determine whether or not a part will be solderable to a PCB. Generally this number is pretty conservative, and it needs to be because JEDEC does not know the thickness of the solder stencil that will be used at PCB assembly. A thick stencil means a thicker deposit of solder will be made on the PCB at assembly, which would accommodate a more warped package. This ignores the fact that as parts reach solder-melt temperatures, they tend to flatten out again since this high temperature is a much lower stress condition for a package in general. The “ddd” dimension in the dimensioned image shows how this coplanarity dimension is specified.

Ceramics had always been a solution to maintaining acceptable flatness for larger devices, but the inordinately high cost made this tradeoff difficult to swallow. Stiffener rings also have been used, but they are difficult to manage on a laminate prior to flipchip assembly, and are only usable on more expensive assembly lines. Lower-cost flipchip assembly subcontractors do not use devices with stiffener rings, given that they do not fit well into their assembly processes.

Several recent events have broadened the horizon for organic flipchip packages. There are now newer package dielectric materials that have a lower thermal expansion rate. This makes a part warp less after flipchip attach reflow. Another key point is that some assembly houses are using much thicker heat spreaders to re-flatten a package and keep it flatter. This seems to have opened the door to flipchip packages up to the 55×55mm range.

As the available size of a package grows and the interfaces continue to utilize more high-speed SerDes, you just can’t ignore the 800-pound gorilla in the room, heat dissipation! Pulling the heat out of these devices is rapidly becoming a bottleneck in this trend. The cost of pulling the heat out of these devices has been an afterthought, but really needs to be considered up front when planning for a device. Thermal estimates are not always accurate early on, so planning for a worst-case scenario may be prudent.

–Javier DeLaCruz is eSilicon’s semiconductor packaging director.