By Jack Harding
The vast majority of private fabless semiconductor companies are venture funded and, rationally, anticipate an exit through acquisition. The statistics around achieving an exit via an IPO are daunting, at best.

But, as we have all read, the valuations are much lower than they once were. One of the reasons is the recent valuations of the acquirers are lower. But there is another reason, more subtle in nature, and it can be the difference between a good and a poor exit. Specifically, the FSC operations are so inefficient they drag down the purchase price from the acquirer.

Like all good business management, the way to a better valuation is a better balance sheet. Keep what’s necessary to keep in-house, and outsource wherever possible.
The VCP model, for one, can improve gross margins for customers by 2% to 7% by leveraging commercial and technical advantages. By aggregating buying power and technical skills there is less waste and a broader skill set.

That’s all part of a successful outsourcing equation. It includes lower, not to exceed, guaranteed pricing, which is something the internal ops team cannot do. Other benefits include WIP financing for “cash challenged” companies, and a reduction in operating expenses.

When an acquirer arrives in your lobby it is typically a larger, successful firm. Its folks look at the FSC’s financial performance; see the places to save cost and tuck that away for future benefit…for them.

This is not theory. It is happening today. Just this week investment bankers came to see me to understand how their client’s financial performance improved so dramatically over a weekend. The answer: The customer outsourced its existing production.

Everybody wins. The acquirer gets a more efficient and competitive target company. The selling FSC gets paid for improvements they have already made. The suppliers have a superior, efficient interface to the outsourcer. The bankers potentially get a higher fee but they certainly endear themselves to the VCs that invested in the FSC.

Waste is bad. The internal ops teams at small companies are wasteful. The change is coming fast. Improve your margins before the acquirer knocks on your door.

–Jack Harding is chairman and CEO of eSilicon

By Javier DeLaCruz
So many of us in the semiconductors realm are guilty of using JEDEC thermal data incorrectly. I often get questions such as “how much power can this package handle” or “what’s the thermal efficiency of this package.” Unfortunately, in almost all situations these questions cannot be generally answered.

The numbers we throw around for thermal performance come from the JEDEC JESD51 thermal standard. This spec was really created to compare one package to another. Many folks have used this to determine the thermal performance of their package in their system, which is not correct. The following statement is contained in the twelfth chapter in the spec, and is commonly overlooked:

“While standardized thermal test information cannot apply directly to the many specific applications, the standardized results can help compare the relative thermal performance of different packages. A more meaningful comparison is possible if the test conditions are understood along with the factors affecting package thermal performance…

Several factors affect the thermal performance of a device in a user’s application. These include power dissipation in the component; airflow velocity, direction and turbulence level; power in adjacent components; two-sided vs. one-sided active component mounting; printed circuit board (PCB) orientation; and adjacent boards and their power dissipation.”.

Therefore, even the JEDEC committee that compiled this standard did not intend for these theta-ja and theta-jc numbers to be used the way they commonly are. These really are intended to compare one package to another. They do happen to be helpful indicators of approximate performance.

Let’s take a common example of how data may be misused in an application. Assume you have a device that is going into a handheld device such as a cell phone. Most folks will assume that theta-ja (thermal resistance from junction to ambient air) without airflow would make the most sense. This is actually a poor indicator of performance. First of all, the circuit boards used in a handheld device are generally smaller than the JEDEC 100mm x 100mm test boards, and hence have a much lower ability to absorb heat (lower thermal mass.) More importantly, the JEDEC condition of no airflow is actually more accurately described as no forced-airflow.

The JEDEC condition does allow for natural airflow to occur since the board is in a 300mm x 300mm x 300mm cube, so heat can rise from the device (shown in purple in the image,) cool off as it rises and then fall again, causing a natural air circulation in this large enclosure. This would not be the environment inside of a handheld device (unless your target market had really large hands). Therefore, there are several reasons why theta-ja is not a good indicator of thermal performance in this particular system.

This particular example has an interesting thermal solution. I’m sure most people reading this have had long conversations on a mobile phone when they notice their ear gets hot. Rest assured this is not caused by radiation. Instead, mobile phone system designers use one of the few components inside of their system that can spread heat effectively, which is the LCD display housing inside of the phone. Many of the most power hungry devices are located there and are in contact with the display to dissipate heat from the sealed interior of the phone to the exterior. Unfortunately, your ear is generally in contact with this same LCD display, so your ear ends up being the heat sink for these power devices. This is just another good reason to use a hands-free set while on a long discussion.

–Javier DeLaCruz is the semiconductor packaging director at eSilicon

By Kalar Rajendiran

In efforts to improve product quality AND cut development and production costs while decreasing time to market, fabless semiconductor companies (FSCs) and OEMs have outsourced functions that didn’t add value to their products and to the company’s bottom line. Over the past 20+ years, they’ve outsourced EDA tools, test and packaging, IP core development and of course, foundry services. As we’ve moved from 200-gate simple ICs to highly complex SoCs that contain, on average, 50 or more IP cores, integration has created major challenges that begin with design issues and carry through to complete production services. These challenges have led FSCs and OEMs to find experts who could do solve integration problems but without adding additional cost.

But why has IP integration become so challenging? The answer to that question comes from a closer examination of the semiconductor ecosystem. Traditionally, a majority of semiconductor companies were vertically integrated, having dedicated internal resources for every step in the supply chain from design to manufacturing and distribution. They were staffed by highly-specialized engineers who understood all aspects of design, manufacturing, packaging, and test. And, they were both willing and able to make the significant investment required to be successful.

Throughout the years though, this vertically-integrated approach to design evolved thanks to the adoption of outsourcing of different aspects of the semiconductor development process as a temporary measure during economic downturns. As the economy recovered, companies soon realized that it was simply more efficient to outsource than to bring different aspects of the development process back in-house. Consequently, the outsourced functions were often left alone. It made good business sense for companies to go wherever the required skills were available and where there existed the potential of local markets for their products. Over time, the number of specialized suppliers increased to such a degree that it brought about a new challenge – how to manage the supply chain or value chain. Today, many companies are finding an answer to this challenge in the Value Chain Producer model (Figure 1).

A better model
Bringing products to market today is a multifaceted, global process often requiring involvement from a range of suppliers including design tool and services providers, IP developers, equipment vendors, and test and packaging service providers; just to name a few. This semiconductor value chain differs depending on a customer’s unique requirements and design. The semiconductor VCP is a new breed of company that simplifies and optimizes this value chain by consolidating a number of services and solutions traditionally offered by disparate suppliers, and delivering them to the customer along with lower cost, lower risk and increased flexibility. Through these services, FSCs and OEMs are successfully taking on the next level of outsourcing—the outsourcing of everything from design through production depending on their needs. Companies have gone from “fabless” to “productless.” Today many come with R&D and application expertise and leave the rest to trusted partners.

–Kalar Rajendiran is senior director of marketing at eSilicon.

By Jack Harding
It should be no surprise. The industry has been consolidating and expanding and consolidating for nearly 40 years. So when Virage Logic was gobbled up by Synopsys and Denali was ingested by Cadence, it is really a lot more of the same. Or is it?

There is a difference. Synopsys has made it crystal clear that its definition of EDA now permanently includes IP. Not that acquiring Chipidea from MIPS was dabbling but, let’s face it, that deal—rumored to be in the low tens of millions price range—could have been construed as a bargain too irresistible to pass even if IP was not going to be mainstream.

That’s history. EDA is now and forever defined as tools to design and stuff to design around. After all, we just acquired tiny but formidable Silicon Design Solutions to have a large Asian footprint from which to grow, and along the way now find ourselves in the custom, dense memory IP business. That the piece, by the way, that Virage never wanted to do–the custom compilers and instances. Even the value-chain provider model includes IP and there’s no going back. The customers are asking for it, and we intend to acquire more.

With the rare exception of ARM, Rambus and Virage (and a few others), IP has been a bad business. IP needs the leverage of other value propositions and channels that it now seems to be getting; tools from Synopsys and chips from us.

So, for us, we now find ourselves in the interesting… and not yet enviable…position of selling the one piece of memory IP Synopsys doesn’t have. Brilliant strategy? Nah. Like most things in Silicon Valley “brilliant strategy” is just the folklore that gets retro-scribed after dumb luck serendipity.

Don’t get me wrong. We are thrilled with our SDS deal. But, let’s face it, we had no way of knowing we would end up with the one piece of IP Synopsys doesn’t sell or want to sell…so far.

What’s next? Well, we can expect Synopsys and Cadence to make a run at every private or low-market-cap IP company. The bet has been made and there is no backing out now. The only question is how far will they go. Is there an ARM/Synopsys deal on the horizon? While it can’t be imminent, for reasons ranging from ego to ecosystem, for the first time it’s not out of the question. (If you doubt that just look at the rollup of the foundry business and the inevitable two and only two sources of CMOS wafers.)

The question now is whom do you trust?

–Jack Harding is the chairman and CEO of eSilicon.

By Jack Harding
IP reusability has been a drumbeat in the semiconductor industry for a dozen years or more. The thesis is simple: Why build again what you already have? And with most durable, simple statements, the foundation is profundity.

The basic need has yielded breakthrough innovation from IP companies large and small. EDA methodologies to “assemble” blocks from pre-existing inventions, and business models like the Value Chain Producer (VCP) that provide the margin-of-victory services to tie it all together. After all, very few, if any, companies can track the specification and actual performance of IP blocks from dozens of suppliers. VCPs do. That is one of our many functions.

As the industry samples 40nm parts and dabbles with 28nm test cases, the imperative for reusability is greater than ever. To date, the form factor has been in cores and blocks. But that must change and it will because even the most “reused IP” on a 40nm device carries a too-expensive NRE tab, whether it’s reused or not.

The unit of measure for reusable IP is rapidly becoming the die. And the delivery mechanism is the Multi-Chip Module (MCM) or the so-called System-in-Package (SiP). Call it whatever you like. There is great promise in taking two die, perhaps both from your company or one from you and another from your partner, and creating a “device” that 1) goes to market faster; 2) has comparatively no NRE tab as compared to a 40nm development, and 3) definitely runs the existing software.

Further, when it’s time to integrate an Analog Front End (AFE) or a GaAs RF radio, probably acquired from a partner, there is no better solution.

But there is also no free lunch. MCMs or SiPs carry their own class of risk. They demand a level of packaging expertise that exceeds what’s held by most fabless companies: It’s die packaging, test, PCB and raw physics rolled into one unforgiving challenge. And once that code is cracked you get to wade through the commercial issues. Who owns the failure if the die comes from a partner?

No one can make a mask set cheaper. We can’t precipitously lower the cost of third-party IP. But there are ways to get to market faster, lower NRE and reuse the IP that either made you great or never saw the light of day.

–Jack Harding is chairman and CEO of eSilicon

By Jack Harding

With the recent Global Semiconductor Alliance (GSA) Board of Directors vote to create a new category of semiconductor company, the value chain producer’s contribution to the overall industry has been formalized and made permanent.

This should come as no surprise. The VCP market segment is closing in on $1 billion in annual sales. The category has evolved from a conceptual alternative to the classic ASIC model to the mainstream for the development of both ASICs for OEMs and ASSPs for the small and midsized fabless semiconductor companies (FSCs). Even some of the top fabless semiconductor companies are using this model.

Why is a new category warranted? The reasons are many but a common theme is that it’s simply getting too hard for the average company to make one or two mega complex parts per year.

Consider the following five reasons:

1. Complexity is forcing the daily availability of critical, specialized skills once provided by operations generalists. Packaging and signal integrity join power management and timing closure as major challenges. Most OEMs and FSCs can’t attract and afford these specialists, but a VCP can keep them engaged in a wide range of products.

2. Time and effort spent in vetting the supply chain and working on different contracts for each project isn’t a core competency of most companies. What they should be focusing on is product innovation and market growth.

3. Integration of chip sets into one SoC has greatly limited the learning curve available to any given team. They may have made four chips a year at 180nm, but now they’re probably only making one at 40nm. That makes it almost impossible to master the skill sets needed to move to 28nm.

4. Wasteful buying practices leave too many dollars on the table that can be optimized by the collective buying power of the VCP. A VCP can beat most companies pricing and still make a good margin. There is waste everywhere that needs to be purged.

5. Accessing the “R&D” in any given EDA tool, IP, wafer or package is best done by a high-volume buyer or a VCP. A company making one or two chips a year cannot stretch the limits compared to a major FSC nor leverage the special “bells and whistles” in any given tool or raw material for both performance and economics. VCPs solve these and many other problems.

A decade ago it wasn’t expected the VCP would be a new semiconductor category. Today there is no other way to resolve complexity, cost and integration problems globally and seamlessly with the existing supply chain.

Jack Harding is chairman, president and CEO of eSilicon.

By Jack Harding

The Global Semiconductor Alliance, the GSA, is at the front lines of a great opportunity. As the semiconductor industry has become a 24-hour-per-day, seven-day-per-week flywheel of activity and innovation, there is only one organization in the world poised to keep pace.

It was no stray coincidence that precipitated the renaming of the Fabless Semiconductor Association, the FSA, to the current handle. But more importantly, the renaming was no leap of faith or credibility. It was obvious and inevitable.

More than a decade ago, Bob Pepper saw the need for the then-fledgling fabless model to have a voice in a world dominated by massive IDMs and conglomerates. And it wasn’t just Intel and TI. United Technologies and GE were among the behemoths that saw both the business and strategic rationale to participate in an exciting space. The question in Bob’s mind I can only speculate (actually, he told me) was, “How do we get a toehold against these global players?” The result was the FSA.

Led then and now by Jodi Shelton, the GSA is no longer just the voice of the little guy but, rather, the eyes, ears, hands feet and voice of more than 50% of the semiconductor market; GSA is the body of the industry and growing every day.

We grow in two ways. The first is membership. Even many of yesteryear’s behemoths are members. They see the value and the reach. Second, there is an exciting geographic expansion that now incorporates Europe and all of Asia. In fact, the new leadership for this fiscal is chairman Nicky Lu, chairman and CEO of Taiwan-based Etron Technology Inc. and vice chairman Joep Van Beurden, CEO of CSR Plc of the UK.

The GSA is global in agenda, offices, staff, members and leadership.

So what’s the opportunity? In my view it’s becoming the cross-industry and intergovernmental advisor. With the momentum, reach and recognition the GSA now enjoys, what organization is better positioned to advise the other segments, like consumer products and automotive? And governments, both sophisticated in semis like the United States and Taiwan, or neophytes like Vietnam and Brazil, can benefit around the implementation of their policies and investments shaded by the nuances of this critical, strategic business. We can be there, too.

Like many Board members of the GSA, I have participated regularly in discussions and programs in both vectors. It is neither a luxury nor an option for GSA to take this role. Other organizations, like the Semiconductor Industry Association, the SIA, have a U.S.-only agenda and charter. Their role is important but limited. Semiconductors are international; the policies are international; and the markets are international….all the turf of the GSA.

Further, semiconductors are ubiquitous. Like Michael Porter of Harvard said a decade ago, “There are no low-tech industries; only low-tech companies.” Semis are at the hub of this statement and it is even truer today. What organization is more prepared to consult with the lagging companies of the world and the thoughtful industries attempting to digest our wares?

The GSA has the heritage, leadership, support and perspective to play this role. The question is whether it will pick up the baton and run like hell, or let some other lesser organization fill the vacuum. My money is on the GSA. It’s the right thing for all of us and a natural extension of the very vision and charter that conceived the GSA more than 15 years ago.

–Jack Harding is the CEO of eSilicon.

By Jack Harding

I recently participated in a panel hosted by TSMC.  The other panelists represented EDA, IP and Foundry market segments. We were asked to comment on new business models as a means to facilitate more design-starts in companies large and small and, otherwise, make it easier to be in this business with increasing NREs and greater complexity.

To my delight the EDA guy talked about software as a service. The IP guy talked about novel payment plans and strategic deals that concentrate the efficient development of basic IP into a few suppliers. The foundry guy from TSMC talked about how his company isn’t a bank. Well, two out of three isn’t bad. But he did say the foundry is receptive to new business and payment ideas that put more chips in production solving more problems.

These are all admirable goals and strategies, but all of these have to come together for the model to truly work. The new terminology is value chain producer, which combines SaaS, IP databases and services, unique financing to amortize NRE into production, finance WIP and manage die banks and other things that save the customer money.

It’s great the industry is recognizing that innovation must come in our business models, as well as our laboratories.  It’s great that TSMC is stepping up to its leadership role for these discussions. And it’s not so bad that the VCP model has emerged as a way of taking advantage of all of these models.

–Jack Harding is the CEO of eSilicon

By Jack Harding

When I started my career at IBM, one of the favorite sales lines we used was, “No one ever lost their job because they chose IBM.” In the burgeoning business computer market, that was true. Why? It wasn’t the size of the company. Actually, we were forbidden to link customer success with IBM’s “bigness,” which was an artifact of the Consent Decree with the U.S. Department of Justice. It wasn’t always the technology either. Fledglings DEC, Wang and Basic Four, not to mention HP, were often a generation ahead of us. Oh, and did I mention we were the most expensive?

So what was the difference? It was service, and not just seminars and brochures. It was what I call Dark Day Service. It was the belief, the trust, that we would fix the problem.

The Dark Days are the time in a project when the wheels come off…and we can thank entropy for the fact they always do. Dark Day Service was what the company did when that happened. What resources were brought? What attitude did the company present? What sensitivity and real concern was exhibited for the customer’s situation? Was there a sincere sense of urgency that led to the relentless pursuit of resolution and customer satisfaction?

Few companies ever really ingrain in their people the fundamental and unshakable truism that getting the customer to the goal line is everything. But those that do, reap the rewards of long-term profitable relationships. We see it in our industry. TSMC is known for its customer service and enjoys the leadership role. Synopsys has grabbed that high ground in EDA through customer satisfaction and became the leader as well. But it’s not always the biggest guys in the field that get the recognition as great Dark Day suppliers. We have enjoyed relationships with several small and very small IP suppliers that have done whatever it takes to make us successful and, thereby, allowed us pass it on to our customers. No, it’s not size, it’s attitude.

–Jack Harding is the CEO of eSilicon

By Jack Harding

When it comes to internal operations, “Do it yourself is dead.”

By internal operations I mean all those activities from netlist to EOL (end of life). After all, nobody makes their own EDA tools or wafers. So, why are there a thousand companies with teams of 5 to 200 all doing the same job and, in many cases, poorly? How good can you be at making one or two 65 or 40 nm chips a year? Where’s the learning curve? How do you justify the idle time? Where’s the buying power? And the fixed cost!

I was talking recently to an operations professional I’ve known over the years and said, “Imagine someone standing in front of your CEO, CFO and VP of sales saying, “No matter what [Fred] makes your chip for, what if it can be done for 5% less and guaranteed.”

His eyes widened and said the usual, “But I have the double secret, sacred handshake with [supplier] and I’m the only guy in the world that has his substrates delivered by carrier pigeon daily at noon.”

“Great, like I said, 5% cheaper and guaranteed.”

This time his head fell and he said, “But I love going to Asia and getting all that supplier attention and, besides, what will I do?” You get the picture. Operations guys working in small and medium-sized companies will be working for the aggregators soon much like EDA absorbed the thousands of developers dotted across the electronics landscape. The economics of a slowing industry demand it and it is unavoidable. And why not? How much waste can an aging industry absorb before management looks around and says operations has to go, like EDA, fabs, assembly, IP, layout and everything else? It’s inevitable and it’s happening now.

Like the admonition from the Borg on Star Trek, “Resistance is futile. You will be assimilated.”

Jack Harding is the CEO of eSilcon