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	<title>Comments on: How to Future-Proof A Hardware Designer</title>
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	<link>http://chipdesignmag.com/sld/mcdonald/2009/07/31/how-to-future-proof-a-hardware-designer/</link>
	<description>Deep Insights for Chip Architects and Engineers</description>
	<lastBuildDate>Wed, 03 Apr 2013 16:30:29 +0000</lastBuildDate>
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		<title>By: Jon McDonald</title>
		<link>http://chipdesignmag.com/sld/mcdonald/2009/07/31/how-to-future-proof-a-hardware-designer/comment-page-1/#comment-20</link>
		<dc:creator>Jon McDonald</dc:creator>
		<pubDate>Wed, 05 Aug 2009 14:39:21 +0000</pubDate>
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		<description>In preparing for the future we have to be aware that the future will not be the same as the present.  From a current and recent past perspective I agree that there may be 10X more RTL coders than architects. The challenge in this changing landscape is to understand were the value in design is being derived and as an engineer to focus my contribution in an area of high value.  With ESL capabilities improving in both high level synthesis and architectural specification and analysis the value in design is moving to the architectural level, I believe over time we will see the ratio of engineers focused on architecture to RTL increasing.  As Rishiyur states, &quot;good architectures trump everything&quot;, as ESL methodologies and tools become mainstream more resources will be invested in ensuring that we have a good architectures, ultimately requiring more engineers working at this level.</description>
		<content:encoded><![CDATA[<p>In preparing for the future we have to be aware that the future will not be the same as the present.  From a current and recent past perspective I agree that there may be 10X more RTL coders than architects. The challenge in this changing landscape is to understand were the value in design is being derived and as an engineer to focus my contribution in an area of high value.  With ESL capabilities improving in both high level synthesis and architectural specification and analysis the value in design is moving to the architectural level, I believe over time we will see the ratio of engineers focused on architecture to RTL increasing.  As Rishiyur states, &#8220;good architectures trump everything&#8221;, as ESL methodologies and tools become mainstream more resources will be invested in ensuring that we have a good architectures, ultimately requiring more engineers working at this level.</p>
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		<title>By: Daniel Payne</title>
		<link>http://chipdesignmag.com/sld/mcdonald/2009/07/31/how-to-future-proof-a-hardware-designer/comment-page-1/#comment-19</link>
		<dc:creator>Daniel Payne</dc:creator>
		<pubDate>Mon, 03 Aug 2009 15:44:55 +0000</pubDate>
		<guid isPermaLink="false">http://chipdesignmag.com/sld/mcdonald/?p=44#comment-19</guid>
		<description>Jon,

At EDA companies we knew that there was only 1 system architect per 10 or mroe RTL coders, so the challenge in becoming the architect is that there are so few positions available.</description>
		<content:encoded><![CDATA[<p>Jon,</p>
<p>At EDA companies we knew that there was only 1 system architect per 10 or mroe RTL coders, so the challenge in becoming the architect is that there are so few positions available.</p>
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		<title>By: Rishiyur Nikhil</title>
		<link>http://chipdesignmag.com/sld/mcdonald/2009/07/31/how-to-future-proof-a-hardware-designer/comment-page-1/#comment-18</link>
		<dc:creator>Rishiyur Nikhil</dc:creator>
		<pubDate>Fri, 31 Jul 2009 20:26:58 +0000</pubDate>
		<guid isPermaLink="false">http://chipdesignmag.com/sld/mcdonald/?p=44#comment-18</guid>
		<description>Amen! Word! You&#039;re singing our song!

We have long recommended that &quot;architectural transparency&quot; and &quot;high level architectural synthesis&quot; are the keys to value, i.e., to letting designers focus on what&#039;s important.  It&#039;s long been understood in software that &quot;good algorithms trump everything&quot;. The hardware version of this aphorism is that &quot;good architectures trump everything&quot;.

Good performance (area, latency, throughput, power, etc.) is all about good algorithmic cost models, and architectures are precisely the primary determinants of algorithmic cost models.  If you can&#039;t flexibly and precisely manipulate and control architectural choices, you&#039;re dead.

[ Which is why I&#039;m so skeptical about C/C++ synthesis, because they provide no transparency or control towards algorithmic cost models, but that&#039;s another story. ]

Rishiyur Nikhil, CTO, Bluespec, Inc.</description>
		<content:encoded><![CDATA[<p>Amen! Word! You&#8217;re singing our song!</p>
<p>We have long recommended that &#8220;architectural transparency&#8221; and &#8220;high level architectural synthesis&#8221; are the keys to value, i.e., to letting designers focus on what&#8217;s important.  It&#8217;s long been understood in software that &#8220;good algorithms trump everything&#8221;. The hardware version of this aphorism is that &#8220;good architectures trump everything&#8221;.</p>
<p>Good performance (area, latency, throughput, power, etc.) is all about good algorithmic cost models, and architectures are precisely the primary determinants of algorithmic cost models.  If you can&#8217;t flexibly and precisely manipulate and control architectural choices, you&#8217;re dead.</p>
<p>[ Which is why I'm so skeptical about C/C++ synthesis, because they provide no transparency or control towards algorithmic cost models, but that's another story. ]</p>
<p>Rishiyur Nikhil, CTO, Bluespec, Inc.</p>
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