When everyone hits the shops, some bloggers want to see presents fall from the sky. This week there is also a sleek design project, new uses for SoCs, an Arduino project (with video) a hypervisor discussion and a summit review.
This week, our blog search finds: Put on your music shoes; Wi-Fi’s next big wave; Trust, listen and learn; The three Cs of IoT, and much, much more
Coffee breaks and C layers; Ideas for IoT security; Weather protection technology; Productivity boost; Shining a light on dark silicon
IP fingerprinting; Beware- 5G!; And the award goes to – encryption; Fear of FinFET; Smart kids; Virtual vs real hardware
Although the venue was the German city of Nuremberg, there was a distinctive coterie of French companies at Embedded World, writes Caroline Hayes, senior editor.
Traditional EDA vendors are late in supporting one side of the electronics industry: software development. Although much is being said about system-level support and hardware/software co-design, the work has been left to companies like Altera, ARM®, Xilinx and others to develop software development tools.
ARM®’s Embedded Strategist Dominic Pajak talks about the latest innovations and why Makers are choosing ARM technology.
A fourth stage in the evolution of TrustZone® is a new market for security hardened apps.
European semiconductor company STMicroelectronics has announced sampling of the world’s first ARM® Cortex®-M7 based 32-bit MCU, the STM32 F7 series.
ARM® keeps to the core, building fundamental tools for everything in its line-up
Videos/PodcastsFPGAs for ASIC Prototyping Bridge Global Development
Clarifing Embedded IOT Connectivity Confusion
Low Power Engineering
IEEE Governance in Division Will a proposed amendment modernize the governance of one of the oldest technical societies...
Has The Time Come for SOC Embedded FPGAs? Shrinking technology nodes at lower product costs plus the rise of compute-intensive IOT applications...
- Renuka: So true for embedding sustainability aspects right from design mode.
- Dennis Brophy: I’m not certain I ever questioned an online offering for technical information coming out of...
- Jeff Brower: Chris- Your analysis is very good. I have been using your blog post since last year for reference in...
- Justin Nescott: It’s a honor to be included in your blog review. I’m glad you found the ANSYS Top 5...
- Daniel Payne: I think there’s a typo in the third paragraph with “0.07V”, should instead be 0.7V....
Jim Kobylecky Besides, eating a coding rivet from time to time has to be a whole lot less painful than the alternative. Hmm,...
Srini What a great prediction/foresight Gabe! We have indeed DVCon happening in India this year, 2014, intact little...
jblyler Hi Steve. Thx for the correction. I mentioned it to the editor and updated the post. Cheers. -- John
Windy Windy... DAC 2013 Pictures | JB's Circuit...
An interconnect, also referred to as a bus matrix or fabric, serves as the communication hub of multiple intellectual property (IP) cores inside a system on chip (SoC). As the capacity of today’s SoCs continues to increase dramatically…
Finding the optimal configuration options that meet the requirements of a particular system requires complementary design tools to enable the designer to rapidly explore and correlate trade-offs in performance, power, and area (PPA).
The recent advent of low-cost cluster management offerings have allowed IT organizations to adopt failover techniques for a variety of mission-critical systems, including the ENOVIA Synchronicity DesignSync Design Data Management (DDM) product from Dassault Systèmes. This paper provides a detailed example developed with a current semiconductor customer.
When templates, methodologies and verification IP components were integrated, suddenly simulation speed took a nosedive. Here’s why.
A new method for dramatically reducing CPU and RAM resource requirements.
New techniques that are making advanced SoC verification possible.
The relative advantages and disadvantages of single-threaded tag and multi-threaded non-blocking protocols.
A trove of technical videos and presentations from Cadence and other companies.
RTL flows are straining to meet the demands of most product teams. Moving up a level of abstraction is no longer an option.
A new design methodology is needed for rapid layout prototyping, in-design signoff and to improve collaboration between schematic and layout designers.