When everyone hits the shops, some bloggers want to see presents fall from the sky. This week there is also a sleek design project, new uses for SoCs, an Arduino project (with video) a hypervisor discussion and a summit review.
At advanced technology nodes (40nm and below), the number of options that a system-on-chip (SoC) designer faces is exploding. Choosing the correct combination of these options can have a dramatic impact on the quality, performance, cost and schedule of the final SoC.
Massively parallel architecture scales linearly beyond 10M instances while improving power, performance and area.
Hardware controlled power management is more efficient than CPU-based techniques.
The intelligent car should be considered a node on the Internet of Things (IoT).
A discussion about IoT definition, need for standards, and security.
Although the venue was the German city of Nuremberg, there was a distinctive coterie of French companies at Embedded World, writes Caroline Hayes, senior editor.
Physically aware synthesis techniques that can help accelerate the physical design closure process for high-performance, power-sensitive SoCs at 28nm and below.
Aart de Geus keynote and the Art or Science Panel prove that DVCon is not just for verification engineers.
Arduino beyond LAN; SoC secrets; NXP and Freescale; Connectivity at Mobile World Congress; Embedded Scandinavia; PCI Express verification, and more
Videos/PodcastsWhy IP Providers Need the New 1149.1/JTAG
Imec’s mm Wave Motion Sensing Technology
Low Power Engineering
Part II: The Ecstasy and the Agony of UVM Abstraction and Encapsulation Featuring the AMIQ APB VIP Part II of our tour through UVM reusability through TLM ports and the factory in the AMIQ...
The Ecstasy and the Agony of UVM Abstraction and Encapsulation Featuring the AMIQ APB VIP: Part I An interesting thing happened on the way to arriving at a completed article about the AMIQ...
- Renuka: So true for embedding sustainability aspects right from design mode.
- Dennis Brophy: I’m not certain I ever questioned an online offering for technical information coming out of...
- Jeff Brower: Chris- Your analysis is very good. I have been using your blog post since last year for reference in...
- Justin Nescott: It’s a honor to be included in your blog review. I’m glad you found the ANSYS Top 5...
- Daniel Payne: I think there’s a typo in the third paragraph with “0.07V”, should instead be 0.7V....
Jim Kobylecky Besides, eating a coding rivet from time to time has to be a whole lot less painful than the alternative. Hmm,...
Srini What a great prediction/foresight Gabe! We have indeed DVCon happening in India this year, 2014, intact little...
jblyler Hi Steve. Thx for the correction. I mentioned it to the editor and updated the post. Cheers. -- John
Windy Windy... DAC 2013 Pictures | JB's Circuit...
An interconnect, also referred to as a bus matrix or fabric, serves as the communication hub of multiple intellectual property (IP) cores inside a system on chip (SoC). As the capacity of today’s SoCs continues to increase dramatically…
Finding the optimal configuration options that meet the requirements of a particular system requires complementary design tools to enable the designer to rapidly explore and correlate trade-offs in performance, power, and area (PPA).
The recent advent of low-cost cluster management offerings have allowed IT organizations to adopt failover techniques for a variety of mission-critical systems, including the ENOVIA Synchronicity DesignSync Design Data Management (DDM) product from Dassault Systèmes. This paper provides a detailed example developed with a current semiconductor customer.
When templates, methodologies and verification IP components were integrated, suddenly simulation speed took a nosedive. Here’s why.
A new method for dramatically reducing CPU and RAM resource requirements.
New techniques that are making advanced SoC verification possible.
The relative advantages and disadvantages of single-threaded tag and multi-threaded non-blocking protocols.
A trove of technical videos and presentations from Cadence and other companies.
RTL flows are straining to meet the demands of most product teams. Moving up a level of abstraction is no longer an option.
A new design methodology is needed for rapid layout prototyping, in-design signoff and to improve collaboration between schematic and layout designers.