When everyone hits the shops, some bloggers want to see presents fall from the sky. This week there is also a sleek design project, new uses for SoCs, an Arduino project (with video) a hypervisor discussion and a summit review.
If you want to start a new successful EDA company look at the system level. Develop hardware and software components and the tools to assemble them together with third party proprietary components into a leading edge system.
The cost and complexity of the 14 nm process requires designers to be more creative in exploiting the characteristics of older processes. Tradeoffs between financial and technological issues are more important than ever.
Any short term predictions that Intel is in trouble seem off the mark to me, and the financial markets agree with my assessment.
Qualcomm uses Dassault Systemes’ dashboarding tool in its Hexagon DSP chip to incorporate multiple design metrics from key EDA tools.
Major ARM TechCon keynotes focus on societal shifts, defining IoT and little data’s big impact.
I have heard multiple times that once an EDA company goes public almost always the new investors do not experience the growth in the share price that other companies in the electronics industry can offer. At least this is what one hears from publicly traded EDA companies. My brief analysis disproves it.
Peregrine Semiconductor and GlobalFoundries create an RF SOI roadmap; Imec demonstrates an alternative FinFET and a metamaterial harvests energy wirelessly.
Videos/PodcastsIn Focus – System News for Feb. 2014
Nanotechnology Transforming Material Civilization
Low Power Engineering
Unexplained Absence: An Engineer's Cautionary Tale You may have noticed, (I hope at least), that I havent written here in a while. Heres why....
Jasper on Verification Gap s there a verification gap? Or is it that too much time is being spent inefficiently on verification?...
- Justin Nescott: It’s a honor to be included in your blog review. I’m glad you found the ANSYS Top 5...
- Daniel Payne: I think there’s a typo in the third paragraph with “0.07V”, should instead be 0.7V....
- Edward Thornton: Could you identify the author? It’s tough to understand if a Chip Design writer wrote this or...
- Drew Wingard: Wow! I wish that Sonics had been a big enough company to drive an IP standards organization that signed...
The Babylonian system au contraire, The xCORE XS1-L4-64 integrates four 32bit processor cores at a price under $3 that is comparable...
The Babylonian system that's because and thanks to The Babylonian system of mathematics ,the sexagesimal (base 60) numeral system. "From...
R Frank John, In Ireland the Croissants are terrible but the Guinness is really good. Your short piece energized me to...
Earle Rock on! All together or nothing , step up as one! Earle.
An interconnect, also referred to as a bus matrix or fabric, serves as the communication hub of multiple intellectual property (IP) cores inside a system on chip (SoC). As the capacity of today’s SoCs continues to increase dramatically…
Finding the optimal configuration options that meet the requirements of a particular system requires complementary design tools to enable the designer to rapidly explore and correlate trade-offs in performance, power, and area (PPA).
The recent advent of low-cost cluster management offerings have allowed IT organizations to adopt failover techniques for a variety of mission-critical systems, including the ENOVIA Synchronicity DesignSync Design Data Management (DDM) product from Dassault Systèmes. This paper provides a detailed example developed with a current semiconductor customer.
When templates, methodologies and verification IP components were integrated, suddenly simulation speed took a nosedive. Here’s why.
A new method for dramatically reducing CPU and RAM resource requirements.
New techniques that are making advanced SoC verification possible.
The relative advantages and disadvantages of single-threaded tag and multi-threaded non-blocking protocols.
A trove of technical videos and presentations from Cadence and other companies.
RTL flows are straining to meet the demands of most product teams. Moving up a level of abstraction is no longer an option.
A new design methodology is needed for rapid layout prototyping, in-design signoff and to improve collaboration between schematic and layout designers.