When everyone hits the shops, some bloggers want to see presents fall from the sky. This week there is also a sleek design project, new uses for SoCs, an Arduino project (with video) a hypervisor discussion and a summit review.
System Companies are changes in development methods will be more obvious in 2015 together with higher percentages of mixed/signals designs.
Synopsys won’t let the hybrid debate mess with your head; automating automotive verification; the write stuff; software’s role in wearable medical technology; ARM’s bandwidth stretching.
By Caroline Hayes, Senior Editor
ARM’s Cortex®-M7 provides performance and low power to IoT applications
The major constituent of system complexity today is the integration of computing with mechanical and human interfaces. Both of these are analog in nature, so designing mixed-signal systems is a necessity. The entire semiconductor chain is impacted by this requirement.
Leaving the solution to design and integration problems to a later stage of the development process creates more complexity since the network impacted is much larger. Each node in the architecture is now a collection of components and primitive electronic elements that dilute and thus hide the intended functional architecture.
Accellera prepares UVM; Shades of OpenGL ES; Healthy heart in 3D; Webinar for SoC-IoT; Smart watch tear-down
Wearables have secured a base in the fitness and health markets but growth is linked to associated technologies, related industries and emerging applications.
If you want to start a new successful EDA company look at the system level. Develop hardware and software components and the tools to assemble them together with third party proprietary components into a leading edge system.
The cost and complexity of the 14 nm process requires designers to be more creative in exploiting the characteristics of older processes. Tradeoffs between financial and technological issues are more important than ever.
Videos/PodcastsWhy IP Providers Need the New 1149.1/JTAG
Imec’s mm Wave Motion Sensing Technology
Low Power Engineering
Is Hardware Really That Much Different From Software When is hardware really software? Are software flows less complex? Are hardware tools less...
Citizen Science and The Search for Sputnik IV: Part 1 The holiday season is once again upon us, and, as usual this time of year, my thoughts are...
- Renuka: So true for embedding sustainability aspects right from design mode.
- Dennis Brophy: I’m not certain I ever questioned an online offering for technical information coming out of...
- Jeff Brower: Chris- Your analysis is very good. I have been using your blog post since last year for reference in...
- Justin Nescott: It’s a honor to be included in your blog review. I’m glad you found the ANSYS Top 5...
- Daniel Payne: I think there’s a typo in the third paragraph with “0.07V”, should instead be 0.7V....
Jim Kobylecky Besides, eating a coding rivet from time to time has to be a whole lot less painful than the alternative. Hmm,...
Srini What a great prediction/foresight Gabe! We have indeed DVCon happening in India this year, 2014, intact little...
jblyler Hi Steve. Thx for the correction. I mentioned it to the editor and updated the post. Cheers. -- John
Windy Windy... DAC 2013 Pictures | JB's Circuit...
An interconnect, also referred to as a bus matrix or fabric, serves as the communication hub of multiple intellectual property (IP) cores inside a system on chip (SoC). As the capacity of today’s SoCs continues to increase dramatically…
Finding the optimal configuration options that meet the requirements of a particular system requires complementary design tools to enable the designer to rapidly explore and correlate trade-offs in performance, power, and area (PPA).
The recent advent of low-cost cluster management offerings have allowed IT organizations to adopt failover techniques for a variety of mission-critical systems, including the ENOVIA Synchronicity DesignSync Design Data Management (DDM) product from Dassault Systèmes. This paper provides a detailed example developed with a current semiconductor customer.
When templates, methodologies and verification IP components were integrated, suddenly simulation speed took a nosedive. Here’s why.
A new method for dramatically reducing CPU and RAM resource requirements.
New techniques that are making advanced SoC verification possible.
The relative advantages and disadvantages of single-threaded tag and multi-threaded non-blocking protocols.
A trove of technical videos and presentations from Cadence and other companies.
RTL flows are straining to meet the demands of most product teams. Moving up a level of abstraction is no longer an option.
A new design methodology is needed for rapid layout prototyping, in-design signoff and to improve collaboration between schematic and layout designers.