When everyone hits the shops, some bloggers want to see presents fall from the sky. This week there is also a sleek design project, new uses for SoCs, an Arduino project (with video) a hypervisor discussion and a summit review.
I have heard multiple times that once an EDA company goes public almost always the new investors do not experience the growth in the share price that other companies in the electronics industry can offer. At least this is what one hears from publicly traded EDA companies. My brief analysis disproves it.
John Blyler from Extension Media interviews Jell De Smet, a senior researcher on smart contact lenses, Centre for Microsystems Technology (CMST), imec and Ghent University. This video was shot during the Imec Technology Forum in Oct. 2013 in Leuven, Belgium.
- Edward Thornton: Could you identify the author? It’s tough to understand if a Chip Design writer wrote this or...
- Drew Wingard: Wow! I wish that Sonics had been a big enough company to drive an IP standards organization that signed...
R Frank John, In Ireland the Croissants are terrible but the Guinness is really good. Your short piece energized me to...
hamilton I agree Daryl! I'd love to see one of these gadgets in working order.
Daryl Hanson Comptons global positioning system had an error of +/- of 6.7 miles, if you assume 1 degree is 67 miles. No even...
Bill C. I forgot to put the company name - it's Parallax
An interconnect, also referred to as a bus matrix or fabric, serves as the communication hub of multiple intellectual property (IP) cores inside a system on chip (SoC). As the capacity of today’s SoCs continues to increase dramatically…
Finding the optimal configuration options that meet the requirements of a particular system requires complementary design tools to enable the designer to rapidly explore and correlate trade-offs in performance, power, and area (PPA).
The recent advent of low-cost cluster management offerings have allowed IT organizations to adopt failover techniques for a variety of mission-critical systems, including the ENOVIA Synchronicity DesignSync Design Data Management (DDM) product from Dassault Systèmes. This paper provides a detailed example developed with a current semiconductor customer.
When templates, methodologies and verification IP components were integrated, suddenly simulation speed took a nosedive. Here’s why.
A new method for dramatically reducing CPU and RAM resource requirements.
New techniques that are making advanced SoC verification possible.
The relative advantages and disadvantages of single-threaded tag and multi-threaded non-blocking protocols.
A trove of technical videos and presentations from Cadence and other companies.
RTL flows are straining to meet the demands of most product teams. Moving up a level of abstraction is no longer an option.
A new design methodology is needed for rapid layout prototyping, in-design signoff and to improve collaboration between schematic and layout designers.