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Archive for June, 2014

Accellera Systems Initiative UVM 1.2

Wednesday, June 25th, 2014

Gabe Moretti, Contributing Editor

In one of my blogs from this year’s DAC I mentioned the panel on UVM held during Accellera traditional Tuesday morning breakfast. The subject of UVM 1.2 was covered then. Now Accellera has officially announced the release of the new version of its Universal Verification Methodology (UVM) class reference document, UVM 1.2 for SoC (system on chip) verification. UVM 1.2 improves interoperability and reduces the cost of IP development and reuse for each new project. The new version includes enhanced messaging, improvements to the register layer and other features. UVM 1.2 and its reference implementation are available for download under Apache 2.0 open source license at During the recent DAC conference Accellera also held a tutorial on UVM 1.2.
“The UVM working group has achieved the goals of its charter to enhance SoC productivity throughout the industry,” said Tom Alsop, UVM Working Group co-chair. “We are proud to report that UVM 1.2 continues the work to define new features and improve quality of the reference implementation.”
UVM 1.2 is entering a three-month review period ending October 1, 2014 with a commitment to take the resulting updated UVM 1.2 standard to the IEEE. Users are encouraged to post comments and suggestions using the following link:
During the panel discussion there were general praises for the new version although some of the panelists were a bit discouraged by the fact that the new standard is not compatible with the previous version. Unfortunately in building a standard is not possible to add significant new features and still maintain backward compatibility.

An Eclectic DAC

Wednesday, June 4th, 2014

The type of exhibitors at this year’s DAC 2014 was more varied than in previous year. For example I met with Riscure a Dutch company that specializes in security issues. They are hired by companies and goverments to test the security of chips used in credit cards, passports, and other ID cards. I also met with Tiempo, a French company that has developed a very secure chip used for the same applications. They use asynchronous circuits to defeat spoofing and the tools employed by Riscure.

On the services side I met with Oski that offers formal signoff services, and with eSilicon that offers a complete, easy to use and very fast way to obtain binding quotes from fabs on a large variety of projects. Mike Gianfagna, one of its early employees has rejoined while at the same time keeping strong ties with Atrenta. The service is worth testing out.

Gold Standard Simulation is a survivor of the Scottish Silicon Glen that has an impressive TCAD product worth testing if you would like to evaluate different processes and transistors architectures.
Coventor, initially only a MEMS company now also offers a TCAD simulator.

Allegro, another French company, offers H.264/MPEG-4 AVC/MVC//SVC Compliance streams as well as some IP for HEVC/H.265 encoding.

Invarian offers full-chip and SoC sign-off analysis tools for the challenges facing chip designers today. Using standard interface formats provides physical verification accurate, seamless, and fast with high capacity for Digital, Analog and Mixed signal designs.

So something for everyone with an emphasis on the total system, not just its electronic parts.


Tuesday, June 3rd, 2014

The second day of DAC was a very busy one for me. I met with Dassault Systeme that showed me an impressive approach to EDA based on project management system that provides different views of the state of the project depending on the viewer position in the project. For example, project manager, individual engineer, verification engineer, and so on. I met with Verific and Invionics two different companies that have found a symbiotic way to expand the market they serve without competing with each other.
Synopsys described their approach to the automotive market. The presentation described almost perfectly my 2014 Lincoln MKZ hybrid. It is impressive to see technology becoming reality as I write.
Carbon is growing, revenues were up 46% last year and diversifying. They were not quite ready for a big announcement at DAC but I was told it would be made before the end of this month.
Much work is going on in formal verification embolden by Cadence acquisition of Jasper Design.
More meetings are scheduled for tomorrow and I promise a final impression of what DAC meant for me.

Power management and IP

Monday, June 2nd, 2014

Moscone South is all about IP and low power.  This is the 51st DAC and my 34th.  Time flies.  The most intimidating thing is that the Apple Developers Forum is going on at the same time, and they have TV trucks and live interview on the street.  We of course do not.  It was nice to hear Antun Domic as one of the two keynote speakers this morning  His discussion on how the latest EDA tools are used to produce designs fabricated with processes as old as 180 nanometers was refreshing.  In general people equate the latest EDA tools with the latest semiconductor process.  Yet one needs to manage power even at 180 nanometers.

Chip Estimate runs a series of talks from IP developers in its booth.  I listened to Peter Mc Guiness of Imagination Technologies talk about advances in image processing.  it was interesting to hear him talk about lane departure warning as an automotive feature employing such technology.  Now I know how it works in one of my cars.  On the other hand to hear how the retail industry is planning to use facial recognition to choose for me what I should be interested in purchasing is not so reassuring.  But, on the other hand, its use in robotics applications is fashinating.