The Intricate Puzzle Known as Chip Design
Senior Vice President of Marketing and Business Development
These days, chip design may seem like an intricately connected jigsaw puzzle, including small, oddly shaped interlocking pieces. Instead of static parts of a puzzle – typically, 300, 500, 750 or 1,000 pieces – spread across a coffee table, a chip under design has loads of dynamic parts located in a variety of directories or sub-directories found on various computers. The focal point is the processor, not the center of a well-known and photographed painting or skyline, as is often the case with puzzles.
Ah, but memories are playing almost as big a role as processors, especially in chips slated for mobile multimedia devices with higher bandwidth and performance, and low-cost and power requirements. That means an engineer’s attention is being drawn away from the processor to an increasingly devilish piece of the design – the DDR memory subsystem that includes the DDR controller, PHY and I/O. The DDR memory subsystem, after all, manages the data traffic flowing to and from the processor and external DDR memory. More than a few engineers have struggled to bring up the DDR interface in a new chip design, followed by weeks calibrating the DDR interface timing. If something’s amiss with the DDR memory subsystem, chances are there will be product failure.
Fortunately, things aren’t that dire any longer for engineers worried about a chip’s system yield and reliability. One clever engineering group was motivated to figure this out. It set a goal to implement a DDR memory subsystem that would deliver the highest performance and quality within a small footprint and minimal power consumption. It identified a way to improve the DDR memory controller subsystem and solved the problem, though it wasn’t easy. For example, DDR memory chips must be small and fast to keep costs down, an important consideration for the group, and not a simple endeavor.
The elegant solution is an efficient piece of logic embedded in the DDR PHY that measures the system timing in-situ for improved device and system yield and reduced system bring-up. It is able to precisely measure the timing window and automatically adjust it for each system. It offers a flexible and customizable architecture and includes patented SCL (self-calibrating logic) and DSCL (dynamic self-calibrating logic) for real-time calibration to accommodate static and dynamic variations in the system operating environment. The self-calibrating logic precisely measures latency and the phase difference between the DDR clock and system clock and aligns the capture of DDR data within the center of the timing window.
What the engineers achieved is remarkable. The DDR memory subsystem enables a system to run at maximum performance and boosts device and system yield and reliability, reducing variation effects. Also, it maintains DDR memory system performance as temperature and supply voltages fluctuate during system operation. Not surprisingly, the need for SCL and DSCL is greater when speed and clocking are higher and margins smaller.
The proof can be found with one high-end, highly reliable HDTV series currently on the market. The savvy project group picked this DDR memory subsystem to improve the TV’s quality and reliability.
With this innovation, the chip design’s system yield and reliability puzzle has been solved leaving engineers to focus on crafting a chip custom-made for any number or variety of electronics devices.
About Bob Smith
Bob Smith is senior vice president of Marketing and Business Development at Uniquify. He began his career in high tech as an analog design engineer working at Hewlett Packard. Since then, he has spent more than 30 years in various roles in marketing, business development and executive management primarily working with startup and early stage companies. These companies include IKOS Systems, Synopsys, LogicVision, and Magma Design Automation. He was a member of the IPO teams that took Synopsys public in 1992 and Magma public in 2001. Smith received a Bachelor of Science degree in Electrical Engineering from the University of California at Davis and a Master of Science degree in Electrical Engineering from Stanford University.