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Intel’s FinFETs and Professor Asenov’s Independent Work

Gabe Moretti, Senior Editor

At this year’s DAC I met Professor Asen Asenov who is the Founder and CEO of Gold Standard Simulation (GSS) a TCAD company. Professor Asenov teaches in the Department of Electronics and Electrical Engineering at the University of Glasgow where he also heads the Device Modeling Group. I spent about an hour getting to know him and learning a lot about TCAD.
Over two years ago Professor Asenov published two blogs on the GSS webpage indicating that the trapezoidal shape of the Intel 22nm FinFETs is suboptimal and results in stronger short channel effects and in up to 15% reduction in current compared to an ‘ideal’ rectangular FinFETs. It would appear that Intel is a fast learner and according to a recent article in the German publication Golem website they have achieved the perfect rectangular shape in their 14nm FinFET offering.
The article shows the following figure to illustrate the improvements.

Dr. Asenov’s has written about the topic again and I am reporting part of his piece below.

“From a first glance the reduced fin pitch and increased fin height suggest more than 1.7x improvement of the drive current. However the drive current will be strongly affected by the contact resistance and the extrinsic access resistance, both of which are expected to increase with the scaling of the pitch.

GSS has recently simulated very similar rectangular shape FinFETs and the results are published in [1]. The table below compares the geometry of the 14nm Intel FinFETs with the devices simulated in the above paper.

Based on the GSS predictive Ensemble Monte Carlo simulations in [1] illustrated below the ‘intrinsic’ pFinFET drive current of the transistors simulated in the paper can be more than 1.6 mA/m; Vdd=0.75V. This is based on the assumption that 1.5 GP compressive strain can be introduced in the channel of the simulated transistors by suitable source/drain engineering. The velocity overshoot associated with the non-equilibrium velocity in the channel and the related high degree of ballisticity plays significant role in achieving such performance.

Strained Si pFinFET performance obtained form EMC, (b) Strain Si pFinFET carrier velocity. In the two graphs results of the EMC simulations are compared with results of ‘standard’ TCAD drift diffusion simulations before and after calibration.

However the Ensemble Monte Carlo simulations do not include the contact and additional access resistances. If access resistance of 1K ohm is included in the calibrated drift diffusion simulations the drive current drops from 1.6 mA/m to 1.2 mA/m. Access resistance of 2K ohm can reduce the drive current to 1.0 mA/m.”

In another instance this week I have been reminded of how small our industry really is and how well information travels, not always in “regular” channels among professionals in specific areas of the industry.

[1] L. Shifren, R. Aitken, A. Brown, V. Chandra, B. Cheng, C. Riddet, A. Alexander, B. Cline, C. Millar, S. Sinha, G. Yeric, A. Asenov, Predictive Simulation and Benchmarking of Si and Ge PMOS FinFETs for Future CMOS, IEEE Transactions on Electron Devices Vol. 61 No. 7, pp.2271-2277 (2014).

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