3D-IC’s Are the Future
Gabe Moretti, Senior Editor
Looking at a cross section of a 3D-IC one can most of the time see two or more distinct functional systems stacked over each other. These devices have taken the clue from real estate in order to find their initial architecture. When the lot (in this case the die) is too small, go vertical. So 3D-IC’s look like a multi-story building.
Each die is a stand alone functional system that cooperates with the other die to form a complete solution. We can say that most 3D-IC’s are really a packaging solution, not a system solution. Right now, due also to limitations in most EDA tools connections are built in two dimensions. The connection between the two or more dies happen as a result of integrating the communication among the systems. What if every cell could have six possible ways to connect instead of four?
I found scholarly papers on 3D-IC as far back as 2005. Not that there are none previously, I just did not find them. And a few of those I read did mention the problem of “thinking in three dimensions”. I think that soon engineers will learn to design in three dimensions and this will require significant development on the part of EDA tools vendors. There is really no reason why IC designers should not have the same freedom as PCB designers who enjoy a number of layers onto which to distribute the various components forming the system. And by the way, would there be an advantage to have power and ground on their separate IC layers? Or may be have a power bus that is thermally and electronically insulated from most, if not all, components?
Much has been written in the last few months about the “death” of Moore’s Law. If we can design in three dimensions, then the Law is not dead. We just have to define the area as a volume, and not just as a plane. Yes, I agree, it would take some sophisticated partitioning algorithm to divide a block into two, or more, planes instead of a plane. And I wonder, is it really optimal to separate vertically digital from analog and RF components? What if we could find that a vertical RF module distributed on more than one layer is better? Has someone thought of considering it?
I agree that manufacturing a 3D-IC is more challenging and yield is often mentioned as an obstacle to the growth of 3D-IC popularity. But, if a less challenging process could be used while at the same time take advantage of the latest versions of EDA tools, as Dr. Antun Domic of Synopsys suggested at DAC 2014, would the yield problem be significantly minimized if not all together eliminated?
Think outside the box by building the box and find a new way to grow.