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Archive for December, 2014

The eSilicon IP MarketPlace: Easy and Quick Integration of IP in Your Design

Monday, December 8th, 2014

Gabe Moretti, Senior Editor

The eSilicon IP MarketPlace product is simply what every IP vendor would like to have.  I am not a practicing designer, yet I found the environment easy to navigate, full of useful information, and an evaluation tool that takes one directly to selecting the correct IP for the target design.  Once I logged on and started my “test drive”, I felt instant gratification, as my commands produced data I could process readily, or information I could evaluate right away.  And the best thing is that it is free.

In my career as an editor I have very seldom started a product launch review so positively, but it is my job to give the correct information and this product is special.  The reason, I think, is because it bridges the gap between what one can learn from a good data sheet and what one finds when the GDS tape is generated.  In between there is a lot of work, and work that gets exponentially harder as we move to the latest process nodes technology.  And don’t even try to evaluate the same IP fabricated by two different foundries without this tool!  It would just take too long.

The IP MarketPlace environment helps users avoid complicated paperwork; find which memories will best help meet their chip’s power, performance, and area (PPA) targets that apply to your specific requirements, easily isolate key data, and perform vital “what-if” analysis.

The IP MarketPlace environment contains all eSilicon-developed IP across multiple foundries and technologies:

  • Memory compilers, including 28HPM TCAMs, four-port register files and two-port asynchronous register files
  • General-purpose I/O libraries from 16nm to 180nm
  • Specialty I/O libraries from 16nm to 180nm, including 1.8V/3.3V LVCMOS I/Os

Once a designer has chosen a memory type, IP Marketplace provides immediate answers with pre-loaded data for eSilicon memory compilers and I/O libraries.  Engineers can:

  • Generate dynamic, graphical analyses of power, performance and area (PPA) data
  • View data graphically, in table format, or download it to Microsoft Excel
  • Build and download a complete chip memory subsystem
  • Generate and download IP front-end views
  • Make changes over time and pay for the IP when ready to tape out (in the next release the payment will be made on-line without leaving the environment)

“We wanted to simplify the comparison of results across multiple technologies, architectures and other characteristics and take the guesswork out of hitting PPA targets,” said Lisa Minwell, eSilicon’s senior director of IP product marketing. “This goes much, much deeper than IP portals that serve as IP catalogs. Using the IP MarketPlace environment, users can download front-end views, run simulations in their own environments, then come back to purchase the back-end views of the IP and I/Os that best fit their design.”

To kick the tires go to  I bet you will be convinced.  The only drawback I found is that it may take up to 24 hours before you get access to the tool since they email you back your login information almost immediately but then you have to wait for another email that gives you access to the site where you can choose an IP and start working with it.  So the first time is not immediate gratification but, as I said, the wait is worth it.

EDA in 2015: Something New and Something Old

Monday, December 1st, 2014

Gabe Moretti, Senior Editor

Every year I like to contact EDA companies to ask what they expect in 2015.  When I started working on this project I visualized one article that would offer the opinions of EDA industry leaders from many companies covering their expectations for the coming year.  As work progressed I found, as I should have expected, that the responses to my questions were much broader and in depth than could possibly be covered in one article.  Doing so would have resulted in such a long article that would have surpassed the time limits most engineers have to read a magazine, even a digital one.

So I decided to publish three articles in addition to this introductory blog.  The decision is based mostly on the amount of feedback I received, and in part by how stand-alone the input was.  It turns out that both Cadence and Mentor provided me with material that can be judged to be a contributed article, while the rest of the companies submitted contributions that could be grouped into an article, albeit one significantly longer than normal.  The articles will be published during this week, one article a day.

Designers, architects, and verification engineers will find worthwhile material in more than one article.  One subject that is receiving attention lately and that is not covered directly in the articles is Agile IC Methodology.  In truth Chi-Ping Hsu of Cadence talks about the issue in his article, but not in the terms of the conversation going on under the auspices of Sonics, Inc.  I am sure that I will write about Agile IC Methodology in 2015 so this subject will receive its due attention.

Verification and mixed/signal design are the subject that have received the greatest attention.  But it is important to acknowledge the underlying drivers for such attention: hardware/software co-design, and the use of third party IP.  These are the true technology drivers.  From a market point of view, automotive looms important.  This market has been developing for a few years and has now reached the point in which it can approach its full potential.  Distributed intelligence and “Thing to Thing” communication and co-operation is within the grasps of product developers.  The automobile is the first working implementation of the Internet of Things (IoT).  IoT is in everyone’s mind in our industry, and the intelligent automobile, even if such product does not really use the internet architecture in most instances, is often used as an example.  The IoT will certainly be a significant driver of our industry, but its growth ramp in 2015 will still be linear as we continue to understand what the hierarchical architecture should really look like.  At this point anything that could possibly generate data is seen as a good prospect, but soon the market will discover that much of the data may be interst9ing but it is not necessary, and in fact would just clutter one’s life.  As usual, customers’ demand will inject sense in the market.

In a time when all festivities seem to start two months before they actually occur let me be one of the firsts to wish all of you a productive and peaceful 2015.