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Archive for February, 2015

DVCon is the Primary Design and Verification Conference

Friday, February 20th, 2015

Gabe Moretti, Senior editor

DVCon United States opens on March 2nd and ends on March 5th.  If you have not yet made plans to attend and have something to do with developing ICs you should plan to attend.  The growth of this conference has been remarkable.

In February 2000 VHDL International (VI) and Open Verilog International (OVI) agreed to merge and form Accellera.  That year DVCon, which until 2003 was called HDLCon, took place with the format it had for the previous 12 years.  Started in 1988 as the co-location of the Verilog Users Group and the VHDL International Users Forum (VIUF), DVCon was successful since its inception.

The name DVCon derives from Design and Verification Conference, and its focus was, and in part still is, the development, use, and improvement of Hardware Description Languages.  This year’s conference is the 27th and offers an expanded technical program.  In spite of the consolidation occurring in the industry the exhibit space has remained practically the same as last year.  Although this year there will be one less tutorial than the previous year, the breath of topics is larger.

The merger of OVI and VI produced significant changes, both for DVCon and for Accellera.  In 2001 DVCon boosted a more efficient organization, both for its technical program and for exhibits.  The source of papers offered for acceptance increased in scope as professionals outside of the Verilog and VHDL users communities became interested in presenting papers at the conference.

As Accellera grew and widened the scope of technical subject it handled, so DVCon increased the technical segments it covered.  First SystemC and shortly thereafter SystemVerilog provided interesting papers and Tutorials.  The verification aspect of the conference was enlivened with focus on UVM (Universal Verification Methodology), TLM (Transaction Level Modeling), testbench construction, and various approaches to testing, including formal techniques.

As the percentage of analog circuits increased in SoC, mixed languages and mixed signal design and verification also became a topic, both in papers and in Tutorials.  In fact one can quickly make a list of the most relevant issues current among electronics engineers by quickly reading the current conference program.

Yatin Trivedi, DVCon General Chair succinctly described the aim of DVCon..  ” DVCon continues to focus on serving the Design and Verification community. DVCon is a conference sponsored by Accellera, in order to promote the adoption of its standards and standards-based methodologies. From the days of exclusive focus on Verilog and VHDL, we have come a long way in including SystemVerilog, SystemC, UPF and UVM. As semiconductor IP became significant to our community of designers and verification engineers, the program has expanded its range of topics. However, our focus remains on design and verification.”

FPGA Prototyping Could Become Mainstream Again

Thursday, February 12th, 2015

Gabe Moretti, Senior Editor

Since the very early days of ASIC design engineers have prototyped their ASIC development using FPGA devices in order to debug and verify the design.  The advantage is that the Device Under Test (DUT) runs at speeds that are much greater than those achievable with traditional simulation and in most cases equal or nearly equal those of the actual device.  This is particularly useful in debugging the product’s  firmware, but it also helps in various hardware situations.

FPGA prototyping is not just a thing of the past, before the introduction of emulators, it is a technique used today by many development teams.  Given the imminent development and introduction o a large number of small systems in the IoT architecture, I expect that there will be even more use of FPGA prototyping.  I asked the input of three representatives of EDA companies to get a better picture of the state of affairs.  One, Zibi Zalewski, General Manger of the Hardware Products Division at Aldec, represents the views of what I consider a middle size vendor, while Troy Scott, Product Marketing Manager at Synopsys represent the view of a large company that has a group dedicated explicitly to supporting FPGA prototyping of ASIC designs.  Frank Schirrmeister, Group Director for Product Marketing of the System Development Suite at Cadence,represents a company that competes for the number one position in the emulation and acceleration tools market.

Due to the length of the resulting article I chose to publish the three contributions as separate articles, and to group them herein my blog to give you, the reader, additional flexibility in covering the topic.

A Historical Approach

Zibi reviewed FPGA prototyping from an historical point of view.  He reminisced about his days as a development engineer and compared the requirement at that time with the development environment available today.  You can read his contribution at:

Using FPGA Prototyping for Faster System Validation

Synopsys has always been focused on the design and development of semiconductor devices since its inception, and has entered the market of FPGA based designs mostly in order to support ASIC prototyping.  You can read what Troy Scott sent me at this address:

A Prototyping with FPGA Approach

Frank Schirrmeister provided a view of prototyping that frames it within the present efforts to decrease development time, the so called “shift left” approach or the recently proposed Agile IC Methodology.  You can read his thoughts here:


Although some may think that FPGA prototyping is a methodology that has seen its prime, the focus on IoT architecture, which use a large number of small, focused, systems, will revive this development method, since, in many cases, companies will be able to avail themselves of a fixed general purpose control subsystem and a function based data acquisition subsystem.  I in fact, envision development systems available fr purchase that offer a control and data analysis standard system and allow designers to include the sensor and circuitry specific to the function to generate a complete FPGA based prototyping environment.