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Archive for March, 2015

Yield Analysis: EDA Black Ops

Wednesday, March 25th, 2015

Gabe Moretti, Senior Editor

During my last trip to San Jose I met with John Kibarian, President and CEO of PDF Solutions.  The company, one of the few EDA company publicly traded on the stock market, is not very visible at conferences.  Yet it performs a vital role in helping the electronics industry to increase profit margins.  It is like PDF Solutions is in charge of black ops.

After our discussion I concluded that more design companies should look to PDF Solutions as a tool to improve their designs, just as they look at DFM and DFY tools from other EDA companies to improve their design quality.

PDF Solution is a provider of yield improvement technologies and services for the IC manufacturing process life cycle. The company offers solutions that are designed to enable clients to lower costs of IC design and manufacture, enhance time to market, and improve profitability by addressing design and manufacturing interactions from product design to initial process ramps to mature manufacturing operations.  Although foundries are their major customers, I think this is a mistake.

Yields depend on many factors, some design related.  Analyzing manufacturing defects can help design teams to identify features that are particularly sensitive to the process technology employed by the foundry.  If a specific area of the die fails more frequently than others, designers should pay particular attention to both the layout and the dynamic functionality of the chip in that neighborhood.

In fact, the company pdBRIX Chip Design Platform provides away to library groups to build libraries with qualified layout patterns that ensure that designs are built in the sweet spot of the process.

Figure 1: Design rules and SPICE models with pdBRIX templates.

Another product that is part of the company yield ramp simulation solution is Circuit Surfer.  This tool works in conjunction with a SPICE engine and uses statistical analysis to predict parametric yield as a function of design and process parameters. It is used to set or optimize device sizes in circuits such as memories, RF and analog blocks, critical paths, or in SSTA flows. Circuit Surfer is also used to determine realistic worst-case corners for timing models.  Again, to me this tool seems like a good product to use during development.

Exensio is the latest tool introduced by PDF Solutions. Inevitably, process complexity continuously increases to keep up with today’s advanced integrated circuits, however, there is an exponentially growing amount of data that needs to be analyzed. Most of today’s yield analysis methodologies and infrastructures are not adequate for finding root cause unless they have ways to effectively process Big Data. Additionally, manufacturing issues can result in high variability and low product yields, causing delays in product launches, as well as reduced revenue and profitability. Using Exensio, foundries and IC manufacturers can provide measurable value and faster time to market to their customers.

My opinion is that the yield analysis process is too unidirectional.  It starts with designers working to improve yield through DFY tools and methods.  But the feedback direction is lacking.  I have never heard a designers tell me that he or she has looked at a design with the intent of identifying a feature that was responsible for lower yields through yield analysis.  I hope that more designers find a way t talk to their foundry and ask about the results they obtain with PDF Solutions and find a way to use the information in the interest of their company.