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Archive for August, 2015

UVM goes to the IEEE

Thursday, August 13th, 2015

Gabe Moretti, Senior Editor

The Accellera Ssytems Initiative has released its UVM 1.2 standard to the IEEE for official standardization as IEEE 1800.2.  Accellera, which changed its name after the merger with the Open SystemC Initiative, has been an incubator for IEEE standards in Electronic Design Automation (EDA) market.

The Universal Verification Methodology (UVM) is providing a common methodology for engineers using SystemVerilog for design verification.  Before the introduction of UVM verification tests and run time environments were created in different manners.  This complicated the work of engineers who had to use different verification tools.  As designs grew in size and geographically dispersed teams began to be used one a single project, the situation became a significant source of errors and longer projects.

Dennis Brophy, Director of Strategic Business Development at Mentor Graphics and an Accellera director, wrote in his blog on the Mentor’s website: “To say we are pleased to see UVM move to the IEEE is an understatement.  We congratulate the Accellera UVM team on its accomplishment and look forward to participate in this phase of UVM’s standardization. Since our first public announcement on May 8, 2006 when we introduced the world to AVM and announced support for it from 19 of our Questa Vanguard Partners, to our announced collaboration with Cadence Design Systems on the development of the Open Verification Methodology (OVM) on August 16, 2007 and the eventual announcement January 8, 2010 that Accellera adopts OVM as the basis of its Universal Verification Methodology, we have guided its development and supported a path for the Big-3 EDA to voice positive public support.  We are thrilled Accellera has announced its delivery of UVM to the IEEE for ongoing standardization and maintenance.”  The “Big-3” mentioned by Dennis are Cadence, Mentor, and Synopsys, the largest companies in term of revenue in the EDA industry.

As can be seen from the above narration, developing a standard is a time consuming enterprise.  It requires not only technical expertise, but political skills as well to satisfy the business requirements of all parties involved in the task.

“This is a significant milestone for Accellera,” stated Shishpal Rawat, Accellera Systems Initiative chair. “We have seen rapid adoption of UVM across the global electronic design verification community. As Accellera transfers the ongoing standardization and maintenance to the IEEE, it will continue to maintain the open-source BCL and keep it current with any changes proposed during the IEEE standardization process.”  Indeed the EDA community has embraced UVM with a rapidity superior to previous standards, a sign that engineers needed such a methodology.

Of course the IEEE will not just rubberstamp what it has received from Accellera.  A working group will be created under the Design Automation Standards Committee (DASC) and issues raised by use of the new methodology in the short time since its release by Accellera will be addressed and if necessary solutions will be incorporated in the IEEE standard.  Whatever the outcome, Accellera will support P1800.2 and will collaborate with the IEEE to maintain the standard until, at most five years from its release, the standard will be eligible for updating.