Gabe Moretti, Senior Editor
The semiconductor and EDA companies are pushed by two at times conflicting needs. On one hand they are in business to make money, on the other they have to pursue technological growth and thus spend resources performing advanced development and research. In the second case pursuing Moore’s law seems to have become an obsession when looked from the business side of a company.
The results in the last couple of years, it is clear that the number of electronics companies that can afford to use 20 and 14 nanometer processes is shrinking, not growing. It is true that users of these processes individually generate more revenue both to EDA companies and to foundries but vendors cannot afford to see their customers base narrow to just a couple of dozens of elite customers. Yet the push toward ever smaller geometries continues.
I spoke with Praveen Raghavan, principal engineer at imec, and Vassilios Gerousis, distinguished engineer at Cadence about the announcement that they had partnered to explore the 5 nm process node.
To be sure 5 nm is a couple of steps beyond the production node used today, so this work can be considered pure research. The companies recently completed the first tapeout of a 5nm test chip using extreme ultraviolet (EUV) as well as 193 immersion (193i) lithography.
To produce this test chip, imec and Cadence optimized design rules, libraries and place-and-route technology to obtain optimal power, performance and area (PPA) scaling via Cadence Innovus Implementation System. Using a processor design, imec and Cadence successfully taped out a set of designs using EUV lithography as well as Self-Aligned Quadruple Patterning (SAQP) for 193i lithography, where metal pitches were scaled from the nominal 32nm pitch down to 24nm to push the limit of patterning.
As can be seen from figure 1 the features are quite regular and give the impression that the goal was more to test manufacturing capabilities than design handling. Vassilios pointed out that to improve a tool one must stress its capabilities, including how it handles new very strict design rules. I am puzzled by the lack of interest on the part of foundries to abandon UV lithography to go to X-ray lithography. The design rules book is getting thicker and ticker and the designers are the ones paying the price for the insistence of foundries to keep UV technology alive. Praveen pointed out that it is important to find the breaking point and that the results of the exercise indicates that UV lithography has yet to run its course.