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Archive for October, 2015

The Race to 5nm

Wednesday, October 28th, 2015

Gabe Moretti, Senior Editor

The semiconductor and EDA companies are pushed by two at times conflicting needs.  On one hand they are in business to make money, on the other they have to pursue technological growth and thus spend resources performing advanced development and research.  In the second case pursuing Moore’s law seems to have become an obsession when looked from the business side of a company.

The results in the last couple of years, it is clear that the number of electronics companies that can afford to use 20 and 14 nanometer processes is shrinking, not growing.  It is true that users of these processes individually generate more revenue both to EDA companies and to foundries but vendors cannot afford to see their customers base narrow to just a couple of dozens of elite customers.  Yet the push toward ever smaller geometries continues.

I spoke with Praveen Raghavan, principal engineer at imec, and Vassilios Gerousis, distinguished engineer at Cadence about the announcement that they had partnered to explore the 5 nm process node.

To be sure 5 nm is a couple of steps beyond the production node used today, so this work can be considered pure research.  The companies recently completed the first tapeout of a 5nm test chip using extreme ultraviolet (EUV) as well as 193 immersion (193i) lithography.

To produce this test chip, imec and Cadence optimized design rules, libraries and place-and-route technology to obtain optimal power, performance and area (PPA) scaling via Cadence Innovus Implementation System. Using a processor design, imec and Cadence successfully taped out a set of designs using EUV lithography as well as Self-Aligned Quadruple Patterning (SAQP) for 193i lithography, where metal pitches were scaled from the nominal 32nm pitch down to 24nm to push the limit of patterning.

Figure 1

As can be seen from figure 1 the features are quite regular and give the impression that the goal was more to test manufacturing capabilities than design handling.  Vassilios pointed out that to improve a tool one must stress its capabilities, including how it handles new very strict design rules.   I am puzzled by the lack of interest on the part of foundries to abandon UV lithography to go to X-ray lithography.  The design rules book is getting thicker and ticker and the designers are the ones paying the price for the insistence of foundries to keep UV technology alive.  Praveen pointed out that it is important to find the breaking point and that the results of the exercise indicates that UV lithography has yet to run its course.

EDAC does Patents

Monday, October 19th, 2015

Gabe Moretti, Senior Editor

Silicon Valley would not be what it is without patents.  The valuation of a company is directly related to the value of its patents.  Yet patents remain a somewhat arcane subject to most engineers.  We know what they are, we know it is nice to have some in one’s resume`, but how to get them and how to protect them remain specialized techniques left to even more specialized layers.

For a few years EDAC has had a patent committee, but I do not think it was well advertised or that it talked to those not directly involved in patents’ matters.  This is about to change.  On Thursday, October 29 at the SEMI Global Headquarters, from 6:00 to 9:00 PM EDAC has organized an event called: Patents and Patent Litigation.  The subtitle of the event reads like something most engineers would be interested in: Develop, Strengthen, and Protect Your Intellectual Property.  To register go to: http://conta.cc/1JyX0O3.  The event is free to EDAC members, others will be accommodated if space is available.

The Mayor of San Jose, Sam Liccardo, and the Director of the Silicon Valley United States Patent Office, John Cabeca, will kick off the event and celebrate the opening of the new Silicon Valley United States Patent Office.

The panelists will discuss how to protect innovation and invention through patent procurement and enforcement. This event is open to all EDAC member companies. Non-EDAC members are welcome to join based on space available.

I am not sure how the Mayor fits in patents litigations, but it still a good venue to meet him if you have not already done so.  Clearly he thinks the event is important and shares the opinion that the subject is vital to retaining and growing the wealth in Silicon Valley.

I do not recognize the name of any of the panelists, but then again I never had to defend a patent.  The panel will be moderated by Salumeh Loesch – Associate at Klarquist Sparkman.  The panelists are: John Cabeca who is the Director of the Silicon Valley US Patent and Trademark Office.  He will be joined by Karna Nisewaner, Associate General Counsel at Cadence, Robert Sachs, Partner with Fenwick & West, and John Vanderberg, Partner with Klarwuist Sparkman.

Synopsys’ Relaunched ARC Is Not The Answer

Wednesday, October 14th, 2015

Gabe Moretti, Senior Editor

During the month of September Synopsys spent considerable marketing resources relaunching its ARC processor family of products by leveraging the IoT.  First on September 10 it published a release announcing two additional versions of the ARC EM family of deeply embedded DSP cores.  Then on September 15 the company held a free one-day ARC Processor Summit in Santa Clara and on September 22 issued another press release about its involvement in IoT again mentioning the embARC Open Software Platform and ARC Access Program.  It is not clear that ARC will fare any better in the market after this effort than it did in the past.

Background

Almost ten years ago a company called ARC International LTD designed and developed a RISC processor called Argonaut RISC Core.  Its architecture has roots in the Super FX chip for the Super Nintendo Entertainment System.  In 2009 Virage Logic purchased ARC International.  Virage specialized in embedded test systems and was acquired by Synopsys in 2010.  This is how Synopsys became the owner of the ARC architecture, although it was just interested in the embedded test technology.

Since that acquisition ARC has seen various developments that produced five product families all within the DesignWare group.  Financial success of the ARC family has been modest, especially when compared within the much more popular product families in the company.  The EM family is one of the five product families where the two new products reside.  During this year’s DVCon, at the beginning of March I had an interview with Joachim Kunkel, Sr. Vice President and General Manager of the Solutions Group at Synopsys who is responsible among other things of the IP products.  We talked about the ARC family and how Synopsys had not yet found a way to efficiently use this core.  We agreed that IoT applications could benefit from such an IP especially if well integrated with other DesignWare pieces and security software.

The Implementation

I think that the ARC family will never play a significant part in Synopsys revenue generation, even after this last marketing effort.

It seems clear to me that the IoT strategy is built on more viable corporate resources than just the ARC processor.  The two new cores are the EM9D and EM11D which implement an enhanced version of the ARCv2DSP instruction set architecture, combining RISC and DSP processing with support for an XY memory system to boost digital signal processing performance while minimizing power consumption.  Synopsys claims that the cores are from 3 to 5 times more efficient than the two previous similar cores, but the press release specifically avoids comparison with similar devices from other vendors.

When I read the data sheets of devices from possible competitors I appreciate the wisdom to avoid direct comparison.  Although the engineering work to produce the two new cores seems quite good, there is only so much that can be done with a ten years old architecture.  ARC becomes valuable only if sold as part of a sub-system that integrates other Synopsys IP and security products owned by the company.

It is also clear that those other resources will generate more revenue for Synopsys when integrated with other DSP processors from ARM, Intel, and may be Apple or even Cadence.  ARC has been neglected for too long to be competitive by itself, especially when considering the IoT market.  ARC is best used at the terminals or data acquisition nodes.  Such nodes are highly specialized, small, and above all very price sensitive.  A variation of few cents makes the difference between adoption or not.  This is not a market Synopsys is comfortable with.  Synopsys prefers to control by offering the best solution at a price it finds acceptable.

Conclusion

The ARC world will remain small.  Synopsys mark on the IoT will possibly be substantial but certainly not because of ARC.

Cadence Introduced Tensilica Vision P5 DSP

Thursday, October 8th, 2015

Gabe Moretti, Senior Editor

DSP devices are indispensable in electronic products that deal with the outside environment.  Wheter one needs to see, to touch, or in any way gather information from the environmanet, DSP devices are critical.  Improvements in their performance characteristics, therefore, have a direct impact not only on the capability of a circuit, but more importantly, on its level of competitiveness.  Cadence Design Systems has just announced the Cadence Tensilica Vision P5 digital signal processor (DSP), which it calls its flagship high-performance vision/imaging DSP core. Cadence claims that the new imaging and vision DSP core offers up to 13X performance boost, with an average of 5X less energy usage on vision tasks compared to the previous generation IVP-EP imaging and video DSP.

Jeff Bier, co-founder and president of Berkeley Design Technology, Inc. (BDTI) noted that: “There is an explosion in vision processing applications that require dedicated, efficient offload processors to handle the large streams of data in real time.  Processor innovations like the Tensilica Vision P5 DSP help provide the backbone required for increasingly complex vision applications.”

The Tensilica Vision P5 DSP core includes a significantly expanded and optimized Instruction Set Architecture (ISA) targeting mobile, automotive advanced driver assistance systems (or ADAS, which includes pedestrian detection, traffic sign recognition, lane tracking, adaptive cruise control, and accident avoidance) and Internet of Things (IoT) vision systems.

“Imaging algorithms are quickly evolving and becoming much more complex – particularly in object detection, tracking and identification,” stated Chris Rowen, CTO of the IP Group at Cadence. “Additionally, we are seeing a lot more integrated systems with multiple sensor types, feeding even more data in for processing in real time. These highly complex systems are driving us to provide more performance in our DSPs than ever before, at even lower power. The Tensilica Vision P5 DSP is a major step forward to meeting tomorrow’s market demands.”
Modern electronic systems architecture threats hardware and software with the same amount of attention.  They must balance each other in order to achieve the best possible execution while minimizing development costs.  The Tensilica Vision P5 DSP further improve the ease of software development and porting, with comprehensive support for integer, fixed-point and floating-point data types and an advanced toolchain with a proven, auto-vectorizing C compiler. The software environment also features complete support of standard OpenCV and OpenVX libraries for fast, high-level migration of existing imaging/vision applications with over 800 library functions.

The Tensilica Vision P5 DSP is specifically designed for applications requiring ultra-high memory and operation parallelism to support complex vision processing at high resolution and high frame rates. As such, it allows off-loading vision and imaging functions from the main CPU to increase throughput and reduce power. End-user applications that can benefit from the DSP’s capabilities include image and video enhancement, stereo and 3D imaging, depth map processing, robotic vision, face detection and authentication, augmented reality, object tracking, object avoidance and advanced noise reduction.

The Tensilica Vision P5 DSP is based on the Cadence Tensilica Xtensa architecture, and combines flexible hardware choices with a library of DSP functions and numerous vision/imaging applications from our established ecosystem partners. It also shares the comprehensive Tensilica partner ecosystem for other applications software, emulation and probes, silicon and services and much more.  The Tensilica Vision P5 core includes these new features:

  • Wide 1024-bit memory interface with SuperGather technology for maximum performance on the complex data patterns of vision processing
  • Up to 4 vector ALU operations per cycle, each with up to 64-way data parallelism
  • Up to 5 instructions issued per cycle from 128-bit wide instruction delivering increased operation parallelism
  • Enhanced 8-,16- and 32-bit ISA tuned for vision/imaging applications
  • Optional 16-way IEEE single-precision vector floating-point processing unit delivering a massive 32GFLOPs at 1GHz

Coventor’s MEMS+ 6.0 Enables MEMS/IoT Integration

Tuesday, October 6th, 2015

Gabe Moretti, Senior Editor

In thinking about the architecture and functioning of the IoT, I came to represent it as a nervous system.  Commands and data flow through the architecture of IoT while computations are performed at the appropriate location in the system.  The end terminal points of IoT, just like in the human nervous system function as the interface with the outside world.  MEMS are indispensable to the proper functioning of the interface, yet, as focused as we are on electronics, we seldom give prominence to MEMS when the IoT is discussed in EDA circles.

Coventor, Inc., a leading supplier of MEMS design automation solutions, introduced MEMS+ 6.0, the latest version of its MEMS design platform.   The tool is available immediately.  MEMS+ 6.0 is a significant advance toward a MEMS design automation flow that complements the well-established CMOS design flow, enabling faster integration of MEMS with electronics and packaging.  MEMS+ 6.0 features new enablement of MEMS process design kits (PDKs) and second-generation model reduction capabilities.

“The fast growing Internet of Things market will increasingly require customization of MEMS sensors and customized package-level integration to achieve lower power, higher performance, smaller form factors, and lower costs,” said Dr. Stephen R. Breit, Vice President of Engineering at Coventor.  “MEMS+6.0 is focused on enabling rapid customization and integration of MEMS while enforcing design rules and technology constraints.”

With MEMS+ 6.0, users can create a technology-defined component library that imposes technology constraints and design rules during design entry, resulting in a “correct-by-construction” methodology. This new approach reduces design errors and enables MEMS foundries to offer MEMS Process Design Kits (PDKs) to fabless MEMS designers. Both parties will benefit, with submitted designs having fewer errors, and ultimately fewer design spins and fab cycles required to bring new and derivative products to market.

“We have collaborated with Coventor in defining the requirements for MEMS PDKs for MEMS+,” said Joerg Doblaski, Director of Design Support at X-FAB Semiconductor Foundries. “We see the new capabilities in MEMS+ 6.0 as a big step toward a robust MEMS design automation flow that will reduce time to market for fabless MEMS developers and their foundry partners.”

MEMS+6.0 also includes a second-generation model reduction capability with export to MathWorks Simulink as well as the Verilog-A format. The resulting reduced-order models (ROMs) simulate nearly as fast as simple hand-crafted models, but are far more accurate. This enables system and IC designers to include accurate, non-linear MEMS device models in their system- and circuit-level simulations. For the second generation, Coventor has greatly simplified the inputs for model reduction and automatically includes the key dynamic and electrostatic non-linear effects present in capacitive motion sensors such as accelerometers and gyroscopes. ROMs can be provided to partners without revealing critical design IP.   Figure 1 shows one such integration architecture.

Figure 1: Integration of MEMS with digital/analog design

Additional advances in MEMS+ 6.0 include:

  • Support for design hierarchy, encouraging time-saving re-use of device sub-structures.
  • Refined support for including packaging effects in thermal stability analysis of sensors, reducing the impact ambient temperature can have on the thermal stability of sensor outputs such as zero offset in accelerometers and drift bias in gyros.
  • Improved modeling of devices that rely on piezo-electric effects for sensing. Interest in piezo sensing is growing because the underlying process technology for piezo materials has matured and the potential benefits over capacitive sensing, the current market champion.
  • An expanded MATLAB scripting interface that now allows design entry as well as simulation control.