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Archive for November, 2015

ARM TechCon, the Aftermath

Monday, November 23rd, 2015

Gabe Moretti, Senior Editor

A couple of weeks ago I attended my first ARM TechCon.  Having spent the first 32 years of my professional life developing EDA tools to support the design and development of leading edge semiconductor devices, I have concentrated my editorial career in following that sector of the EDA industry.  ARM TechCon has been a pleasant surprise.  I came face to face with a totally new segment of EDA, one as interesting as what I have been familiar with.

It is true that my segment of EDA has supported ARM in creating those CPUs and MCUs that make the conference possible.  But that is beside the point.  Here is an industry segment whose customers are builders of systems that very often become the final products, and thus very price sensitive.  They are systems integrators, embedded software developers creating both system and application specific modules.

To be sure there were some EDA vendors on the exhibit floor that one finds at DAC as well.  Cadence, Mentor, and Synopsys were there, and I even knew some of the people at both the Cadence and Mentor booths.  Ansys, Sonics and Kilopass were also exhibiting.  All three serve this market in very direct ways: Ansys is a very diversified company, while both Sonics and especially Kilopass offer products that become parts of an electronic product directly.  Imperas was exhibiting and shared the opinion that the conference was more in tone with their products than DAC is.  I am sure I left some companies who also exhibit at DAC out of this list, but the newness of the topics I was dealing with kept me quite busy and away from the floor.

I spoke with Altium a company I knew for its PCB design tools.  They were showing instead their Tasking products, tools that support the development of embedded systems.  A totally new to me side of the company.

The conference really caters to the “Makers”: that set of developers that use less expensive tools to integrate components in a system.  This is really where IoT becomes real, where you see MEMS on a mini PCB, where mixed signal designs are the norm.  On the exhibit floor you could order a drone, or win a number of development boards supporting ARM based systems ready to help you develop the app that will make you famous and probably rich.

One of the peculiarities of conferences exhibit floors like this one or DAC is that vendors have people, usually attractive young ladies, that ask to swipe your badge as you walk from one booth to another.  In spite of the fact that my badge prominently said that I was with the press, those ladies insisted on swiping my badge and I am too shy to offend them.  And thus, a UPS truck pulled up to the house just a couple of hours ago, and after signing for it, I was handed a package I did not expect.  Inside there was a ST Micro STRM32 F7 Discovery development board.  After getting over the confusion of what I should do with it, I read the directions which were quite simple.  So, maybe I will try to develop the ultimate app, or set the house on fire, whichever comes first.  See, for those of you who do not know, I am a computer scientist, not an electronic engineer, so short circuits are a possibility, not a rarity.

It was good to see DAC exhibitors on the floor of ARM TechCon, hopefully not just because it was the politically correct thing to do, but because they truly are considering Makers to be a viable customer base.

Cadence Introduces Palladium Z1 Enterprise Emulation Platform

Thursday, November 19th, 2015

Gabe Moretti, Senior Editor

One would think that the number of customers for very large and expensive emulation systems is shrinking and thus the motivation to launch new such systems would be small.  Clearly my opinion is not correct.

Earlier this week Cadence Design Systems, Inc. launched the Palladium Z1 emulation platform, which the company calls the industry’s first datacenter-class emulation system.  According to Cadence the new platform delivers up to 5X greater emulation throughput than the previous generation, with an average 2.5X greater workload efficiency. the Palladium Z1 platform executes up to 2304 parallel jobs and scales up to 9.2 billion gates, addressing the growing market requirement for emulation technology that can be efficiently utilized across global design teams to verify increasingly complex systems-on-chip (SoCs) designs.

The Palladium Z1 enterprise emulation platform features a rack-based blade architecture, a 92 percent smaller footprint and 8X better gate density than the Palladium XP II platform according to Frank Schirrmeister, Group Director for Product Marketing, System Development Suite at cadence.  Optimizing the utilization of the emulation resource, Palladium Z1 platform offers a virtual target relocation capability, and payload allocation into available resources at run time, avoiding re-compiles. With its massively parallel processor-based architecture, Palladium Z1 platform offers 4X better user granularity than its nearest competitor according to Frank.

Additional key features and benefits of the Palladium Z1 platform include:

  • Less than one-third the power consumption per emulation cycle of the Palladium XP II platform. This is enabled by an up to 44 percent reduction in power density, an average of 2.5X better system utilization and number of parallel users, 5X better job queue turnaround time, up to 140 million gate per hour compile times on a single workstation, and superior debug depth and upload speeds
  • Full virtualization of the external interfaces using a unique virtual target relocation capability. This enables remote access of fully accurate real world devices as well as virtualized peripherals like Virtual JTAG. Pre-integrated Emulation Development Kits are available for USB and PCI-Express interfaces, providing modeling accuracy, high performance and remote access. Combined with virtualization of the databases using Virtual Verification Machine capabilities, it allows for efficient offline access of emulation runs by multiple users
  • The industry’s highest versatility with over a dozen use models, including In-Circuit Emulation running software loads, Simulation Acceleration that allows hot swapping between simulation and emulation, Dynamic Power Analysis using Cadence Joules RTL power estimation, IEEE 1801 and Si2 CPF based Power Verification, Gate-level acceleration and emulation, and OS bring-up for ARM-based SoCs running at 50X the performance of pure standard emulation
  • Seamless integration within the Cadence System Development Suite. This includes Incisive® verification platform for simulation acceleration, Incisive vManager for verification planning and unified metrics tracking, Indago Debug Analyzer and Embedded Software Apps for advanced hardware/software debug, Accelerated and Assertion-Based Verification IP, Protium FPGA-based prototyping platform with common compiler, and Perspec System Verifier for multi-engine system use-case testing.

“We continue to see customer demand for doubling of available emulation capacity every two years, driven by short project schedules amid growing verification complexity and requirements on quality, hardware-software integration, and power consumption” said Daryn Lau, vice president and general manager, Hardware and System Verification, Cadence. “With Palladium Z1 platform as one of the pillars of the System Development Suite, design teams can finally utilize emulation as a compute resource in the datacenter akin to blade server-based compute farms for simulation, and improve schedules while enabling more verification automation to address the growing impact of verification on end product delivery.”

Arduino or Genuino from Intel

Monday, November 9th, 2015

Gabe Moretti, Senior Editor

Intel unveiled a new product at the Maker Faire in Rome, Italy this October.  It is a board 7×5 centimeters in size developed in collaboration with the Italian company Arduino.   Joshua Walden, senior VP and GM, New Technology Group at Intel made the official announcement.  “At the beginning of 2015 we introduced the Curie CPU a very powerful yet small processor which is perfect for the “maker” community.  The processor will be central to the Genuino boards.”  The board will be marketed in the USA under the name Arduino 101, but will be known in the rest of the world as Genuino 101.

The Maker community is a hardware open source movement established by Massimo Banzi ten years ago.  The community has grown in importance to the point to attract the attention of large companies like Intel.

The board is targeting the education field to allow the easy implementation of prototypes of systems that elaborate data and connect to a local network.  One of the areas that is planned to benefit the most from the new product is the educational program of Physical Computing known as Creative technologies for the Classrooms (CTC) which is at present active in 300 schools worldwide.  The primary objective of Arduino 101 is to establish a new type of instructor that will be able to introduce a new method for teaching technology.  Joshua Walden stated that Intel would like to establish the CTC program worldwide in the coming few years.  The board will be available in the first quarter of 2016 with a suggested price around $30.00.

The idea that IoT will significantly expand revenue for the electronics industry cannot be justified without the influx of creative developers that are already familiar with the requirements of new product development.  This board brings the capability of teaching how to develop a product in the classroom at a very affordable price.  Hands-on teaching provides the experience required to foresee and thus avoid obstacles experienced by developers working on their first project.  For sure the financial aspects of productizing a design will not be learned from the experience opened by the Arduino 101 tool, but acquiring technical experience is still a valid reason to develop and provide Arduino (or Genuino) 101 to schools and private individuals.