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Archive for March, 2016

Custom Compiler Shortens Layout of FinFET Circuits

Wednesday, March 30th, 2016

Gabe Moretti, Senior Editor

Synopsys has made a break from constraints driven layout and introduced a new layout system that, according to the company, allows engineers to work in a visual manner. “Legacy custom design tools have not kept pace with the exponential growth in design complexity,” said Antun Domic, executive vice president and general manager of the Design Group at Synopsys. “In particular, the growing number and complexity of FinFET design rules pose significant challenges for layout designers. Custom Compiler’s innovative assistants enable designers to address the most difficult layout challenges while significantly improving FinFET design productivity.”

The new tool is especially efficient when doing FinFET layout since it allows engineers to stack transistors in a visual manner while at the same time conserving the connectivity, thus saving hours of work.  Developing visually-assisted automation technologies that speed up common design tasks reduces iterations and enables reuse.

Custom Compiler Assistants, pictured in the figure above, are productivity aids that leverage the graphical use model familiar to layout designers while eliminating the need to write complicated code and constraints. With Custom Compiler, routine and repetitive tasks are dealt with automatically without extra setup. Custom Compiler provides four types of assistants: Layout, In-Design, Template and Co-Design.

  • Layout Assistants speed layout with visually-guided automation of placement and routing. The router is ideal for connecting FinFET arrays or large-M factor transistors. It automatically clones connections and creates pin taps. The user simply guides the router with the mouse and it fills in the details automatically. The placer uses a new innovative approach to device placement. It allows the user to make successive refinements, offering placement choices but leaving the layout designer in full control of the results—without requiring any up-front textual constraint entry.
  • In-Design Assistants reduce costly design iterations by catching physical and electrical errors before signoff verification. Custom Compiler includes a built-in design rule checking (DRC) engine, which is extremely fast and can be active all the time. In addition to the DRC engine, electromigration checking, and resistance and capacitance extraction are all natively implemented in Custom Compiler. Custom Compiler’s extraction is based on Synopsys’ StarRC engine.
  • Template Assistants help designers reuse existing know-how by making it easy to apply previous layout decisions to new designs. Template Assistants actually learn from the work done with the Layout Assistant’s placer and router. They intelligently recognize circuits that are similar to ones that were already completed and enable users to apply the same placement and routing pattern as a template to the new circuits. Custom Compiler comes pre-loaded with a set of built-in templates for commonly used circuits, such as current mirrors, level shifters and differential pairs.  Users can add more templates that are developed for their design styles as they are created and verified.
  • Co-Design Assistants combine the IC Compiler place and route system and Custom Compiler into a unified solution for custom and digital implementation. Users can freely move back and forth between Custom Compiler and IC Compiler, using the commands of each to successively refine their designs. With the Co-Design Assistants, IC Compiler users can perform full custom edits to their digital designs at any stage of implementation. Likewise, Custom Compiler users can use IC Compiler to implement digital blocks in their custom designs. The lossless, multi-roundtrip capability of the Co-Design Assistants ensures that all changes are synchronized across both the digital and custom databases.

Although Custom Compiler takes advantage of knowledge developed from existing Synopsys tools, it is not only a new product but a new approach to layout that fits well with FinFET use.  “As the leader in analog/mixed-signal semiconductor IP, our team has been exposed to FinFET related design challenges very early in the foundry process development cycle,” said Joachim Kunkel, executive vice president and general manager of the Solutions Group at Synopsys. “We asked the Custom Compiler development team to focus on improving FinFET layout productivity because we saw large increases in the layout effort across a wide range of IP development projects, from standard cells to high-performance SerDes. Custom Compiler’s Layout Assistants allowed us to implement a novel layout methodology that reduces the time of many layout tasks from hours to minutes.”

Register Automation: A visit with Semifore

Tuesday, March 29th, 2016

Gabe Moretti, Senior Editor

During the just passed DVCon U.S. I met with Richard Weber, CEO of Semifore (www.semifore.com).  When I was asked to meet with him by Jill Jacobs I thought she was introducing a new company.  I was wrong! Semifore was founded in 2006 and is an on-going healthy company that has now decided to be more open to the press.

Semifore is a small company, only seven full time employees, with the mission to develop technology that significantly reduces cost to develop and verify complete control register automation of complex ASIC, SoC, and FPGA-based design.  The company offers an advanced compiler for specification, verification, documentation, and implementation of configuration, status registers and address maps for complex designs.

Semifore is self-funded, profitable, and with a healthy list of customers that include a significant number of tier 1 companies.  It is not presently seeking third party funding, although I have pointed out that further significant expansion of the business will require a significant investment.  I put the company in the “life-style” bucket, a good group whose recent principal alumnus is Denali.

When Richard told me that Semifore had developed its own language, CSRSpec, all sorts of warning bells went off in my head.  Not another language! I was thinking.  What amount of work would be necessary to get it accepted?  It turned out that my fears were unfounded.  The language not only interfaces with industry standard busses, but also reads and writes SystemRDL, IP-XACT, and spreadsheets.  It produces RTL, firmware header files, verification data, and documentation in HTML, Word, FrameMaker, and others.  In other words, it fits seamlessly into a design flow with third party tools.

Figure 1 How CSRCompiler fits in the design flow

The limitations of IP_XACT are main reason for the new language.  Richard described it as “kicking IP_XACT up a notch (or 10)”.  Actually the description is not quite fair since IP_XACT, and IEEE 1685 its natural derivative, is a “Standard for IP-XACT, Standard Structure for Packaging, Integrating and Re-Using IP Within Tool-Flows” does not directly address total register automation.  It is more accurate to say that CSRSpec implements functions as a supplement of the capabilities of IP_XACT.  For sure CSRSpec does a much better job than SystemRDL, a de-facto standard developed by the SPIRIT consortium, whose further development has been ignored by the EDA community.  It is true that within the Accellera System Initiative, a SystemRDL Working Group was formed in 2012, but the group is still seeking members and, to my knowledge, has done no development work so far.

It is clear that niche companies can still find a way to contribute to EDA and in the process generate a respectable revenue stream.  But it takes both ingenuity and dedication.  Before founding Semifore Richard Weber and Jamsheed Agahi worked at Cisco and each have more than twenty years of design and verification experience.  Herb Winsted, VP of business development and Customer Care was a mask designer at AMD and then provided sales support at Cadence, Silicon Valley Research, and Silvar-Lisco.  Rob Callaghan, COO has more than 25 years of experience in the electronic industry, including a stint at Cadence.

ONeSpin Solutions Introduced FormalWorld.org at DVCon

Tuesday, March 8th, 2016

Gabe Moretti, Senior Editor

Formal techniques, especially the use of assertions to describe desired or unwanted behavior is a powerful method not only to verify a design but to specify the design itself before ever writing any development code.

As the technical program was getting under way at DVCon U.S. OneSpin Solutions announced that it was sponsoring a new community focused on formal technologies and tools called FormalWorld.  The community is hosted at www.FormalWorld.org.  “Formal is a key technology in current and future design flows, making electronics reliable,” notes Dr. Raik Brinkmann, OneSpin Solutions’ president and chief executive officer (CEO). “Making it easy to explore and learn about formal, as well as to share experience and research with others, is a key requirement of the community. Therefore, OneSpin is sponsoring FormalWorld.org to help make it an open platform.”

The new site hosts an online community dedicated to advancing the widespread use of formal verification, with the goal to be the complete online resource for the expanding formal verification community.  The site is managed by Jan Kuster, an independent consultant.  OneSpin Solutions provided the initial sponsorship for this site, but will take a hands-off role in its management.

FormalWorld.org is an open and free community. Anyone interested in Formal Verification is invited to post relevant and useful information, or write a blog. Contact Jan with suggestions or ideas at ContactUs@FormalWorld.org.


A desirable FormalWorld

FormalWorld.org offers links to a broad range of information sources and will be updated on a continuous basis. Its monthly newsletter will include recent developments and non-commercial, technical postings related to formal verification. The first edition features links to Jim Hogan’s “Guide to Formal Verification” published in DeepChip.com, a blog post from Gila Logic’s Elchanan Rappaport and links to videos and presentations from the recent Test & Verification (TVS) Verification Futures.

A blog section is open to the formal engineering community to post non-commercial, technical contributed viewpoints and articles. Visitors will find links to current events and news, a research center with instructional videos and presentations, case studies, academic and topical articles, books and training material, along with a listing of products and service providers. In the future, an independently moderated email questions and answers forum will be available.