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Custom Compiler Shortens Layout of FinFET Circuits

Gabe Moretti, Senior Editor

Synopsys has made a break from constraints driven layout and introduced a new layout system that, according to the company, allows engineers to work in a visual manner. “Legacy custom design tools have not kept pace with the exponential growth in design complexity,” said Antun Domic, executive vice president and general manager of the Design Group at Synopsys. “In particular, the growing number and complexity of FinFET design rules pose significant challenges for layout designers. Custom Compiler’s innovative assistants enable designers to address the most difficult layout challenges while significantly improving FinFET design productivity.”

The new tool is especially efficient when doing FinFET layout since it allows engineers to stack transistors in a visual manner while at the same time conserving the connectivity, thus saving hours of work.  Developing visually-assisted automation technologies that speed up common design tasks reduces iterations and enables reuse.

Custom Compiler Assistants, pictured in the figure above, are productivity aids that leverage the graphical use model familiar to layout designers while eliminating the need to write complicated code and constraints. With Custom Compiler, routine and repetitive tasks are dealt with automatically without extra setup. Custom Compiler provides four types of assistants: Layout, In-Design, Template and Co-Design.

  • Layout Assistants speed layout with visually-guided automation of placement and routing. The router is ideal for connecting FinFET arrays or large-M factor transistors. It automatically clones connections and creates pin taps. The user simply guides the router with the mouse and it fills in the details automatically. The placer uses a new innovative approach to device placement. It allows the user to make successive refinements, offering placement choices but leaving the layout designer in full control of the results—without requiring any up-front textual constraint entry.
  • In-Design Assistants reduce costly design iterations by catching physical and electrical errors before signoff verification. Custom Compiler includes a built-in design rule checking (DRC) engine, which is extremely fast and can be active all the time. In addition to the DRC engine, electromigration checking, and resistance and capacitance extraction are all natively implemented in Custom Compiler. Custom Compiler’s extraction is based on Synopsys’ StarRC engine.
  • Template Assistants help designers reuse existing know-how by making it easy to apply previous layout decisions to new designs. Template Assistants actually learn from the work done with the Layout Assistant’s placer and router. They intelligently recognize circuits that are similar to ones that were already completed and enable users to apply the same placement and routing pattern as a template to the new circuits. Custom Compiler comes pre-loaded with a set of built-in templates for commonly used circuits, such as current mirrors, level shifters and differential pairs.  Users can add more templates that are developed for their design styles as they are created and verified.
  • Co-Design Assistants combine the IC Compiler place and route system and Custom Compiler into a unified solution for custom and digital implementation. Users can freely move back and forth between Custom Compiler and IC Compiler, using the commands of each to successively refine their designs. With the Co-Design Assistants, IC Compiler users can perform full custom edits to their digital designs at any stage of implementation. Likewise, Custom Compiler users can use IC Compiler to implement digital blocks in their custom designs. The lossless, multi-roundtrip capability of the Co-Design Assistants ensures that all changes are synchronized across both the digital and custom databases.

Although Custom Compiler takes advantage of knowledge developed from existing Synopsys tools, it is not only a new product but a new approach to layout that fits well with FinFET use.  “As the leader in analog/mixed-signal semiconductor IP, our team has been exposed to FinFET related design challenges very early in the foundry process development cycle,” said Joachim Kunkel, executive vice president and general manager of the Solutions Group at Synopsys. “We asked the Custom Compiler development team to focus on improving FinFET layout productivity because we saw large increases in the layout effort across a wide range of IP development projects, from standard cells to high-performance SerDes. Custom Compiler’s Layout Assistants allowed us to implement a novel layout methodology that reduces the time of many layout tasks from hours to minutes.”

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