Part of the  

Chip Design Magazine


About  |  Contact

Archive for May, 2016

Cadence’s Allegro and Orcad Updates

Tuesday, May 31st, 2016

Gabe Moretti, Senior Editor

At the beginning of May, in time for CDNLive, Cadence announced major upgrades for its Allegro and Orcad products.  The Printed Circuit Board (PCB) sector of our industry gets the second cousin treatment in an industry so focused on silicon products.  Yet PCB play a very important role in system design, one that is almost never recognized by the ESL tools.  I cannot name an ESL tool that allows architects to evaluate the topology of a system on a PCB.  PCB designers are always left with the task of accommodating the electronic system within the mechanical confines of the product.  Naturally this brings about thermal and electrical issues that are not at all considered by the IC designers.

The new versions introduced by Cadence do not attempt to address this problem either, although they have improved the interoperability between Allegro and Sigrity to shorten PCB design and verification time.  Other new capabilities in the Allegro product include:

Rigid-Flex design enhancements, inter-layer checks for both flex and rigid flex, a new native 3D engine, and finally a Programmable Interface with the Sigrity tool.

By looking at the capabilities offered by similar products from Mentor and Zuken, it turns out that Allegro does not offer any capability that is not already present in Mentor ‘s Xploration or Zuken’s CR8000 products.  All three products address the problem of PCB design and verification in different manner, so that a choice among them is a matter of methods more than of capability.

What is interesting within the PCB market is that all three leading vendors have chosen a dual approach.  Cadence with Allegro and OrCAD, Mentor with Xpedition and PADS, and Zuken with the CR family and CADSTAR.  There seems to be a real division among PCB designers that supports such strategy.  OrCAD, PADS, and CADSTAR aim to support the individual designer who works on a less challenging PCB design and whose verification requirements are less demanding.  Allegro, Xpedition, and CR8000 (or CR7000 for that matter) support team design and a verification cycle that deals with power distribution, IR- Drop, noise, and thermal issues among others.

While both Mentor and Zuken address the PCB market by addressing PCB design and verification problems in their own importance, Cadence serves this market as a function of what an IC designer needs from the PCB.  The lack of consideration by Cadence for the role that a PCB plays is system design is therefore more intriguing.  It would seem to me that Cadence would be the one concerned with co-design and co-verification of IC and PCB, but this is not the case at all.  In all three cases the IC, or ICs are taken as given, there is no possibility to tradeoff IC characteristics and a PCB characteristics.  True enough, in most cases the IC is what it is, it comes from a third party, and thus the PCB designer must adapt to a set of characteristics that are unchangeable.  But that is not always the case.  Some ICs come as a family with different electrical specification, and evaluating various flavors of a CPU or MCU should be an easy thing to do.

Unfortunately, PCB designers are mostly ignored by DAC.  Zuken is not even on the exhibitors list this year, so attendees will not get the opportunity to compare products, beside may be Mentor’s and Cadence’s.  I  wrote “may be” because both booths will certainly underscore IC design and there will be a high level of discourse about IoT.  But you need to ask, if you want to find someone on the booth that can demo a PCB product.

ESDA to Host System Scaling Forum

Wednesday, May 4th, 2016

Gabe Moretti

Not too long ago EDAC was a quite consortium that only bothered analysts and journalists by issuing EDA market reports.  Since Bob Smith became its executive director it seems that not one week passes without another press release reaches my inbox.  First there was the name change, from EDAC to ESDA, just a little further down the alphabet.  Then there was a marketing agreement with SEMICO and the appointment of Lucio Lanza to the ESDA board.  Both with the aim to convince IP companies to join ESDA.  The easoning went something like this: ”We serve the same market, so why not collaborate?”

The latest move is to organize a working group on System Scaling.  No one knows what the working group mission is, but why not try something as long as it generates news.  So now ESDA seems to want to compete with Accellera, probably a very bad idea given the overlap of membership between the two organization at the board of directors level.  As usual ESDA did not ask for my advice.  Had they done so I would have told them to explore a working relationship with Accellera.  They have more experience in running successful working groups than most other organizations and ESDA might even gather a few suggestions on how to improve DAC, seen the results DVCon is producing worldwide.

The meeting is scheduled for May 17, from 6 to 8 PM at the impressive sounding ESDA Global Headquarters, 3081 Zanker Road in San Jose.  The evening is free of charge and open to members of the design and manufacturing community interested in system scaling.  Herb Reiter of EDA2ASIC Consulting will conduct the Forum that has been titled “More than Moore –– Enabling the Power of System Scaling”.  I called Herb to find out what “system scaling” is all about.  He told me that 3D and 2.5D Packaging is what he means when he talks about system scaling.  The idea is to package systems in a smaller volume.  The system is scaled to smaller dimensions thus the name.  He has authored a Multi-die IC design Guide of over 300 pages on the subject.  The volume can be downloaded from the site free of charge.  The scope of the forum is to seek community input on direction and priorities for the System Scaling Working Group.

To be sure 3D and 2.5D packaging present a number of challenges to designers and verification engineers.  Place and route, power distribution, signal integrity are all issues found not only with traditional dies, but also on printed circuit boards (PCB).  Are the tools used today to analyze and solve these types of issues sufficient?  Is there human interface adequate?  How can the total system into which these packages are integrated be simulated while still maintaining the identity of each individual die?  I am sure there are more issues than just these, but the issue remains how an organization that has never run a technical working group can be efficient and effective from the start.