ESDA to Host System Scaling Forum
Not too long ago EDAC was a quite consortium that only bothered analysts and journalists by issuing EDA market reports. Since Bob Smith became its executive director it seems that not one week passes without another press release reaches my inbox. First there was the name change, from EDAC to ESDA, just a little further down the alphabet. Then there was a marketing agreement with SEMICO and the appointment of Lucio Lanza to the ESDA board. Both with the aim to convince IP companies to join ESDA. The easoning went something like this: ”We serve the same market, so why not collaborate?”
The latest move is to organize a working group on System Scaling. No one knows what the working group mission is, but why not try something as long as it generates news. So now ESDA seems to want to compete with Accellera, probably a very bad idea given the overlap of membership between the two organization at the board of directors level. As usual ESDA did not ask for my advice. Had they done so I would have told them to explore a working relationship with Accellera. They have more experience in running successful working groups than most other organizations and ESDA might even gather a few suggestions on how to improve DAC, seen the results DVCon is producing worldwide.
The meeting is scheduled for May 17, from 6 to 8 PM at the impressive sounding ESDA Global Headquarters, 3081 Zanker Road in San Jose. The evening is free of charge and open to members of the design and manufacturing community interested in system scaling. Herb Reiter of EDA2ASIC Consulting will conduct the Forum that has been titled “More than Moore –– Enabling the Power of System Scaling”. I called Herb to find out what “system scaling” is all about. He told me that 3D and 2.5D Packaging is what he means when he talks about system scaling. The idea is to package systems in a smaller volume. The system is scaled to smaller dimensions thus the name. He has authored a Multi-die IC design Guide of over 300 pages on the subject. The volume can be downloaded from the eda2asic.com site free of charge. The scope of the forum is to seek community input on direction and priorities for the System Scaling Working Group.
To be sure 3D and 2.5D packaging present a number of challenges to designers and verification engineers. Place and route, power distribution, signal integrity are all issues found not only with traditional dies, but also on printed circuit boards (PCB). Are the tools used today to analyze and solve these types of issues sufficient? Is there human interface adequate? How can the total system into which these packages are integrated be simulated while still maintaining the identity of each individual die? I am sure there are more issues than just these, but the issue remains how an organization that has never run a technical working group can be efficient and effective from the start.