Part of the  

Chip Design Magazine

  Network

About  |  Contact

Archive for August, 2016

ARC Processor summit in Santa Clara

Tuesday, August 30th, 2016

Gabe Moretti, Senior Editor

Synopsys is holding its second ARC Processor summit on September 13 at the Santa Clara Marriott.

The full day conference will open at 9:00 for on-site registration.  Synopsys will provide complimentary parking to attendees.  To see the full program please go to:

http://www.synopsys.com/IP/ProcessorIP/ARCProcessors/Pages/arc-processor-summit-2016.aspx

The ARC processor family comprises a number of versions of the MCU adapted to specific applications as well as a general purpose version.  From my point of view, the ARC processor family offers two major advantages to its customers: the availability of a large and tested IP family directly from Synopsys, and Synopsys leading edge rapport with many foundries, including all the important ones.

The day’s events are divided into three tracks: Hardware, Software, and Embedded Vision.

Linley Gwennap, The Linley Group, will deliver the keynote.  The title is: “IoT Standards Wars: Caught in the Middle?”

Given the number of devices and the differences of applications, it is extremely important to arrive quickly to a set of agreed upon standards that can support this variety and still offer robustness, flexibility and security.

The day will conclude with a demo session and networking opportunity from 5:30 to 7:00.

Accellera Relicenses SystemC Reference Implementation under the Apache 2.0 License

Monday, August 15th, 2016

Gabe Moretti, Senior Editor

SystemC is a subset of the C language.  The C language is widely used by software developers.  The SysremC subset contains the features of C that are synthesizable, that is, they are useful to describe hardware components and designs.  SystemC is used mainly by designers working at the system level, especially when it is necessary to simulate both hardware and software concurrently.  An algorithmic description in SystemC of a hardware block generally simulates faster than the same description implemented in a traditional hardware description language.

Accellera Systems Initiative (Accellera), the electronics industry organization focused on the creation and adoption of electronic design automation (EDA) and intellectual property (IP) standards, just announced that all SystemC supplemental material, including material contributed under the SystemC Open Source License Agreement prior to the merger of the Open SystemC Initiative (OSCI) and Accellera in 2011, has now been re-licensed under the Apache License, version 2.0.

The SystemC Open Source License used for the supplemental material required a lengthier contribution process that will no longer be necessary under Apache 2.0. Other Accellera supplemental material already available under Apache 2.0 includes the Universal Verification Methodology (UVM) base class library.

“This is a significant milestone for Accellera and the SystemC community,” stated Shishpal Rawat, Accellera Systems Initiative chair. “Having all SystemC supplemental material, such as proof-of-concept and reference implementations, user guides and examples, under the widely used and industry-preferred Apache 2.0 license will make it easier for companies to more readily contribute further improvements to the supplemental material.  We have been working with all of the contributing companies over the past 18 months to ensure that we could offer SystemC users a clear path to use and improve the SystemC supplemental material, and we are very proud of the efforts of our team to make this happen.”

The supplemental material forms the basis for possible future revisions of the standard as new methods and possible extensions to the language are adopted by a significant majority of users.  It is important to keep in mind that a modeling language is a “living” language, which means that it is subject to periodic changes.  For example, the IEEE specifies that an EDA modeling language standard be reaffirmed every five years.  This institutionalizes the possibility of a new version of the standard at regular intervals.

Hardware Based Security

Friday, August 5th, 2016

Gabe Moretti, Senior Editor

If there is one thing that is obvious about the IoT market it is that security is essential.  IoT applications will be, if they are not already, invasive to the life of their users and the privacy of each individual must be preserved.  The European Union has stricter privacy laws than the US, but even in the US privacy is valued and protective.

Intrinsic-ID has published a white paper “SRAM PUF: The Secure Silicon Fingerprint” that you can read in the Whitepapers section of this emag, or you can go to www.intrinsic-id.com and read it under the “Papers” pull down.

For many years, silicon Physical Unclonable Functions (PUFs) have been seen as a promising and innovative security technology that was making steady progress. Today, Static Random-Access Memory (SRAM)-based PUFs offer a mature and viable security component that is achieving widespread adoption in commercial products. They are found in devices ranging from tiny sensors and microcontrollers to high performance Field-Programmable Gate Arrays (FPGAs) and secure elements where they protect financial transactions, user privacy, and military secrets.

Intrinsic-ID goal in publishing this paper is to show that SRAM PUF is a mature technology for embedded authentication. The behavior of an SRAM cell depends on the difference of the threshold voltages of its transistors. Even the smallest differences will be amplified and push the SRAM cell into one of two stable states. Its PUF behavior is therefore much more stable than the underlying threshold voltages, making it the most straightforward and most stable way to use the threshold voltages to build an identifier.

It turns out that every SRAM cell has its own preferred state every time the SRAM is powered resulting from the random differences in the threshold voltages. This preference is independent from the preference of the neighboring cells and independent of the location of the cell on the chip or on the wafer.

Hence an SRAM region yields a unique and random pattern of 0’s and 1’s. This pattern can be called an SRAM fingerprint since it is unique per SRAM and hence per chip. It can be used as a PUF. Keys that are derived from the SRAM PUF are not stored ‘on the chip’ but they are extracted ‘from the chip’, only when they are needed. In that way they are only present in the chip during a very short time window. When the SRAM is not powered there is no key present on the chip making the solution very secure.

Intrinsic-ID has bundled error correction, randomness extraction, security countermeasures and anti-aging techniques into a product called Quiddikey. This product extracts cryptographic keys from the SRAM PUF in a very secure manner and is available as Hardware IP (netlist), firmware (ANSI C Code), or a combination of these.

The hardware IP is small and fast – around 15K gates / 100K cycles – and connects to common interconnects like AMBA AHB, APB as well as proprietary interfaces. A Built-In Self-Test (BIST) and health checks are included in the logic. Since it is pure digital, single clock logic it synthesizes readily to any technology.  Software reference implementations start from 10KB of code and are available for major platforms like ARM, ARC, Intel and MIPS. Software implementations can be used to add PUF technology to existing products by a firmware upgrade.

I will deal with security issues in more depth in September.  In the mean time the Intrisic-ID white paper is worth your attention