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Archive for September, 2016

eSilicon Fully Automates Semiconductor IP Selection and Purchasing

Wednesday, September 21st, 2016

Gabe Moretti, Senior Editor

Approximately half of the area of advanced system-on-chip (SoC) designs is composed of memory IP. Optimizing the memory subsystem of an SoC requires exploration of hundreds to thousands of possible configurations to identify the optimal match for the chip’s power, performance and area (PPA) requirements. This process can take weeks and traditionally designers and architects have not been able to fully explore all the options available to them, resulting in sub-optimal memory architectures and design closure challenges.

eSilicon’s STAR Navigator tool addresses this challenge by allowing designers to choose, evaluate and procure eSilicon IP online. Now, designers can access a wide variety of memory and I/O options online to find the best configuration for each design. With the latest enhancements to STAR Navigator, designers can now get quotes for their chosen IP online and procure it by uploading a valid purchase order. Designers are now in control of specifying and purchasing the most appropriate IP for their projects.

STAR Navigator increases security of the transactions by providing one channel of communication that allows engineering, purchasing and finance to avoid misunderstandings.  BY eliminating multiple emails to different recipients, the progress of the choice of IP and its purchasing and delivery are all documented in one channel of communication.

Previously, purchasing memory IP and I/Os could be difficult to manage by the engineer. Accessing specific memory instances with a variety of options was time consuming and complex. STAR Navigator helps designers avoid complicated paperwork; find which memories will best help meet their SoC’s power, performance or area (PPA) targets; and easily isolate key data without navigating convoluted data sheets. Pre-loaded data is available to enable architects and designers to obtain immediate PPA information for their early chip planning.

STAR Navigator empowers chip architects and designers to choose the best and highly differentiated eSilicon-developed IP solutions by performing the following tasks online:

  • Generate dynamic, graphical analyses of PPA data
  • View data graphically, view in table format, or download to Microsoft Excel
  • Build and download a complete SoC memory subsystem
    • Generate and download IP front-end views
    • Make changes over time
    • Purchase the IP that best meets the needs of the design

STAR Navigator contains all eSilicon-developed IP across multiple foundries and technologies:

  • Standard and specialty memory compilers from 14nm to 180nm including CAMs, fast cache single-port SRAMs, multi-port register files, ultra-low-voltage SRAMs and pseudo two-port architectures targeted for specific market segments
  • General-purpose and specialty I/O libraries from 14nm to 180nm
  • High-bandwidth memory (HBM) Gen2 PHY in 14/16nm and 28nm
  • Foundries include Dongbu, GLOBALFOUNDRIES, LFoundry, Samsung, SMIC, TSMC and UMC

“STAR Navigator simplifies the comparison of results across multiple technologies, architectures and other characteristics and takes the guesswork out of hitting PPA targets,” said Lisa Minwell, eSilicon’s senior director, IP marketing. “This goes much, much deeper than IP portals that serve as IP catalogs. Using STAR Navigator, designers can download front-end views, run simulations in their own environments and then purchase the back-end views of the IP and I/Os that best fit their design. The choice of optimized IP is now in the hands of the designer.”

An interesting White Paper from S2C

Tuesday, September 6th, 2016

Gabe Moretti, Senior Editor

S2C has published a white paper on Chip Design with the title: “Choosing the best pin multiplexing method for your Multiple-FPGA partition”.  It is of particular interest to designers that use FPGA based prototyping in their development of SoC designs.

Using multiple FPGAs to prototype a large design requires solving a classic problem: the number of signals that must pass between devices is greater than the number of I/O’s pins on an FPGA. The classic solution is to use a TDM (Time Domain Multiplexing) scheme that multiplexes two or more signals over a single wire or pin.

There are two distinct types of TDM implementations: synchronous and asynchronous. In synchronous TDM the multiplexing circuitry is driven by a fast clock that is synchronous with the (user’s) design clock.

In asynchronous mode, the TDM fast clock runs completely independent of the design clocks. Although asynchronous mode is slower, it supports multiple clocks and the timing constraints are easier to meet.

The paper shows that S2C’s Prodigy Play Pro is a tool that provides design partitioning across multiple FPGAs, and offers automatic TDM insertion based on an asynchronous TDM using LVDS.   Prodigy Play Pro Combines the technique of using asynchronous LVDS TDM with a single clock cycle design, and can partition a design and perform automatic TDM insertion. The result is that the tool is able to:

1)   Optimize buses and match the LVDS resources in each bank considering such factors as trace lengths, matching impedances, and impedance continuity, and

2)   Avoid consuming FPGA design resources for the TDM circuity by taking advantage of built-in reference clocks (e.g.: IODELAY) to drive TDM clocks and resets.

Just click on the title of the white paper to read it in its entirety or go to http://www.s2cinc.com/resource-library/white-papers.