Gabe Moretti, Senior Editor
The DVCon conference has now solid traditions not only in the USA but also in Europe, India, and next year will start flowering in China.
The conference will be held February 27 – March 2, 2017 at the DoubleTree in San Jose, California. Early registration was open and the program is available on line at https://dvcon.org. “DVCon U.S. 2017 planning is taking shape,” commented Dennis Brophy, DVCon U.S. General Chair. “We look forward to a compelling and in-depth technical program full of engaging content that practicing design and verification engineers, managers and EDA tool suppliers have come to depend on from DVCon.” The four-day program offers attendees an Expo, two exciting standards-focused panels and numerous informative papers, tutorials and posters to choose from. Accellera Day starts the conference on Monday and will devote the entire morning to a tutorial on Accellera’s emerging Portable Stimulus standard titled “Creating Portable Stimulus Models with the Upcoming Accellera Standard,” with two afternoon tutorials: “SystemC Design and Verification – Solidifying the Abstraction above RTL” and “Introducing IEEE P1800.2 – The Next Step for UVM.”
This important technical event in India was held in Bangalore in September with almost 440 attendees over the two-day event. There were local start-ups participating and exhibiting for the first time, further demonstrating the local focus and interest in each conference. “DVCon India rightly promotes the four C’s: connect, contribute, collaborate, and celebrate,” stated Gaurav Jalan, DVCon India General Chair. The two-day event was inaugurated with a traditional lamp-lighting ceremony and welcome remarks by Jalan. Dr. Walden Rhines, Chairman and CEO of Mentor Graphics, and Professor Kamakoti Veezhinathan, Indian Institute of Technology Madras, delivered the keynotes.
As in previous years the conference was held in Munich, Germany. Held in October it enjoyed an increase in attendance of 20% over the previous year. Attendees of the two-day conference included representatives from 93 companies and organizations from 25 countries. Insightful keynotes were delivered by Hobson Bullman, General Manager of ARM’s Technology Services Group, and Jugen Weyer, Vice President of Automotive Sales for EMEA at NXP Semiconductors. Bob Smith, Executive Director of the ESD Alliance, gave the keynote at the gala dinner. “It’s fantastic to see this event continuing to do so well, meeting a clear need for a European forum that provides practical, detailed information on state-of-the-art development methodologies,” noted Oliver Bell, DVCon Europe General Chair. “This year’s conference was particularly exciting with three dynamic keynote speeches, overwhelming tutorial and paper submissions, and a vibrant exhibition. Now that DVCon Europe is established as the must-attend event in Europefor engineers to upgrade their skills, we are looking forward to an even larger event in 2017.”
During 2017 DVCon will premier as a one-day event in Shanghai on April 17, 2017. The steering committee is in the process of analyzing a number of excellent paper abstract submissions for its inaugural program.. “Ideas, networking, technical discussions, learning opportunities and exciting exhibits of new products and services. This is what DVCon China will offer to attendees,” stated Andy Liu Hongliang, DVCon China General Chair. “Many hot areas of ASIC design and verification such as UVM, Low Power, IP Reuse, Formal, Mixed-Signal, System Design and Debug Strategies will be distributed throughout the whole conference with lectures, discussions, presentations and demos.”