Part of the  

Chip Design Magazine


About  |  Contact

Archive for April, 2017

ESDA CEO Outlook Panel, not a Cause for Celebration

Tuesday, April 25th, 2017

Gabe Moretti, Senior Editor

About two weeks ago the ESD Alliance held its 2017 CEO Outlook Panel.  The panel used to be a yearly event for EDAC, the precursor of the ESD Alliance, but had not been held for a few years since.

I did not have the opportunity to attend the panel in person and was looking forward to read the entire transcript on the ESDA site.  But there is no transcript.  There is a picture of the panelists with Ed Sperling as the moderator, and a brief video showing introductory remarks from each of the panelists.

Unfortunately, the introductory remarks could have been delivered by a set of industry cheerleaders, since there was really no depth in them.  You can guess the contents: greater need for silicon, IoT and IIoT (Industrial IoT) are the future.  Lip-Bu Tan did say something interesting by addressing data architecture within the IIoT.  Too many articles have been written about the IoT hardware architecture and I have found almost nothing that talks about the data architecture.  Lip-Bu emphasized the need for local computational and decision making capability, thus limiting the need to transfer large amount of data up in the hierarchy of the system.  Given the complex connectivity of a IoT system, where everything is potentially connected to everything else, security would be a major concern should the need to transfer a large amount of information arise.  The smaller the amount of data transfer, the higher the security.

What Lip-Bu did not say, but is implied, is the need for distributed intelligence in the system with application specific hardware playing a greater role.  It is back to the future.  ASIC once again will step to the forefront replacing software based system running on general purpose hardware.

Wally Rhines noted that our industry economics are back at the levels of six years ago in spite of the significant consolidation of our customer base.  It is called recovery, and our industry has had less of a recovery than most other industries.

The consolidation issue points out the real problem of the EDA industry.  We sell tools used in the design and development of a product, not its manufacturing.  Manufacturing volume means nothing to the EDA bottom line.  Fewer “makers” means fewer “tools needed”.

Mentor is now part of one of its customers, so does such consolidation matter to Wally?  I hear of course that Mentor will continue to do business in an independent manner, and that will be true unless and until a conflict of interest ensues.  Will Mentor sell its best tools to companies directly competing with Siemens in a specific, competitive, market?

Simon Segers of ARM was also part of the panel.  If he said something important as a result of now working for SoftBank, you could not have guessed it from his introductory remarks either.  He just repeated Aart De Geus observation about the world needing more silicon.  It has been clear since the acquisition that SoftBank other captive industries need more silicon and more IP cores, the reason for the acquisition!  ARM will expertly create whatever SoftBank needs and will market what it creates to the outside world.  The other way around will not happen, at least not in any important way.

Speaking as the scientist that he is Aart pointed out that as algorithms’ complexity increases the need for computational capability increases as well, thus the need for more silicon.  It is an assumption that increased silicon production means increased EDA revenue.  This is a fallacy, since EDA revenues are realized at the front end of the project and do not grow with product volume!  The amount of EDA products that are used in wafer production and testing is small in comparison to the tools used to design and test before production.

There is also a significant difference in the revenue generated by different types of silicon.  A 90 nm device requires less up-front investment in tools than a 10nm device.  And there will be much more of the former than the latter type.

I think that reviving the CEO Panel is a good thing.  It shows, at least, that accepted leaders of the EDA industry are willing to appear in public and deliver statements without fear of sounding irrelevant.  And the lack of a full transcript, given the high level of professionalism now in the ESDA, must mean that nothing worthy of greater analysis was said during the panel.

Cadence Builds a Winged Horse for Verification

Monday, April 17th, 2017

Gabe Moretti, Senior Editor

Cadence reached back into Greek mythology to name its new Verification engine for digital designs: Pegasus.  The hope is, of course, that the new product will prove itself more than a popular myth, but that the product will soar to new heights in efficiency.

The company describes Pegasus as: “a massively parallel, cloud-ready physical verification signoff solution that enables engineers to deliver advanced-node ICs to market faster. The new solution is part of the full-flow Cadence® digital design and signoff suite and provides up to 10X faster design rule check (DRC) performance on hundreds of CPUs while also reducing turnaround time from days to hours versus the previous-generation Cadence solution.”

The major benefits offered by Pegasus, according to Dr. Anirudh Devgan, executive vice president and general manager of the Digital & Signoff Group and the System & Verification Group at Cadence are:

  • Massively parallel architecture: The solution incorporates a massively parallel architecture that provides unprecedented speed and capacity, enabling designers to easily run on hundreds of CPUs to speed up tapeout times.
  • Reduced full-chip physical verification runtimes: The solution’s gigascale processing offers near-linear scalability that has been demonstrated on up to 960 CPUs, allowing customers to dramatically reduce DRC signoff runtimes.
  • Low transition cost: Using existing foundry-certified rule decks, customers achieve 100 percent accurate results with a minimal learning curve.
  • Flexible cloud-ready platform: The solution offers native cloud support that provides an elastic and flexible compute environment for customers facing aggressive time-to-market deadlines.
  • Efficient use of CPU resources: The solution’s data flow architecture enables customers to optimize CPU usage, regardless of machine configurations and physical location, providing maximum flexibility to run on a wide range of hardware, achieving the fastest DRC signoff.
  • Native compatibility with Cadence digital and custom design flows: The Pegasus Verification System integrates seamlessly with the Virtuoso custom design platform, delivering instantaneous DRC signoff checks to guide designers to a correct-by-construction flow that improves layout productivity. An integration with the Innovus Implementation System enables customers to run the Pegasus Verification System during multiple stages of the flow for a wide range of checks—signoff DRC and multi-patterning decomposition, color-balancing to improve yield, timing-aware metal fill to reduce timing closure iterations, incremental DRC and metal fill during engineering change orders (ECOs) that improve turnaround time, and full-chip DRC.

Anirudh concluded that: “The Pegasus Verification System’s innovative architecture and native cloud-ready processing provides an elastic and flexible computing environment, which can enable our customers to complete full-chip signoff DRC on advanced-node designs in a matter of hours, speeding time to market.”

Industrial IoT, a Silicon Valley Opportunity

Tuesday, April 11th, 2017

Gabe Moretti, Senior Editor

I read a white paper written by Brian Derrick, VP of Corporate Marketing at Mentor titled Industrial IoT (IIOT) – Where Is Silicon Valley?  It is an interesting discussion about the IIoT market pointing out that most of the leading companies in the market are not located in Silicon Valley.  In fact Brian only lists Applied Material as having a measurable market share in IIoT (1.4% in 2015), HP and Avago as sensors providers.  Amazon and Google are listed as Cloud Service Providers, Cisco, ProSoft, and Cal Amp as Intelligent Gateway Providers and Sierra Wireless as Machine to Machine Communication Hardware supplier.

It does not make sense to list EDA companies in the valley that supply the tools used by many of the IIoT vendors to design their products.  Unfortunately, it is the service nature of EDA that allows analysts to overlook the significant contribution of our industry to the electronics market place.

There is actually a company in Silicon Valley that in my opinion offers a good example of what IIoT is: eSilicon.  The company started as a traditional IP provider but in the last three years it developed itself into a turn-key supplier supporting a customer from design to manufacturing of IC with integrated analysis tools, and order, billing and WIP reports, all integrated in a system it calls STAR.

A customer can submit a design that uses a eSilicon IP, analyze physical characteristics of the design, choose a foundry, receive a quote, place an order, evaluate first silicon, and go into production all in the STAR system.  This combines design, analysis, ordering, billing, and manufacturing operations, significantly increasing reliability through integration.  The development chain that usually requires dealing with many corporate contributors and often more than one accounting system, has been simplified through integration not just of engineering software tools, but accounting tools as well.

I think that we will regret the use of the term “Internet” when describing communication capabilities between and among “Things”.  Internet is not just hardware, it is a protocol.  A significant amount of communication in the IoT architecture takes place using Bluetooth and WiFi hardware and software, not internet.  In fact, I venture that soon we might find that the internet protocol s the wrong protocol to use.  We need networks that can be switched from public to private, and in fact an entire hierarchy of connectivity that offer better security, faster communication, and flexibility of protocol utilization.

I find that the distinction between real time and batch processing is disappearing because people are too used to real time.  But real time connectivity is open to more security breaches than batch processing.  On the manor, for example, a machine can perform thousands of operations without being connected to the internet all the time.  Status reports, production statistics information, for example, can be collected at specific times and only at those times does the machine need to be connected to the internet.  For the machine to continuously say that all is normal to a central control unit is redundant.  All we should care is if something is not normal.

The bottom line is that there are many opportunities for Silicon Valley corporations to become a participant to IIoT, and, of course, start-ups, a specialty of the Valley, can find a niche in the market.