Part of the  

Chip Design Magazine

  Network

About  |  Contact

Cadence Builds a Winged Horse for Verification

Gabe Moretti, Senior Editor

Cadence reached back into Greek mythology to name its new Verification engine for digital designs: Pegasus.  The hope is, of course, that the new product will prove itself more than a popular myth, but that the product will soar to new heights in efficiency.

The company describes Pegasus as: “a massively parallel, cloud-ready physical verification signoff solution that enables engineers to deliver advanced-node ICs to market faster. The new solution is part of the full-flow Cadence® digital design and signoff suite and provides up to 10X faster design rule check (DRC) performance on hundreds of CPUs while also reducing turnaround time from days to hours versus the previous-generation Cadence solution.”

The major benefits offered by Pegasus, according to Dr. Anirudh Devgan, executive vice president and general manager of the Digital & Signoff Group and the System & Verification Group at Cadence are:

  • Massively parallel architecture: The solution incorporates a massively parallel architecture that provides unprecedented speed and capacity, enabling designers to easily run on hundreds of CPUs to speed up tapeout times.
  • Reduced full-chip physical verification runtimes: The solution’s gigascale processing offers near-linear scalability that has been demonstrated on up to 960 CPUs, allowing customers to dramatically reduce DRC signoff runtimes.
  • Low transition cost: Using existing foundry-certified rule decks, customers achieve 100 percent accurate results with a minimal learning curve.
  • Flexible cloud-ready platform: The solution offers native cloud support that provides an elastic and flexible compute environment for customers facing aggressive time-to-market deadlines.
  • Efficient use of CPU resources: The solution’s data flow architecture enables customers to optimize CPU usage, regardless of machine configurations and physical location, providing maximum flexibility to run on a wide range of hardware, achieving the fastest DRC signoff.
  • Native compatibility with Cadence digital and custom design flows: The Pegasus Verification System integrates seamlessly with the Virtuoso custom design platform, delivering instantaneous DRC signoff checks to guide designers to a correct-by-construction flow that improves layout productivity. An integration with the Innovus Implementation System enables customers to run the Pegasus Verification System during multiple stages of the flow for a wide range of checks—signoff DRC and multi-patterning decomposition, color-balancing to improve yield, timing-aware metal fill to reduce timing closure iterations, incremental DRC and metal fill during engineering change orders (ECOs) that improve turnaround time, and full-chip DRC.

Anirudh concluded that: “The Pegasus Verification System’s innovative architecture and native cloud-ready processing provides an elastic and flexible computing environment, which can enable our customers to complete full-chip signoff DRC on advanced-node designs in a matter of hours, speeding time to market.”

Leave a Reply