Part of the  

Chip Design Magazine


About  |  Contact

Archive for May, 2017

Gallium Nitride for Power Applications

Monday, May 15th, 2017

Gabe Moretti, Senior Editor

Gallium nitride (GaN) has long been used in LED devices and other optoelectronic devices with high power and high frequency requirements.  It can work at much higher temperatures and voltages than gallium arsenide (GaAs) for example and thus it is also used in military and space applications.

A few days ago X-FAB and Exagan announced that they have produced GaN-on-Silicon devices on 200-mm wafers.

X-FAB, whose headquarter is in Germany, is a leading analog/mixed-signal and MEMS foundry group manufacturing silicon wafers for automotive, industrial, consumer, medical and other applications.  The company operates one fab in the USA, specifically in Lubbock Texas where it fabricates mixed-signal devices.  It also operates other fabs both in Europe and in Asia.

Founded in 2014 with support from CEA-Leti and Soitec, Exagan is based in Grenoble, France.  its mission is to accelerate the power electronics industry’s transition from silicon-based technology to GaN-on-silicon technology, enabling smaller and more efficient electrical converters.

The two companies have demonstrated mass-production capability to manufacture highly efficient high-voltage power devices on 200-mm GaN-on-silicon wafers using X-FAB’s standard CMOS production facility in Dresden, Germany.

Exagan and X-FAB have successfully resolved many of the challenges related to material stress, defectivity and process integration while using standard fabrication equipment and process recipes. Combined with the use of 200-mm wafers, this will significantly lower the cost of mass producing GaN-on-silicon devices. By enabling greater power integration than silicon ICs, GaN devices can improve the efficiency and reduce the cost of electrical converters, which will accelerate their adoption in applications including electrical vehicle charging stations, servers, automobiles and industrial systems.

The industry’s previous work with GaN had been limited to 100-mm and 150-mm wafers due to the challenges of layering GaN films on silicon substrates. Exagan’s G-Stack technology enables GaN-on-silicon devices to be manufactured more cost effectively on 200-mm substrates by depositing a unique stack of GaN and strain-management layers that relieves the stress between GaN and silicon layers. The resulting devices have been shown to exhibit high breakdown voltage, low vertical leakage and high-temperature operation.

The new GaN-on-silicon devices have been built using substrates fabricated at Exagan’s 200- mm epi-manufacturing facility in Grenoble, France. These epi wafers meet the physical and electrical specifications to produce Exagan’s 650-volt G-FET devices as well as the tight requirements for compatibility with CMOS manufacturing lines.

IP Fingerprinting Initiative from the ESD Alliance

Thursday, May 11th, 2017

Gabe Moretti, Senior Editor

I had occasion to discuss with Bob Smith, Executive Director of the ESD Alliance, and Warren Savage, General Manager IP at Silvaco, my March article “Determining a Fair Royalty Value for IP” ( as we addressed the IP Fingerprinting Initiative of the ESD Alliance.

I stated that there really was not a standard way to determine the amount of royalty that could be charged for an IP.

Bob Smith responded: “Royalties should be based on value provided. Value comes in many forms, such as how much of the functionality of the end product is provided by the IP, the risk and time-to-market reduction, and design and verification cost savings. There is no simple formula for IP royalties. In fact, they can be quite complicated.”

Warren added: “Business models used for licensing royalties are always a negotiation between the buyer and seller with each party striving to optimize the best outcome for their business. In some cases, the customer may be willing to pay more for royalties in exchange for lowering the upfront licensing costs. A different customer may be willing to invest more upfront to drive down the cost of royalties. Calculation of the actual royalty amounts may be based on a percentage of the unit cost or a fixed price, and each may have sliding scales based on cumulative volumes. Both parties need to derive the value that fits their own business model. The IP user needs to arrive at a price for the IP that supports the ROI model for the end product. The IP supplier needs to ensure that it receives sufficient value to offset its investment in IP development, verification and support. It is able then to participate in the success of the buyer’s product based (at least in part) on the value of the IP provided.”

Since it seems impossible to have a standard function to determine royalties, is there an intrinsic value for an IP?

Warren remarked: “An IP has zero intrinsic value in of itself. The value is completely dependent on the application in which it is used, the ability of the IP to offset development costs and risks and the contributions it makes to the operation and success of the target product. For example, an IP that is developed and ends up sitting on the shelf has no value at all. In fact, its value is negative given the resources and costs spent on developing it. Size doesn’t matter. An IP that has hundreds of thousands of gates may command a higher price because the IP supplier needs to sell it for that price to recoup its investment in creating it.  A small IP block may also command a high price because it may contain technology that is extremely valuable to the customer’s product and differentiates it significantly from the competition. The best way to think about intrinsic value is to think of it in the context of value delivered to the customer. If there is no apparent difference in this regard between an IP product from two or more suppliers, then the marketplace sets the price and the lowest cost supplier wins.”

In terms of the IP Fingerprinting Initiative of the ESD Alliance, I was curious to understand how the owner of the IP could protect against illegal uses.

Warren said: “This is the great problem we have in the IP industry today. Approximately 99% percent of IP is delivered to customers in source code form and IP companies rely on the good faith of their customers to use it within the scope of the license agreement. However, there is a fundamental problem. Engineers rarely know what the usage terms and restrictions of the agreement their company has with the IP supplier, so it is quite easy for a semiconductor company to be in violation, and not even know it. New technologies are coming into play, such as the IP fingerprinting scheme that the ESD Alliance is promoting. Fingerprinting is a non-invasive approach that protects both IP suppliers and their customers from “accidental reuse.”

Bob Smith added: “IP suppliers can utilize The Core Store ( at no charge to showcase their products and register “fingerprints” of their technology. Semiconductor companies can use this registry to detect IP usage within their chips by means of “DNA analysis” software available through Silvaco.”

Memory Subsystem Solutions Announced

Tuesday, May 9th, 2017

Gabe Moretti, Senior Editor

Integrating a Network on Chip (NoC) with a memory controller provides increased system throughput by decreasing the latency of data transfer to and from local storage.  Sonics, Inc. and Northwest Logic have announced their partnership to deliver high throughput memory subsystem solutions for complex System-On-Chip (SOC) designs.  The subsystem is focused on SOC Designs for Machine Learning, Computer Vision, UHD Video Processing, and Enterprise SSD Applications.   The companies’ partnership, which is being driven by a mutual customer SOC design win, integrates Sonics’ flagship interconnect fabric, SonicsGN NoC, and Sonics’ MemMax memory scheduler with Northwest Logic’s family of HBM2, DDRx, LPDDRx memory controllers.

“As DRAM data rates increase, the number of pipelined outstanding transactions required to achieve full throughput grows dramatically,” said Drew Wingard, CTO of Sonics. “This requires more intelligent transaction scheduling that considers both the bandwidth and latency requirements of pending requests and the page and bank states of DRAM. Without careful coordination between the NoC, memory scheduler, and memory controller, the subsystem will miss data transfer deadlines and suffer performance degradation at several points along the memory subsystem transaction path. Our partnership with Northwest Logic ensures that MemMax’s scheduling decisions produce a transaction stream enabling Northwest Logic’s controllers to efficiently map into memory commands that fully leverage the customer’s chosen DRAM technology.”

“Northwest Logic and Sonics share an uncompromising commitment to customer success,” said Brian Daellenbach, President of Northwest Logic. “We are seeing a significant uptick in demand for high throughput memory subsystems that address data-intensive applications and markets such as Machine Learning, Computer Vision, UHD Video Processing, and Enterprise SSD. Our memory controllers have a strong industry reputation for delivering high-performance, high quality, and ease-of-use. Our partnership with Sonics enables us to provide our mutual customers with a complete memory subsystem solution that also takes into account the need for high performance NoCs that support multi-channel memory subsystem architectures and integrate all of the cores in the system.”

The Sonics-Northwest Logic high throughput memory subsystem solutions where developed for a mutual customer and are now being integrated in designs by other customers as well.