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DVCon is a Worldwide Conference

December 21st, 2016

Gabe Moretti, Senior Editor

The DVCon conference has now solid traditions not only in the USA but also in Europe, India, and next year will start flowering in China.

DVCon U.S.

The conference will be held February 27 – March 2, 2017 at the DoubleTree in San Jose, California. Early registration was open and the program is available on line at  https://dvcon.org. “DVCon U.S. 2017 planning is taking shape,” commented Dennis Brophy, DVCon U.S. General Chair. “We look forward to a compelling and in-depth technical program full of engaging content that practicing design and verification engineers, managers and EDA tool suppliers have come to depend on from DVCon.” The four-day program offers attendees an Expo, two exciting standards-focused panels and numerous informative papers, tutorials and posters to choose from. Accellera Day starts the conference on Monday and will devote the entire morning to a tutorial on Accellera’s emerging Portable Stimulus standard titled “Creating Portable Stimulus Models with the Upcoming Accellera Standard,” with two afternoon tutorials: “SystemC Design and Verification – Solidifying the Abstraction above RTL” and “Introducing IEEE P1800.2 – The Next Step for UVM.”

DVCon India

This important technical event in India was held in Bangalore in September with almost 440 attendees over the two-day event. There were local start-ups participating and exhibiting for the first time, further demonstrating the local focus and interest in each conference. “DVCon India rightly promotes the four C’s: connect, contribute, collaborate, and celebrate,” stated Gaurav Jalan, DVCon India General Chair. The two-day event was inaugurated with a traditional lamp-lighting ceremony and welcome remarks by Jalan. Dr. Walden Rhines, Chairman and CEO of Mentor Graphics, and Professor Kamakoti Veezhinathan, Indian Institute of Technology Madras, delivered the keynotes.

DVCon Europe

As in previous years the conference was held in Munich, Germany. Held in October it enjoyed an increase in attendance of 20% over the previous year. Attendees of the two-day conference included representatives from 93 companies and organizations from 25 countries. Insightful keynotes were delivered by Hobson Bullman, General Manager of ARM’s Technology Services Group, and Jugen Weyer, Vice President of Automotive Sales for EMEA at NXP Semiconductors. Bob Smith, Executive Director of the ESD Alliance, gave the keynote at the gala dinner. “It’s fantastic to see this event continuing to do so well, meeting a clear need for a European forum that provides practical, detailed information on state-of-the-art development methodologies,” noted Oliver Bell, DVCon Europe General Chair. “This year’s conference was particularly exciting with three dynamic keynote speeches, overwhelming tutorial and paper submissions, and a vibrant exhibition. Now that DVCon Europe is established as the must-attend event in Europefor engineers to upgrade their skills, we are looking forward to an even larger event in 2017.”

DVCon China

During 2017 DVCon will premier as a one-day event in Shanghai on April 17, 2017. The steering committee is in the process of analyzing a number of excellent paper abstract submissions for its inaugural program.. “Ideas, networking, technical discussions, learning opportunities and exciting exhibits of new products and services. This is what DVCon China will offer to attendees,” stated Andy Liu Hongliang, DVCon China General Chair. “Many hot areas of ASIC design and verification such as UVM, Low Power, IP Reuse, Formal, Mixed-Signal, System Design and Debug Strategies will be distributed throughout the whole conference with lectures, discussions, presentations and demos.”

Siemens Acquisition of Mentor Graphics is Good for EDA

November 15th, 2016

Gabe Moretti, Senior Editor

Although Mentor has been the subject of take-over attempts in the past, the business specifics of the transactions have never been favorable to Mentor.  The acquisition by Siemens, instead, is a favorable occurrence for the third largest EDA company.  This time both companies obtain positive results from the affair.

Siemens acquires Mentor following the direction set forth in 2014 when its Vision 2020 was first discussed in public.  The 6 year plan describes steps the company should take to better position itself for the kind of world it envisions in 2020.

The Vision 2020 document calls for operational consolidation and optimization during the years 2016 and 2017.  It also selects three of its business division as critical to corporate growth.  It calls it the E-A-D system that include: Digitalization, Automation, and Electrification.

Although it is possible that Mentor technology and products may be strategic in Electrification, they are of significant importance in the other two areas: Digitalization and Automation.  Digitalization, for example, includes vehicle automation, including smart cars and vehicle to vehicle communication.  Mentor already has an important presence in the automotive industry and can help Siemens in the transition to state of the art car management by electronic systems to the innovation of new systems required by the self-driving automobile and the complete integration of the components into an intelligent systems including vehicle-to-vehicle communication.

Mentor also has experience in industrial robots and what is, in my mind, more remarkable, is that the PCB and cabling portions of Mentor, often minimized in an EDA industry dominated by the obsession of building ICs, are the parts that implement and integrate the systems in the products designed and built by third parties.

With its presence in the PCB and cabling markets, Mentor can bring additional customers to Siemens as well as insight in future marketing requirements and limitations that will serve extremely well in designing the next generation industrial robots.

Of course, Mentor will also find an increased internal market as other divisions of Siemens not part of the E-A-D triumvirate will utilize its products and services.

Siemens describes itself as an employee oriented company, so present Mentor employee should not have to fear aggressive cost cutting and consolidation.  Will Mentor change? Of course, it will adapt gradually to the new requirements and opportunities the Siemens environment will create and demand, but the key word is “gradually”.  Contrary to the acquisition of ARM by SoftBank, where the acquiring company had no previous activity in ARM’s business, Siemens has been active in EDA internally, both in its Research Lab and strong connections with university programs that originated a number of European EDA startups.  Siemens executives have an understanding of what EDA is all about and what it takes to be successful in EDA.  The result, I expect, is little interference and second guessing which translates in continuous success for Mentor for as long as they are capable of it.

Wil other EDA companies benefit from this acquisition? I tink they will.  First of all it attracts more attention to our industry by the financial community, but it also is likely to increase competition among the “big 3” forcing Cadence and Synopsys to focus more on key markets and while diversifying into related markets like optical, security, software development for example.  In addition I do not see the reason for an EDA company to enter into a business partnership with some of its customers to explore new revenue generating business models.

ARM TechCon is the Model for Future Successful Conferences

October 26th, 2016

Gabe Moretti, Senior Editor

It has become abundantly clear that corporate and consortia sponsored conferences are gaining in both popularity and usefulness over generic conferences like DAC and DesignCon.  The reason, in my opinion, is how development has changed.  The industry has moved from the ASIC era, to the integrated system era.

Instead of designing an entire system, engineers now integrate subsystems.  This has been made possible with the introduction of IP licensing and the growth of the IP industry.  From a fledging and challenging design opportunity in the early 1990’s the use of IP is now a routine function that embraces both hardware and software modules.

Now both IP vendors and EDA tools providers can offer an ecosystem that is complete to their customers, both in capability and in range of functions.  The result is that conferences like ARM TechCon provide greater utility to working engineers, than the exhibit areas of DAC or DesignCon.

Only specialized conferences like DVCon held by Accellera on three continents continue to grow, because attendees benefit from the focused topics offered.  An engineer is concerned with issues covering the integration of design and verification functions finds interesting content in DVCon, while the same engineer would have to work from advanced conference documentation to create his or her own program at times dealing with conflicting schedules.

ARM holds its own specific program within DAC.  So conference attendees can take advantage of focused curricula.  But the problem is that other companies that enhance the specific environment by collaborating with ARM, for example, cannot provide focused support, since their attention must be directed toward all possibilities available within the conference.

A design engineer attending DAC finds a plethora of activities that are of no interest, or of marginal interest, and has a harder time moving within the conference just to follow what he or she wishes to see and hear.

Professionals dealing with layout and fabrication issues, for example, would find a conference organized by a fab company dealing with its own fabrication environment, challenges, and guidelines, more interesting that a series of academic papers presented at DAC.  I believe that DAC sponsor organizations need to take into consideration the changed reality of IC and system design, not just in the material presented, but in the format it is presented in.

The significant increase in size and popularity of ARC Day from Synopsys, for example, is another indication that such workshops are more valuable than generic conferences.  The same can be said for Accellera’s DVCon conferences now held in the US, Europe, India and China.  Although design and verification issue are global, they have different flavors in certain important parts of the planet.

ARM IP users find at ARM TechCon everything they need to successfully complete a design.  Both design, verification, software integration issues are covered with a depth and spread that is not available any place else.

Kilopass Unveiled Vertical Layered Thyristor (VLT) Technology for DRAMs

October 19th, 2016

Gabe Moretti, Senior Editor

Kilopass Technology, Inc., is a leader in embedded non-volatile memory (NVM) intellectual property (IP).  Its patented technologies of one-time programmable (OTP) NVM solutions scale to advanced CMOS process geometries. They are portable to every major foundry and integrated device manufacturer (IDM), and meet market demands for increased integration, higher densities, lower cost, low-power management, better reliability and improved security.  The company has just announced a new device that potentially allows it to diversify into new markets.

According to Charlie Cheng, Kilopass’ CEO, VLT eliminates the need for DRAM refresh, is compatible with existing process technologies and offers significant other benefits including lower power, better area efficiency and compatibility.  When asked the reason for this additional corporate direction Charlie replied: “Kilopass built its reputation as the leader in one-time programmable memories,” says Charlie Cheng, Kilopass’ chief executive officer. “As the next step on our roadmap, we examined many possible devices that would not need new materials or complex process flows and found this vertical thyristor to be very compelling.  We look forward to commercializing VLT DRAM in early 2018.”

VLT Overview

Kilopass’ VLT is based on thyristor technology, a structure that is electrically equivalent to a cross-coupled pair of bipolar transistors that form a latch. The latch lends itself to memory applications since it stores values and, as opposed to current capacitor-based DRAM technology, does not require refresh. The thyristor was first invented in the 1950s and several attempts have been made to use it for the SRAM market without success.  Kilopass’ VLT is the realization of DRAM requirements based on implementing the thyristor structure vertically.

Since VLT does not require complex performance- and power-consuming refresh cycles, a VLT-based DDR4 DRAM lowers standby power by 10X when compared to conventional DRAM at the same process node. Furthermore, VLT requires fewer processing steps and is designed to be built using existing processing equipment, materials and flows.

The VLT bitcell operations and silicon measurement were completed in 2015 and shown to have excellent correlation to Kilopass’ proprietary ultra-fast TCAD simulator that is one hundred thousand times faster than a traditional TCAD simulator. The TCAD simulator enables Kilopass to predict the manufacturing windows for key process parameters, and optimize the design for any given manufacturing process.  A full macro level test chip was taped-out in May and initial silicon testing is underway.
Industry Perspective

The $50B DRAM market is being driven by strong demand in the server/cloud computing market as mobile phone and tablet market growth are slowing down and computing is moving increasingly to the cloud. The outlook for DRAM growth remains strong. In a report published in 2015, IC Insights forecasts DRAM CAGR of 9% over the period from 2014 – 2019. This growth rate shows DRAM growing faster than the total IC market.

Servers and server farms consume a tremendous amount of energy with memory being a major contributor. In an ideal world, the current generation of 20 nanometer (nm) DRAM would migrate to sub-20nm processes to deliver even lower power.

Current DRAM technology is based on the 1 transistor, 1 capacitor. The (1T1C) bitcell is difficult to scale since the smaller transistors exhibit more leakage and the smaller capacitor structure has less capacitance, resulting in the need to reduce the time between refresh intervals. Up to 20% of a 16Gb DDR DRAM’s raw bandwidth will be lost due to the increased frequency of refresh cycles, a negative for multi-core/multi-thread server CPUs that must squeeze out every bit of performance to remain competitive. The DRAM industry is in a quandary trying to increase memory performance while reducing power consumption, a tough challenge given the physics at play with the current 1T1C technology. In order to address the need for lower power consumption a new DRAM technology and architecture is needed.

Kilopass stated that its initial target markets include “PCs” and servers. I am of the old school and associate the term “PC” to personal computers.  But Kilopass uses the term to mean Portable Computing Devices so it is talking about a different market.  Kilopass expects to have test silicon by early 2017 that will confirm performance of the new VLT DRAM technology and manufacturability.   Kilopass has two primary reasons to announce the new technology over one year in advance of product delivery.  First the company is in the IP business, so it is giving itself time to look for licensees.  Secondly it thinks that the DRAM market has been stuck at 20nm. Adoption of new technology takes time, though VLT has been shown to be manufacturable. This is the right time to alert the market that there are alternative solutions, allowing time for investigation of this new technology.   Market penetration of new technology is not always assured.  Wide acceptance almost always requires a second source, especially with something so new as the VLT device.  Memories play a critical role cloud computing but a far smaller one in PC since power consumption in PC is not a widespread issue.

Interview with Pim Tuyls, President and CEO of Intrinsic-ID

October 4th, 2016

Gabe Moretti, Senior Editor

After the article on security published last week, I continued the conversation with more corporations.  The Apple vs. FBI case showed that the stakes are high and the debate is heated.  Privacy is important, not only for guarding sensitive information but for also ensuring functionality in our digital world.

I asked Pim Tuyls his impressions on security in electronics systems.

Pim:

“Often, privacy is equated with security. However, ‘integrity’, is often the more important issue. This is especially true with the Internet of Things (IoT) and autonomous systems, which rely on the inputs they receive to operate effectively.    If these inputs are not secure, how can they be trusted?  Researchers have already tricked sensors of semi-autonomous cars with imaginary objects on the road, triggering emergency braking actions.  Counterfeit sensors are already on the market.

Engineers have built in redundancy and ‘common-sense’ rules to help ensure input integrity. However, such mechanisms were built primarily for reliability, not for security. So something else is needed. Looking at the data itself is not enough. Integrity needs to be built into sensors and, more generally, all end-points.”

Chip Design: Are there ways you think could be effective in increasing security?

Pim:

“One way to do this is to append a Message Authentication Code (MAC) to each piece of data. This is essentially a short piece of information that authenticates a message or confirms that the message came from the claimed sender (its authenticity) and has not been changed in transit (its integrity). To protect against replay attacks the message is augmented with a timestamp or counter before the MAC is calculated.  Another approach to implement a MAC is based on hash functions (HMAC or Hash-based message authentication code). Hash functions such as the SHA-2 family are well-known and widely supported cryptographic primitives with efficient and compact implementation.”

Chip Design: These approaches sound easy but there are reasons they are not widely adopted?

Pim:

“First, even though an algorithm like HMAC is efficient and compact, it may still be too high of a burden on the tiny microcontrollers and sensors that are the nerves of a complex system.  Authenticating every piece of data naturally takes up resources such as processing, memory and power.  In some cases, like in-vitro medical sensors, any reduction in battery life is not acceptable. Tiny sensor modules often do not have any processing capabilities. In automotive, due to the sheer number of sensors and controllers, costs cannot be increased.”

Chip Design: It is true that many IoT devices are very cost sensitive, I said, however, over recent years there is an increasing use of more powerful, 32-bit, often ARM- based microcontrollers. Many of these now come with basic security features like crypto accelerators and memory management. So some of the issues that prevent adoption of security are quickly being eroded.

Pim continued:

“A second obstacle relates to the complex logistics of configuring such a system. HMAC relies on a secret key that is shared between the sensor and the host.  Ensuring that each sensor has a unique key and that the key is kept secret via a centralized approach creates a single point of failure and introduces large liabilities for the party that manages the keys.”

Chip Design: What could be a cost-effective solution?

Pim concluded:

“A new solution to all these issues is based on SRAM Physical Unclonable Functions (PUFs). An SRAM PUF can reliably extract a unique key from a standard SRAM circuit on a standard microcontroller or smart sensor. The key is determined by tiny manufacturing differences unique to each chip. There is no central point of failure and no liability for key loss at the manufacturer.  Furthermore, as nothing is programmed into the chip, the key cannot even be extracted through reverse engineering or other chip-level attacks.

Of course adapting a new security paradigm is not something that should be done overnight. OEMs and their suppliers are rightly taking a cautious approach. After all, the vehicle that is now being designed will still be on the road in 25 years. For industrial and medical systems, the lifecycle of a product may even be longer.

Still, with technologies like SRAM PUF the ingredients are in place to introduce the next level of security and integrity, and pave the road for fully autonomous systems. Using such technologies will not only help to enhance privacy but will also ensure a higher level of information integrity.”

This brought me back to the article where a solution using PUF was mentioned.

eSilicon Fully Automates Semiconductor IP Selection and Purchasing

September 21st, 2016

Gabe Moretti, Senior Editor

Approximately half of the area of advanced system-on-chip (SoC) designs is composed of memory IP. Optimizing the memory subsystem of an SoC requires exploration of hundreds to thousands of possible configurations to identify the optimal match for the chip’s power, performance and area (PPA) requirements. This process can take weeks and traditionally designers and architects have not been able to fully explore all the options available to them, resulting in sub-optimal memory architectures and design closure challenges.

eSilicon’s STAR Navigator tool addresses this challenge by allowing designers to choose, evaluate and procure eSilicon IP online. Now, designers can access a wide variety of memory and I/O options online to find the best configuration for each design. With the latest enhancements to STAR Navigator, designers can now get quotes for their chosen IP online and procure it by uploading a valid purchase order. Designers are now in control of specifying and purchasing the most appropriate IP for their projects.

STAR Navigator increases security of the transactions by providing one channel of communication that allows engineering, purchasing and finance to avoid misunderstandings.  BY eliminating multiple emails to different recipients, the progress of the choice of IP and its purchasing and delivery are all documented in one channel of communication.

Previously, purchasing memory IP and I/Os could be difficult to manage by the engineer. Accessing specific memory instances with a variety of options was time consuming and complex. STAR Navigator helps designers avoid complicated paperwork; find which memories will best help meet their SoC’s power, performance or area (PPA) targets; and easily isolate key data without navigating convoluted data sheets. Pre-loaded data is available to enable architects and designers to obtain immediate PPA information for their early chip planning.

STAR Navigator empowers chip architects and designers to choose the best and highly differentiated eSilicon-developed IP solutions by performing the following tasks online:

  • Generate dynamic, graphical analyses of PPA data
  • View data graphically, view in table format, or download to Microsoft Excel
  • Build and download a complete SoC memory subsystem
    • Generate and download IP front-end views
    • Make changes over time
    • Purchase the IP that best meets the needs of the design

STAR Navigator contains all eSilicon-developed IP across multiple foundries and technologies:

  • Standard and specialty memory compilers from 14nm to 180nm including CAMs, fast cache single-port SRAMs, multi-port register files, ultra-low-voltage SRAMs and pseudo two-port architectures targeted for specific market segments
  • General-purpose and specialty I/O libraries from 14nm to 180nm
  • High-bandwidth memory (HBM) Gen2 PHY in 14/16nm and 28nm
  • Foundries include Dongbu, GLOBALFOUNDRIES, LFoundry, Samsung, SMIC, TSMC and UMC

“STAR Navigator simplifies the comparison of results across multiple technologies, architectures and other characteristics and takes the guesswork out of hitting PPA targets,” said Lisa Minwell, eSilicon’s senior director, IP marketing. “This goes much, much deeper than IP portals that serve as IP catalogs. Using STAR Navigator, designers can download front-end views, run simulations in their own environments and then purchase the back-end views of the IP and I/Os that best fit their design. The choice of optimized IP is now in the hands of the designer.”

An interesting White Paper from S2C

September 6th, 2016

Gabe Moretti, Senior Editor

S2C has published a white paper on Chip Design with the title: “Choosing the best pin multiplexing method for your Multiple-FPGA partition”.  It is of particular interest to designers that use FPGA based prototyping in their development of SoC designs.

Using multiple FPGAs to prototype a large design requires solving a classic problem: the number of signals that must pass between devices is greater than the number of I/O’s pins on an FPGA. The classic solution is to use a TDM (Time Domain Multiplexing) scheme that multiplexes two or more signals over a single wire or pin.

There are two distinct types of TDM implementations: synchronous and asynchronous. In synchronous TDM the multiplexing circuitry is driven by a fast clock that is synchronous with the (user’s) design clock.

In asynchronous mode, the TDM fast clock runs completely independent of the design clocks. Although asynchronous mode is slower, it supports multiple clocks and the timing constraints are easier to meet.

The paper shows that S2C’s Prodigy Play Pro is a tool that provides design partitioning across multiple FPGAs, and offers automatic TDM insertion based on an asynchronous TDM using LVDS.   Prodigy Play Pro Combines the technique of using asynchronous LVDS TDM with a single clock cycle design, and can partition a design and perform automatic TDM insertion. The result is that the tool is able to:

1)   Optimize buses and match the LVDS resources in each bank considering such factors as trace lengths, matching impedances, and impedance continuity, and

2)   Avoid consuming FPGA design resources for the TDM circuity by taking advantage of built-in reference clocks (e.g.: IODELAY) to drive TDM clocks and resets.

Just click on the title of the white paper to read it in its entirety or go to http://www.s2cinc.com/resource-library/white-papers.

ARC Processor summit in Santa Clara

August 30th, 2016

Gabe Moretti, Senior Editor

Synopsys is holding its second ARC Processor summit on September 13 at the Santa Clara Marriott.

The full day conference will open at 9:00 for on-site registration.  Synopsys will provide complimentary parking to attendees.  To see the full program please go to:

http://www.synopsys.com/IP/ProcessorIP/ARCProcessors/Pages/arc-processor-summit-2016.aspx

The ARC processor family comprises a number of versions of the MCU adapted to specific applications as well as a general purpose version.  From my point of view, the ARC processor family offers two major advantages to its customers: the availability of a large and tested IP family directly from Synopsys, and Synopsys leading edge rapport with many foundries, including all the important ones.

The day’s events are divided into three tracks: Hardware, Software, and Embedded Vision.

Linley Gwennap, The Linley Group, will deliver the keynote.  The title is: “IoT Standards Wars: Caught in the Middle?”

Given the number of devices and the differences of applications, it is extremely important to arrive quickly to a set of agreed upon standards that can support this variety and still offer robustness, flexibility and security.

The day will conclude with a demo session and networking opportunity from 5:30 to 7:00.

Accellera Relicenses SystemC Reference Implementation under the Apache 2.0 License

August 15th, 2016

Gabe Moretti, Senior Editor

SystemC is a subset of the C language.  The C language is widely used by software developers.  The SysremC subset contains the features of C that are synthesizable, that is, they are useful to describe hardware components and designs.  SystemC is used mainly by designers working at the system level, especially when it is necessary to simulate both hardware and software concurrently.  An algorithmic description in SystemC of a hardware block generally simulates faster than the same description implemented in a traditional hardware description language.

Accellera Systems Initiative (Accellera), the electronics industry organization focused on the creation and adoption of electronic design automation (EDA) and intellectual property (IP) standards, just announced that all SystemC supplemental material, including material contributed under the SystemC Open Source License Agreement prior to the merger of the Open SystemC Initiative (OSCI) and Accellera in 2011, has now been re-licensed under the Apache License, version 2.0.

The SystemC Open Source License used for the supplemental material required a lengthier contribution process that will no longer be necessary under Apache 2.0. Other Accellera supplemental material already available under Apache 2.0 includes the Universal Verification Methodology (UVM) base class library.

“This is a significant milestone for Accellera and the SystemC community,” stated Shishpal Rawat, Accellera Systems Initiative chair. “Having all SystemC supplemental material, such as proof-of-concept and reference implementations, user guides and examples, under the widely used and industry-preferred Apache 2.0 license will make it easier for companies to more readily contribute further improvements to the supplemental material.  We have been working with all of the contributing companies over the past 18 months to ensure that we could offer SystemC users a clear path to use and improve the SystemC supplemental material, and we are very proud of the efforts of our team to make this happen.”

The supplemental material forms the basis for possible future revisions of the standard as new methods and possible extensions to the language are adopted by a significant majority of users.  It is important to keep in mind that a modeling language is a “living” language, which means that it is subject to periodic changes.  For example, the IEEE specifies that an EDA modeling language standard be reaffirmed every five years.  This institutionalizes the possibility of a new version of the standard at regular intervals.

Hardware Based Security

August 5th, 2016

Gabe Moretti, Senior Editor

If there is one thing that is obvious about the IoT market it is that security is essential.  IoT applications will be, if they are not already, invasive to the life of their users and the privacy of each individual must be preserved.  The European Union has stricter privacy laws than the US, but even in the US privacy is valued and protective.

Intrinsic-ID has published a white paper “SRAM PUF: The Secure Silicon Fingerprint” that you can read in the Whitepapers section of this emag, or you can go to www.intrinsic-id.com and read it under the “Papers” pull down.

For many years, silicon Physical Unclonable Functions (PUFs) have been seen as a promising and innovative security technology that was making steady progress. Today, Static Random-Access Memory (SRAM)-based PUFs offer a mature and viable security component that is achieving widespread adoption in commercial products. They are found in devices ranging from tiny sensors and microcontrollers to high performance Field-Programmable Gate Arrays (FPGAs) and secure elements where they protect financial transactions, user privacy, and military secrets.

Intrinsic-ID goal in publishing this paper is to show that SRAM PUF is a mature technology for embedded authentication. The behavior of an SRAM cell depends on the difference of the threshold voltages of its transistors. Even the smallest differences will be amplified and push the SRAM cell into one of two stable states. Its PUF behavior is therefore much more stable than the underlying threshold voltages, making it the most straightforward and most stable way to use the threshold voltages to build an identifier.

It turns out that every SRAM cell has its own preferred state every time the SRAM is powered resulting from the random differences in the threshold voltages. This preference is independent from the preference of the neighboring cells and independent of the location of the cell on the chip or on the wafer.

Hence an SRAM region yields a unique and random pattern of 0’s and 1’s. This pattern can be called an SRAM fingerprint since it is unique per SRAM and hence per chip. It can be used as a PUF. Keys that are derived from the SRAM PUF are not stored ‘on the chip’ but they are extracted ‘from the chip’, only when they are needed. In that way they are only present in the chip during a very short time window. When the SRAM is not powered there is no key present on the chip making the solution very secure.

Intrinsic-ID has bundled error correction, randomness extraction, security countermeasures and anti-aging techniques into a product called Quiddikey. This product extracts cryptographic keys from the SRAM PUF in a very secure manner and is available as Hardware IP (netlist), firmware (ANSI C Code), or a combination of these.

The hardware IP is small and fast – around 15K gates / 100K cycles – and connects to common interconnects like AMBA AHB, APB as well as proprietary interfaces. A Built-In Self-Test (BIST) and health checks are included in the logic. Since it is pure digital, single clock logic it synthesizes readily to any technology.  Software reference implementations start from 10KB of code and are available for major platforms like ARM, ARC, Intel and MIPS. Software implementations can be used to add PUF technology to existing products by a firmware upgrade.

I will deal with security issues in more depth in September.  In the mean time the Intrisic-ID white paper is worth your attention

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